From: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, aiqun.yu@oss.qualcomm.com,
tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com,
yijie.yang@oss.qualcomm.com,
Jingyi Wang <jingyi.wang@oss.qualcomm.com>,
Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Subject: [PATCH 17/20] arm64: dts: qcom: kaanapali: Add support for audio
Date: Wed, 24 Sep 2025 17:17:34 -0700 [thread overview]
Message-ID: <20250924-knp-dts-v1-17-3fdbc4b9e1b1@oss.qualcomm.com> (raw)
In-Reply-To: <20250924-knp-dts-v1-0-3fdbc4b9e1b1@oss.qualcomm.com>
From: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Introduce audio support for Kaanapali SoC by adding LPASS macro codecs,
TLMM pin controller and SoundWire controller with similar hardware
implementation to SM8750 platform. Also add GPR (Generic Pack Router) node
along with support for APM (Audio Process Manager) and PRM
(Proxy Resource Manager) audio services.
Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 396 ++++++++++++++++++++++++++++++++
1 file changed, 396 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 182044f61142..6aa8dedbb196 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -17,6 +17,8 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
@@ -2839,6 +2841,400 @@ compute-cb@7 {
dma-coherent;
};
};
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1001 0x80>,
+ <&apps_smmu 0x1041 0x20>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
+ };
+ };
+
+ lpass_wsa2macro: codec@6aa0000 {
+ compatible = "qcom,kaanapali-lpass-wsa-macro",
+ "qcom,sm8550-lpass-wsa-macro";
+ reg = <0x0 0x06aa0000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK
+ LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "wsa2-mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr3: soundwire@6ab0000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ab0000 0 0x10000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_wsa2macro>;
+ clock-names = "iface";
+ label = "WSA2";
+
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f
+ 0x18f 0xff 0xff 0x0f 0x0f 0xff
+ 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00
+ 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00
+ 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_rxmacro: codec@6ac0000 {
+ compatible = "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
+ reg = <0x0 0x06ac0000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK
+ LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr1: soundwire@6ad0000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ad0000 0 0x10000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_rxmacro>;
+ clock-names = "iface";
+ label = "RX";
+
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <1>;
+ qcom,dout-ports = <11>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff
+ 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_txmacro: codec@6ae0000 {
+ compatible = "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
+ reg = <0x0 0x06ae0000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_wsamacro: codec@6b00000 {
+ compatible = "qcom,kaanapali-lpass-wsa-macro",
+ "qcom,sm8550-lpass-wsa-macro";
+ reg = <0x0 0x06b00000 0x0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK
+ LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr0: soundwire@6b10000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x06b10000 0 0x10000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_wsamacro>;
+ clock-names = "iface";
+ label = "WSA";
+
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f
+ 0x18f 0xff 0xff 0x0f 0x0f 0xff
+ 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00
+ 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08
+ 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00
+ 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ swr2: soundwire@7630000 {
+ compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0";
+ reg = <0 0x07630000 0 0x10000>;
+ interrupts-extended = <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "core", "wakeup";
+ clocks = <&lpass_txmacro>;
+ clock-names = "iface";
+ label = "TX";
+
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <0>;
+ qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_vamacro: codec@7660000 {
+ compatible = "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
+ reg = <0 0x07660000 0 0x2000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk", "macro", "dcodec";
+
+ #clock-cells = <0>;
+ clock-output-names = "fsgen";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_tlmm: pinctrl@7760000 {
+ compatible = "qcom,sm8750-lpass-lpi-pinctrl",
+ "qcom,sm8650-lpass-lpi-pinctrl";
+ reg = <0 0x07760000 0 0x20000>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ dmic01_default: dmic01-default-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic23_default: dmic23-default-state {
+ clk-pins {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ wsa_swr_active: wsa-swr-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ wsa2_swr_active: wsa2-swr-active-state {
+ clk-pins {
+ pins = "gpio15";
+ function = "wsa2_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio16";
+ function = "wsa2_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
};
};
--
2.25.1
next prev parent reply other threads:[~2025-09-25 0:17 UTC|newest]
Thread overview: 135+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 0:17 [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Jingyi Wang
2025-09-25 0:17 ` [PATCH 01/20] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards Jingyi Wang
2025-10-06 9:54 ` Krzysztof Kozlowski
2025-10-06 10:24 ` Krzysztof Kozlowski
2025-10-14 5:13 ` Jingyi Wang
2025-09-25 0:17 ` [PATCH 02/20] arm64: dts: qcom: Introduce Kaanapali SoC Jingyi Wang
2025-09-25 3:22 ` Dmitry Baryshkov
2025-10-14 16:43 ` Taniya Das
2025-10-14 11:46 ` Akhil P Oommen
2025-11-04 9:04 ` Jingyi Wang
2025-11-04 12:54 ` Konrad Dybcio
2025-11-05 7:30 ` Jingyi Wang
2025-11-05 10:13 ` Konrad Dybcio
2025-11-20 6:53 ` Komal Bajaj
2025-11-20 7:22 ` Jingyi Wang
2025-09-25 0:17 ` [PATCH 03/20] arm64: dts: qcom: kaanapali: Add base MTP board Jingyi Wang
2025-09-25 3:18 ` Dmitry Baryshkov
2025-09-25 7:17 ` Aiqun(Maria) Yu
2025-09-25 9:44 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali Jingyi Wang
2025-09-25 10:56 ` Konrad Dybcio
2025-10-06 14:23 ` Krzysztof Kozlowski
2025-10-07 1:24 ` Dmitry Baryshkov
2025-10-07 1:46 ` Krzysztof Kozlowski
2025-10-08 19:04 ` Dmitry Baryshkov
2025-09-25 0:17 ` [PATCH 05/20] arm64: dts: qcom: kaanapali: Add SDC2 nodes for Kaanapali soc Jingyi Wang
2025-09-25 0:17 ` [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC Jingyi Wang
2025-09-25 1:50 ` Krzysztof Kozłowski
2025-09-25 7:39 ` Aiqun(Maria) Yu
2025-09-25 8:24 ` Krzysztof Kozłowski
2025-09-25 8:32 ` Krzysztof Kozlowski
2025-09-25 9:01 ` Krzysztof Kozlowski
2025-09-25 16:49 ` Dmitry Baryshkov
2025-09-25 18:26 ` Trilok Soni
2025-09-26 13:04 ` Konrad Dybcio
2025-09-25 13:57 ` Bjorn Andersson
2025-09-25 14:12 ` Krzysztof Kozlowski
2025-09-25 21:31 ` Rob Herring
2025-09-26 13:21 ` Konrad Dybcio
2025-09-26 14:47 ` Rob Herring
2025-09-29 6:06 ` Aiqun(Maria) Yu
2025-09-29 7:19 ` Dmitry Baryshkov
2025-09-25 3:20 ` Dmitry Baryshkov
2025-09-25 7:49 ` Aiqun(Maria) Yu
2025-09-25 9:46 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 07/20] arm64: dts: qcom: kaanapali: Add remoteprocs " Jingyi Wang
2025-09-30 17:24 ` Alexey Klimov
2025-11-04 8:59 ` Jingyi Wang
2025-11-04 10:01 ` Kumari Pallavi
2025-11-04 13:25 ` Alexey Klimov
2025-09-25 0:17 ` [PATCH 08/20] arm64: dts: qcom: Add PMK8850 pmic dtsi Jingyi Wang
2025-09-25 12:20 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 09/20] arm64: dts: qcom: Add PMH0101 " Jingyi Wang
2025-09-25 12:20 ` Konrad Dybcio
2025-10-09 13:47 ` Jishnu Prakash
2025-09-25 0:17 ` [PATCH 10/20] arm64: dts: qcom: Add PMH0104 " Jingyi Wang
2025-09-25 7:59 ` Krzysztof Kozlowski
2025-09-25 12:21 ` Konrad Dybcio
2025-09-29 6:51 ` Aiqun(Maria) Yu
2025-09-25 0:17 ` [PATCH 11/20] arm64: dts: qcom: Add PMH0110 " Jingyi Wang
2025-09-25 0:17 ` [PATCH 12/20] arm64: dts: qcom: kaanapali: Add misc features Jingyi Wang
2025-09-25 0:17 ` [PATCH 13/20] arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines Jingyi Wang
2025-09-25 12:28 ` Konrad Dybcio
2025-09-25 13:19 ` Krzysztof Kozlowski
2025-09-29 3:05 ` Jingyi Wang
2025-09-29 5:42 ` Jingyi Wang
2025-09-29 6:41 ` Aiqun(Maria) Yu
2025-09-29 13:11 ` Konstantin Ryabitsev
2025-09-30 2:14 ` Aiqun(Maria) Yu
2025-09-25 0:17 ` [PATCH 14/20] arm64: dts: qcom: kaanapali-mtp: Enable more features Jingyi Wang
2025-09-25 2:09 ` Dmitry Baryshkov
2025-09-25 9:48 ` Konrad Dybcio
2025-09-26 9:11 ` Ronak Raheja
2025-09-26 11:44 ` Konrad Dybcio
2025-09-26 13:46 ` Dmitry Baryshkov
2025-09-29 3:24 ` Jingyi Wang
2025-09-25 8:03 ` Eugen Hristev
2025-10-09 13:54 ` Jishnu Prakash
2025-10-09 14:58 ` Eugen Hristev
2025-10-09 16:28 ` Dmitry Baryshkov
2025-10-10 10:54 ` Jishnu Prakash
2025-10-10 14:02 ` Eugen Hristev
2025-10-13 16:21 ` Kamal Wadhwa
2025-09-25 0:17 ` [PATCH 15/20] arm64: dts: qcom: kaanapali-mtp: Enable modem Jingyi Wang
2025-09-25 2:10 ` Dmitry Baryshkov
2025-09-29 3:28 ` Jingyi Wang
2025-09-25 14:06 ` Bjorn Andersson
2025-09-29 3:29 ` Jingyi Wang
2025-09-25 0:17 ` [PATCH 16/20] arm64: dts: qcom: kaanapali: Add QRD board Jingyi Wang
2025-09-25 2:15 ` Dmitry Baryshkov
2025-09-29 3:29 ` Jingyi Wang
2025-09-25 0:17 ` Jingyi Wang [this message]
2025-09-25 12:30 ` [PATCH 17/20] arm64: dts: qcom: kaanapali: Add support for audio Konrad Dybcio
2025-09-25 0:17 ` [PATCH 18/20] arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC) Jingyi Wang
2025-09-25 12:30 ` Konrad Dybcio
2025-09-25 13:26 ` Krzysztof Kozlowski
2025-09-30 12:06 ` Prasad Kumpatla
2025-10-06 8:48 ` Krzysztof Kozlowski
2025-10-08 10:20 ` Konrad Dybcio
2025-10-08 10:51 ` Krzysztof Kozlowski
2025-10-08 11:30 ` Konrad Dybcio
2025-10-08 23:50 ` Krzysztof Kozlowski
2025-10-27 9:39 ` Konrad Dybcio
2025-09-25 0:17 ` [PATCH 19/20] arm64: dts: qcom: kaanapali: Add support for camss Jingyi Wang
2025-09-25 0:17 ` [PATCH 20/20] arm64: dts: qcom: kaanapali: Add iris video node Jingyi Wang
2025-10-07 2:17 ` Krzysztof Kozlowski
2025-10-08 8:30 ` Konrad Dybcio
2025-09-25 14:12 ` [PATCH 00/20] arm64: dts: qcom: Introduce Kaanapali platform device tree Rob Herring (Arm)
2025-09-25 16:51 ` Dmitry Baryshkov
2025-09-30 17:48 ` Alexey Klimov
2025-10-03 9:09 ` Prasad Kumpatla
2025-10-03 16:35 ` Alexey Klimov
2025-10-14 6:09 ` Jingyi Wang
2025-12-02 18:21 ` Pavel Machek
2025-12-02 18:33 ` Konrad Dybcio
2025-12-02 20:56 ` Pavel Machek
2025-12-03 10:34 ` Konrad Dybcio
2025-12-03 16:17 ` Pavel Machek
2025-12-03 17:31 ` Krzysztof Kozlowski
2025-12-03 18:10 ` Pavel Machek
2025-12-03 18:40 ` Krzysztof Kozlowski
2025-12-03 18:41 ` Krzysztof Kozlowski
2025-12-04 9:09 ` Pavel Machek
2025-12-04 10:41 ` Krzysztof Kozlowski
2025-12-04 11:42 ` Pavel Machek
2025-12-04 12:10 ` Krzysztof Kozlowski
2025-12-04 12:26 ` Pavel Machek
2025-12-04 9:14 ` Pavel Machek
2025-12-04 10:42 ` Krzysztof Kozlowski
2025-12-04 11:44 ` Pavel Machek
2025-12-04 12:07 ` Krzysztof Kozlowski
2025-12-04 2:41 ` Jingyi Wang
2025-12-04 8:56 ` Pavel Machek
2025-12-04 9:01 ` Krzysztof Kozlowski
2025-12-04 9:06 ` Pavel Machek
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