* [PATCH 0/2] arm64: dts: qcom: glymur: Enable SoC-wise display and eDP panel on CRD
@ 2025-09-25 15:02 Abel Vesa
2025-09-25 15:02 ` [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes Abel Vesa
2025-09-25 15:02 ` [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support Abel Vesa
0 siblings, 2 replies; 9+ messages in thread
From: Abel Vesa @ 2025-09-25 15:02 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pankaj Patil, linux-arm-msm, devicetree, linux-kernel, Abel Vesa
Start by describing the MDSS (Mobile Display SubSystem), the MDP
(Mobile Display Processor) and the 4 DisplayPort controllers it brings,
then describe the PHY used for eDP and tie up the PHY provided clocks
to the Display clock controller.
Do all this in order to enable the eDP panel the CRD comes with.
This patchset depends on:
https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com/
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
Abel Vesa (2):
arm64: dts: qcom: glymur: Describe display related nodes
arm64: dts: qcom: glymur-crd: Enable eDP display support
arch/arm64/boot/dts/qcom/glymur-crd.dts | 76 +++++
arch/arm64/boot/dts/qcom/glymur.dtsi | 492 +++++++++++++++++++++++++++++++-
2 files changed, 560 insertions(+), 8 deletions(-)
---
base-commit: 9380481900aa7bd033b3fe3616531058b0b410be
change-id: 20250925-dts-qcom-glymur-crd-add-edp-a53891f61ade
Best regards,
--
Abel Vesa <abel.vesa@linaro.org>
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes 2025-09-25 15:02 [PATCH 0/2] arm64: dts: qcom: glymur: Enable SoC-wise display and eDP panel on CRD Abel Vesa @ 2025-09-25 15:02 ` Abel Vesa 2025-09-25 17:11 ` Dmitry Baryshkov 2025-09-25 15:02 ` [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support Abel Vesa 1 sibling, 1 reply; 9+ messages in thread From: Abel Vesa @ 2025-09-25 15:02 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pankaj Patil, linux-arm-msm, devicetree, linux-kernel, Abel Vesa The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort controllers. Describe them along with display controller and the eDP PHY. Then, attach the combo PHYs link and vco_div clocks to the Display clock controller and link up the PHYs and DP endpoints in the graph. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++- 1 file changed, 484 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2698,6 +2698,7 @@ port@2 { reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2766,11 +2767,34 @@ port@2 { reg = <2>; usb_1_ss1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; }; }; }; }; + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0 0x00faac00 0 0x1d0>, + <0 0x00faa400 0 0x128>, + <0 0x00faa800 0 0x128>, + <0 0x00faa000 0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsrcc TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; reg = <0x0 0x01500000 0x0 0x17080>; @@ -3248,6 +3272,7 @@ port@2 { reg = <2>; usb_1_ss2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -3523,7 +3548,458 @@ usb_mp: usb@a400000 { dr_mode = "host"; status = "disabled"; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1de0 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0 0x0ae01000 0 0x93000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-205000000 { + opp-hz = /bits/ 64 <205000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0xc0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x9c>, + <0x0 0xaf57000 0x0 0x9c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible = "qcom,glymur-dp", "qcom,sm8650-dp"; + reg = <0x0 0xaf5c000 0x0 0x104>, + <0x0 0xaf5c200 0x0 0xc0>, + <0x0 0xaf5d000 0x0 0x770>, + <0x0 0xaf5e000 0x0 0x9c>, + <0x0 0xaf5f000 0x0 0x9c>; + + interrupts-extended = <&mdss 13>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp1_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp2: displayport-controller@af64000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af64000 0x0 0x104>, + <0x0 0x0af64200 0x0 0xc0>, + <0x0 0x0af65000 0x0 0x770>, + <0x0 0x0af66000 0x0 0x9c>, + <0x0 0x0af67000 0x0 0x9c>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp2_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp3: displayport-controller@af6c000 { + compatible = "qcom,glymur-dp"; + reg = <0 0x0af6c000 0 0x200>, + <0 0x0af6c200 0 0x200>, + <0 0x0af6d000 0 0xc00>, + <0 0x0af6e000 0 0x400>, + <0 0x0af6f000 0 0x400>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp3_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; dispcc: clock-controller@af00000 { @@ -3531,14 +4007,14 @@ dispcc: clock-controller@af00000 { reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>, <0>, /* dsi0 */ <0>, <0>, /* dsi1 */ -- 2.48.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes 2025-09-25 15:02 ` [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes Abel Vesa @ 2025-09-25 17:11 ` Dmitry Baryshkov 2025-09-26 6:50 ` Abel Vesa 0 siblings, 1 reply; 9+ messages in thread From: Dmitry Baryshkov @ 2025-09-25 17:11 UTC (permalink / raw) To: Abel Vesa Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Pankaj Patil, linux-arm-msm, devicetree, linux-kernel On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote: > The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort > controllers. Describe them along with display controller and the eDP > PHY. Then, attach the combo PHYs link and vco_div clocks to the Display > clock controller and link up the PHYs and DP endpoints in the graph. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++- > 1 file changed, 484 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi > index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644 > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi > @@ -2698,6 +2698,7 @@ port@2 { > reg = <2>; > > usb_dp_qmpphy_dp_in: endpoint { > + remote-endpoint = <&mdss_dp0_out>; > }; > }; > }; > @@ -2766,11 +2767,34 @@ port@2 { > reg = <2>; > > usb_1_ss1_qmpphy_dp_in: endpoint { > + remote-endpoint = <&mdss_dp1_out>; > }; > }; > }; > }; > > + mdss_dp3_phy: phy@faac00 { > + compatible = "qcom,glymur-dp-phy"; > + reg = <0 0x00faac00 0 0x1d0>, > + <0 0x00faa400 0 0x128>, > + <0 0x00faa800 0 0x128>, > + <0 0x00faa000 0 0x358>; > + > + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&tcsrcc TCSR_EDP_CLKREF_EN>; > + clock-names = "aux", > + "cfg_ahb", > + "ref"; > + > + power-domains = <&rpmhpd RPMHPD_MX>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > cnoc_main: interconnect@1500000 { > compatible = "qcom,glymur-cnoc-main"; > reg = <0x0 0x01500000 0x0 0x17080>; > @@ -3248,6 +3272,7 @@ port@2 { > reg = <2>; > > usb_1_ss2_qmpphy_dp_in: endpoint { > + remote-endpoint = <&mdss_dp2_out>; > }; > }; > }; > @@ -3523,7 +3548,458 @@ usb_mp: usb@a400000 { > dr_mode = "host"; > > status = "disabled"; > + }; > + > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,glymur-mdss"; > + reg = <0x0 0x0ae00000 0x0 0x1000>; > + reg-names = "mdss"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "mdp0-mem", > + "cpu-cfg"; > + > + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; > + > + iommus = <&apps_smmu 0x1de0 0x2>; > + > + interrupt-controller; > + #interrupt-cells = <1>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,glymur-dpu"; > + reg = <0 0x0ae01000 0 0x93000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", > + "vbif"; > + > + interrupts-extended = <&mdss 0>; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + operating-points-v2 = <&mdp_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + > + mdss_intf4_out: endpoint { > + remote-endpoint = <&mdss_dp1_in>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + > + mdss_intf5_out: endpoint { > + remote-endpoint = <&mdss_dp3_in>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + > + mdss_intf6_out: endpoint { > + remote-endpoint = <&mdss_dp2_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-205000000 { > + opp-hz = /bits/ 64 <205000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-337000000 { > + opp-hz = /bits/ 64 <337000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-417000000 { > + opp-hz = /bits/ 64 <417000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-532000000 { > + opp-hz = /bits/ 64 <532000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + required-opps = <&rpmhpd_opp_nom_l1>; > + }; > + }; > + }; > + > + mdss_dp0: displayport-controller@af54000 { > + compatible = "qcom,glymur-dp"; > + reg = <0x0 0xaf54000 0x0 0x104>, > + <0x0 0xaf54200 0x0 0xc0>, > + <0x0 0xaf55000 0x0 0x770>, > + <0x0 0xaf56000 0x0 0x9c>, > + <0x0 0xaf57000 0x0 0x9c>; > + > + interrupts-extended = <&mdss 12>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; No pixel1 clock? > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; No pixel1 clock? > + > + operating-points-v2 = <&mdss_dp0_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + mdss_dp0_out: endpoint { > + remote-endpoint = <&usb_dp_qmpphy_dp_in>; > + }; > + }; > + }; > + > + mdss_dp0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-192000000 { > + opp-hz = /bits/ 64 <192000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss_dp1: displayport-controller@af5c000 { > + compatible = "qcom,glymur-dp", "qcom,sm8650-dp"; This doesn't match your own bindings. WT? > + reg = <0x0 0xaf5c000 0x0 0x104>, > + <0x0 0xaf5c200 0x0 0xc0>, > + <0x0 0xaf5d000 0x0 0x770>, > + <0x0 0xaf5e000 0x0 0x9c>, > + <0x0 0xaf5f000 0x0 0x9c>; > + > + interrupts-extended = <&mdss 13>; > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; pixel1 > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; pixel1 > + > + operating-points-v2 = <&mdss_dp1_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + mdss_dp1_in: endpoint { > + remote-endpoint = <&mdss_intf4_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + mdss_dp1_out: endpoint { > + remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; > + }; > + }; > + }; > + > + mdss_dp1_opp_table: opp-table { > + compatible = "operating-points-v2"; Is it differnt from dp0 table? > + > + opp-192000000 { > + opp-hz = /bits/ 64 <192000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss_dp2: displayport-controller@af64000 { > + compatible = "qcom,glymur-dp"; > + reg = <0x0 0x0af64000 0x0 0x104>, > + <0x0 0x0af64200 0x0 0xc0>, > + <0x0 0x0af65000 0x0 0x770>, > + <0x0 0x0af66000 0x0 0x9c>, > + <0x0 0x0af67000 0x0 0x9c>; > + > + interrupts-extended = <&mdss 14>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; pixel1 clock > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; pixel1 > + > + operating-points-v2 = <&mdss_dp2_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dp2_in: endpoint { > + remote-endpoint = <&mdss_intf6_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + mdss_dp2_out: endpoint { > + remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; > + }; > + }; > + }; > + > + mdss_dp2_opp_table: opp-table { Different from dp0? > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes 2025-09-25 17:11 ` Dmitry Baryshkov @ 2025-09-26 6:50 ` Abel Vesa 2025-09-26 22:33 ` Dmitry Baryshkov 0 siblings, 1 reply; 9+ messages in thread From: Abel Vesa @ 2025-09-26 6:50 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Pankaj Patil, linux-arm-msm, devicetree, linux-kernel On 25-09-25 20:11:11, Dmitry Baryshkov wrote: > On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote: > > The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort > > controllers. Describe them along with display controller and the eDP > > PHY. Then, attach the combo PHYs link and vco_div clocks to the Display > > clock controller and link up the PHYs and DP endpoints in the graph. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++- > > 1 file changed, 484 insertions(+), 8 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi > > index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644 > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi [...] > > + mdss_dp0: displayport-controller@af54000 { > > + compatible = "qcom,glymur-dp"; > > + reg = <0x0 0xaf54000 0x0 0x104>, > > + <0x0 0xaf54200 0x0 0xc0>, > > + <0x0 0xaf55000 0x0 0x770>, > > + <0x0 0xaf56000 0x0 0x9c>, > > + <0x0 0xaf57000 0x0 0x9c>; > > + > > + interrupts-extended = <&mdss 12>; > > + > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > > No pixel1 clock? Will add it in next version. Everywhere. > > + > > + mdss_dp1: displayport-controller@af5c000 { > > + compatible = "qcom,glymur-dp", "qcom,sm8650-dp"; > > This doesn't match your own bindings. WT? Urgh. Yep, this is wrong. sm8650 compatible needs to be dropped. Will do in the next version. > > + > > + mdss_dp1_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > Is it differnt from dp0 table? Nope, they are the same. Will use the dp0 table for all controllers. Thanks for reviewing. Abel ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes 2025-09-26 6:50 ` Abel Vesa @ 2025-09-26 22:33 ` Dmitry Baryshkov 2025-09-27 12:25 ` Konrad Dybcio 0 siblings, 1 reply; 9+ messages in thread From: Dmitry Baryshkov @ 2025-09-26 22:33 UTC (permalink / raw) To: Abel Vesa Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Pankaj Patil, linux-arm-msm, devicetree, linux-kernel On Fri, Sep 26, 2025 at 09:50:22AM +0300, Abel Vesa wrote: > On 25-09-25 20:11:11, Dmitry Baryshkov wrote: > > On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote: > > > The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort > > > controllers. Describe them along with display controller and the eDP > > > PHY. Then, attach the combo PHYs link and vco_div clocks to the Display > > > clock controller and link up the PHYs and DP endpoints in the graph. > > > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > > --- > > > arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++- > > > 1 file changed, 484 insertions(+), 8 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi > > > index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644 > > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi > > [...] > > > > + mdss_dp0: displayport-controller@af54000 { > > > + compatible = "qcom,glymur-dp"; > > > + reg = <0x0 0xaf54000 0x0 0x104>, > > > + <0x0 0xaf54200 0x0 0xc0>, > > > + <0x0 0xaf55000 0x0 0x770>, > > > + <0x0 0xaf56000 0x0 0x9c>, > > > + <0x0 0xaf57000 0x0 0x9c>; > > > + > > > + interrupts-extended = <&mdss 12>; > > > + > > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > > > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > > > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > > > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > > > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > > > > No pixel1 clock? > > Will add it in next version. Everywhere. Except DP3, if I'm not mistaken. > > > > + > > > + mdss_dp1: displayport-controller@af5c000 { > > > + compatible = "qcom,glymur-dp", "qcom,sm8650-dp"; > > > > This doesn't match your own bindings. WT? > > Urgh. Yep, this is wrong. sm8650 compatible needs to be dropped. Will do > in the next version. > > > > + > > > + mdss_dp1_opp_table: opp-table { > > > + compatible = "operating-points-v2"; > > > > Is it differnt from dp0 table? > > Nope, they are the same. Will use the dp0 table for all controllers. > > Thanks for reviewing. > > Abel -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes 2025-09-26 22:33 ` Dmitry Baryshkov @ 2025-09-27 12:25 ` Konrad Dybcio 0 siblings, 0 replies; 9+ messages in thread From: Konrad Dybcio @ 2025-09-27 12:25 UTC (permalink / raw) To: Dmitry Baryshkov, Abel Vesa Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Pankaj Patil, linux-arm-msm, devicetree, linux-kernel On 9/27/25 12:33 AM, Dmitry Baryshkov wrote: > On Fri, Sep 26, 2025 at 09:50:22AM +0300, Abel Vesa wrote: >> On 25-09-25 20:11:11, Dmitry Baryshkov wrote: >>> On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote: >>>> The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort >>>> controllers. Describe them along with display controller and the eDP >>>> PHY. Then, attach the combo PHYs link and vco_div clocks to the Display >>>> clock controller and link up the PHYs and DP endpoints in the graph. >>>> >>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++- >>>> 1 file changed, 484 insertions(+), 8 deletions(-) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >>>> index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644 >>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >> >> [...] >> >>>> + mdss_dp0: displayport-controller@af54000 { >>>> + compatible = "qcom,glymur-dp"; >>>> + reg = <0x0 0xaf54000 0x0 0x104>, >>>> + <0x0 0xaf54200 0x0 0xc0>, >>>> + <0x0 0xaf55000 0x0 0x770>, >>>> + <0x0 0xaf56000 0x0 0x9c>, >>>> + <0x0 0xaf57000 0x0 0x9c>; >>>> + >>>> + interrupts-extended = <&mdss 12>; >>>> + >>>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; >>> >>> No pixel1 clock? >> >> Will add it in next version. Everywhere. > > Except DP3, if I'm not mistaken. $ rg PIXEL1 drivers/clk/qcom/dispcc-glymur.c 1841: [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1842: [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1855: [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1856: [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1869: [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1870: [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, looks like it Konrad ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support 2025-09-25 15:02 [PATCH 0/2] arm64: dts: qcom: glymur: Enable SoC-wise display and eDP panel on CRD Abel Vesa 2025-09-25 15:02 ` [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes Abel Vesa @ 2025-09-25 15:02 ` Abel Vesa 2025-09-25 16:46 ` Dmitry Baryshkov 1 sibling, 1 reply; 9+ messages in thread From: Abel Vesa @ 2025-09-25 15:02 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pankaj Patil, linux-arm-msm, devicetree, linux-kernel, Abel Vesa Enable the MDSS (Mobile Display SubSystem) along with the 3rd DisplayPort controller and its PHY in order to bring support for the panel on Glymur CRD platform. Also describe the voltage regulator needed by the eDP panel. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 76 +++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 17c8f1a4f4061303982a210b7690783c96ef80b2..1d7e69a27612aea3bfdb2eedad48d8bdb9e7dc8f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -172,6 +172,22 @@ pmic_glink_ss_in2: endpoint { }; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -536,6 +552,52 @@ vreg_l4h_e0_1p2: ldo4 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl01", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + &pmk8850_rtc { no-alarm; }; @@ -570,6 +632,20 @@ &remoteproc_soccp { }; &tlmm { + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + pcie5_default: pcie5-default-state { clkreq-n-pins { pins = "gpio153"; -- 2.48.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support 2025-09-25 15:02 ` [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support Abel Vesa @ 2025-09-25 16:46 ` Dmitry Baryshkov 2025-09-26 6:52 ` Abel Vesa 0 siblings, 1 reply; 9+ messages in thread From: Dmitry Baryshkov @ 2025-09-25 16:46 UTC (permalink / raw) To: Abel Vesa Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Pankaj Patil, linux-arm-msm, devicetree, linux-kernel On Thu, Sep 25, 2025 at 06:02:49PM +0300, Abel Vesa wrote: > Enable the MDSS (Mobile Display SubSystem) along with the 3rd > DisplayPort controller and its PHY in order to bring support > for the panel on Glymur CRD platform. Also describe the voltage > regulator needed by the eDP panel. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/glymur-crd.dts | 76 +++++++++++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > > @@ -536,6 +552,52 @@ vreg_l4h_e0_1p2: ldo4 { > }; > }; > > +&mdss { > + status = "okay"; > +}; > + > +&mdss_dp3 { > + /delete-property/ #sound-dai-cells; > + > + status = "okay"; > + > + aux-bus { > + panel { > + compatible = "samsung,atna60cl01", "samsung,atna33xc20"; > + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; > + power-supply = <&vreg_edp_3p3>; > + > + pinctrl-0 = <&edp_bl_en>; > + pinctrl-names = "default"; > + > + port { > + edp_panel_in: endpoint { > + remote-endpoint = <&mdss_dp3_out>; > + }; > + }; > + }; > + }; > + > + ports { > + port@1 { > + reg = <1>; > + mdss_dp3_out: endpoint { Define the endpoint in the SoC DTSI and just reference it here. > + data-lanes = <0 1 2 3>; > + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; > + > + remote-endpoint = <&edp_panel_in>; > + }; > + }; > + }; > +}; > + -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support 2025-09-25 16:46 ` Dmitry Baryshkov @ 2025-09-26 6:52 ` Abel Vesa 0 siblings, 0 replies; 9+ messages in thread From: Abel Vesa @ 2025-09-26 6:52 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Pankaj Patil, linux-arm-msm, devicetree, linux-kernel On 25-09-25 19:46:45, Dmitry Baryshkov wrote: > On Thu, Sep 25, 2025 at 06:02:49PM +0300, Abel Vesa wrote: > > Enable the MDSS (Mobile Display SubSystem) along with the 3rd > > DisplayPort controller and its PHY in order to bring support > > for the panel on Glymur CRD platform. Also describe the voltage > > regulator needed by the eDP panel. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/glymur-crd.dts | 76 +++++++++++++++++++++++++++++++++ > > 1 file changed, 76 insertions(+) > > > > @@ -536,6 +552,52 @@ vreg_l4h_e0_1p2: ldo4 { > > }; > > }; > > > > +&mdss { > > + status = "okay"; > > +}; > > + > > +&mdss_dp3 { > > + /delete-property/ #sound-dai-cells; > > + > > + status = "okay"; > > + > > + aux-bus { > > + panel { > > + compatible = "samsung,atna60cl01", "samsung,atna33xc20"; > > + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; > > + power-supply = <&vreg_edp_3p3>; > > + > > + pinctrl-0 = <&edp_bl_en>; > > + pinctrl-names = "default"; > > + > > + port { > > + edp_panel_in: endpoint { > > + remote-endpoint = <&mdss_dp3_out>; > > + }; > > + }; > > + }; > > + }; > > + > > + ports { > > + port@1 { > > + reg = <1>; > > + mdss_dp3_out: endpoint { > > Define the endpoint in the SoC DTSI and just reference it here. Will do. Thanks for reviewing. Abel ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-09-27 12:25 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-09-25 15:02 [PATCH 0/2] arm64: dts: qcom: glymur: Enable SoC-wise display and eDP panel on CRD Abel Vesa 2025-09-25 15:02 ` [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes Abel Vesa 2025-09-25 17:11 ` Dmitry Baryshkov 2025-09-26 6:50 ` Abel Vesa 2025-09-26 22:33 ` Dmitry Baryshkov 2025-09-27 12:25 ` Konrad Dybcio 2025-09-25 15:02 ` [PATCH 2/2] arm64: dts: qcom: glymur-crd: Enable eDP display support Abel Vesa 2025-09-25 16:46 ` Dmitry Baryshkov 2025-09-26 6:52 ` Abel Vesa
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