* [PATCH 01/24] dt-bindings: arm: qcom: Document Glymur SoC and board
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 6:32 ` [PATCH 02/24] arm64: defconfig: Enable Glymur configs for boot to shell Pankaj Patil
` (23 subsequent siblings)
24 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil
Document Glymur SoC bindings and Compute Reference Device
(CRD) board id
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 18b5ed044f9fcc4d12f4e3baa001099b6e154af7..b529a8e097a35c10e0008124467d8f6038071308 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -61,6 +61,11 @@ properties:
- qcom,apq8084-sbc
- const: qcom,apq8084
+ - items:
+ - enum:
+ - qcom,glymur-crd
+ - const: qcom,glymur
+
- items:
- enum:
- microsoft,dempsey
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* [PATCH 02/24] arm64: defconfig: Enable Glymur configs for boot to shell
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
2025-09-25 6:32 ` [PATCH 01/24] dt-bindings: arm: qcom: Document Glymur SoC and board Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 17:31 ` Dmitry Baryshkov
2025-09-25 6:32 ` [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts Pankaj Patil
` (22 subsequent siblings)
24 siblings, 1 reply; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil
The serial engine must be properly setup before kernel reaches
"init",so UART driver and its dependencies needs to be built in.
Enable its dependency clocks,interconnect and pinctrl as built-in
to boot Glymur CRD board to UART console with full USB support.
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e3a2d37bd10423b028f59dc40d6e8ee1c610d6b8..9dfec01d347b57b4eae1621a69dc06bb8ecbdff1 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -616,6 +616,7 @@ CONFIG_PINCTRL_IMX8ULP=y
CONFIG_PINCTRL_IMX91=y
CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_MSM=y
+CONFIG_PINCTRL_GLYMUR=y
CONFIG_PINCTRL_IPQ5018=y
CONFIG_PINCTRL_IPQ5332=y
CONFIG_PINCTRL_IPQ5424=y
@@ -1363,6 +1364,9 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
CONFIG_COMMON_CLK_MT8192_VDECSYS=y
CONFIG_COMMON_CLK_MT8192_VENCSYS=y
CONFIG_COMMON_CLK_QCOM=y
+CONFIG_CLK_GLYMUR_DISPCC=y
+CONFIG_CLK_GLYMUR_GCC=y
+CONFIG_CLK_GLYMUR_TCSRCC=y
CONFIG_CLK_X1E80100_CAMCC=m
CONFIG_CLK_X1E80100_DISPCC=m
CONFIG_CLK_X1E80100_GCC=y
@@ -1641,6 +1645,7 @@ CONFIG_PHY_QCOM_QMP=m
CONFIG_PHY_QCOM_QUSB2=m
CONFIG_PHY_QCOM_EUSB2_REPEATER=m
CONFIG_PHY_QCOM_M31_USB=m
+CONFIG_PHY_QCOM_M31_EUSB=m
CONFIG_PHY_QCOM_USB_HS=m
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
CONFIG_PHY_QCOM_USB_HS_28NM=m
@@ -1718,6 +1723,7 @@ CONFIG_INTERCONNECT_IMX8MN=m
CONFIG_INTERCONNECT_IMX8MQ=m
CONFIG_INTERCONNECT_IMX8MP=y
CONFIG_INTERCONNECT_QCOM=y
+CONFIG_INTERCONNECT_QCOM_GLYMUR=y
CONFIG_INTERCONNECT_QCOM_MSM8916=m
CONFIG_INTERCONNECT_QCOM_MSM8996=y
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 02/24] arm64: defconfig: Enable Glymur configs for boot to shell
2025-09-25 6:32 ` [PATCH 02/24] arm64: defconfig: Enable Glymur configs for boot to shell Pankaj Patil
@ 2025-09-25 17:31 ` Dmitry Baryshkov
2025-10-08 11:26 ` Pankaj Patil
0 siblings, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 17:31 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Thu, Sep 25, 2025 at 12:02:10PM +0530, Pankaj Patil wrote:
> The serial engine must be properly setup before kernel reaches
> "init",so UART driver and its dependencies needs to be built in.
> Enable its dependency clocks,interconnect and pinctrl as built-in
> to boot Glymur CRD board to UART console with full USB support.
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/configs/defconfig | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index e3a2d37bd10423b028f59dc40d6e8ee1c610d6b8..9dfec01d347b57b4eae1621a69dc06bb8ecbdff1 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -616,6 +616,7 @@ CONFIG_PINCTRL_IMX8ULP=y
> CONFIG_PINCTRL_IMX91=y
> CONFIG_PINCTRL_IMX93=y
> CONFIG_PINCTRL_MSM=y
> +CONFIG_PINCTRL_GLYMUR=y
> CONFIG_PINCTRL_IPQ5018=y
> CONFIG_PINCTRL_IPQ5332=y
> CONFIG_PINCTRL_IPQ5424=y
> @@ -1363,6 +1364,9 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
> CONFIG_COMMON_CLK_MT8192_VDECSYS=y
> CONFIG_COMMON_CLK_MT8192_VENCSYS=y
> CONFIG_COMMON_CLK_QCOM=y
> +CONFIG_CLK_GLYMUR_DISPCC=y
DISPCC should not be required for the UART, it can go to =m
> +CONFIG_CLK_GLYMUR_GCC=y
> +CONFIG_CLK_GLYMUR_TCSRCC=y
> CONFIG_CLK_X1E80100_CAMCC=m
> CONFIG_CLK_X1E80100_DISPCC=m
> CONFIG_CLK_X1E80100_GCC=y
> @@ -1641,6 +1645,7 @@ CONFIG_PHY_QCOM_QMP=m
> CONFIG_PHY_QCOM_QUSB2=m
> CONFIG_PHY_QCOM_EUSB2_REPEATER=m
> CONFIG_PHY_QCOM_M31_USB=m
> +CONFIG_PHY_QCOM_M31_EUSB=m
Is this also a dependency for UART?
> CONFIG_PHY_QCOM_USB_HS=m
> CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
> CONFIG_PHY_QCOM_USB_HS_28NM=m
> @@ -1718,6 +1723,7 @@ CONFIG_INTERCONNECT_IMX8MN=m
> CONFIG_INTERCONNECT_IMX8MQ=m
> CONFIG_INTERCONNECT_IMX8MP=y
> CONFIG_INTERCONNECT_QCOM=y
> +CONFIG_INTERCONNECT_QCOM_GLYMUR=y
> CONFIG_INTERCONNECT_QCOM_MSM8916=m
> CONFIG_INTERCONNECT_QCOM_MSM8996=y
> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 02/24] arm64: defconfig: Enable Glymur configs for boot to shell
2025-09-25 17:31 ` Dmitry Baryshkov
@ 2025-10-08 11:26 ` Pankaj Patil
2025-10-08 12:56 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Pankaj Patil @ 2025-10-08 11:26 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 11:01 PM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 12:02:10PM +0530, Pankaj Patil wrote:
>> The serial engine must be properly setup before kernel reaches
>> "init",so UART driver and its dependencies needs to be built in.
>> Enable its dependency clocks,interconnect and pinctrl as built-in
>> to boot Glymur CRD board to UART console with full USB support.
>>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> arch/arm64/configs/defconfig | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index e3a2d37bd10423b028f59dc40d6e8ee1c610d6b8..9dfec01d347b57b4eae1621a69dc06bb8ecbdff1 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -616,6 +616,7 @@ CONFIG_PINCTRL_IMX8ULP=y
>> CONFIG_PINCTRL_IMX91=y
>> CONFIG_PINCTRL_IMX93=y
>> CONFIG_PINCTRL_MSM=y
>> +CONFIG_PINCTRL_GLYMUR=y
>> CONFIG_PINCTRL_IPQ5018=y
>> CONFIG_PINCTRL_IPQ5332=y
>> CONFIG_PINCTRL_IPQ5424=y
>> @@ -1363,6 +1364,9 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
>> CONFIG_COMMON_CLK_MT8192_VDECSYS=y
>> CONFIG_COMMON_CLK_MT8192_VENCSYS=y
>> CONFIG_COMMON_CLK_QCOM=y
>> +CONFIG_CLK_GLYMUR_DISPCC=y
> DISPCC should not be required for the UART, it can go to =m
Sure, will mark it as =m
>> +CONFIG_CLK_GLYMUR_GCC=y
>> +CONFIG_CLK_GLYMUR_TCSRCC=y
>> CONFIG_CLK_X1E80100_CAMCC=m
>> CONFIG_CLK_X1E80100_DISPCC=m
>> CONFIG_CLK_X1E80100_GCC=y
>> @@ -1641,6 +1645,7 @@ CONFIG_PHY_QCOM_QMP=m
>> CONFIG_PHY_QCOM_QUSB2=m
>> CONFIG_PHY_QCOM_EUSB2_REPEATER=m
>> CONFIG_PHY_QCOM_M31_USB=m
>> +CONFIG_PHY_QCOM_M31_EUSB=m
> Is this also a dependency for UART?
No, it's a dependency for USB, commit message mentions
full USB support being enabled
>> CONFIG_PHY_QCOM_USB_HS=m
>> CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
>> CONFIG_PHY_QCOM_USB_HS_28NM=m
>> @@ -1718,6 +1723,7 @@ CONFIG_INTERCONNECT_IMX8MN=m
>> CONFIG_INTERCONNECT_IMX8MQ=m
>> CONFIG_INTERCONNECT_IMX8MP=y
>> CONFIG_INTERCONNECT_QCOM=y
>> +CONFIG_INTERCONNECT_QCOM_GLYMUR=y
>> CONFIG_INTERCONNECT_QCOM_MSM8916=m
>> CONFIG_INTERCONNECT_QCOM_MSM8996=y
>> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
>>
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 02/24] arm64: defconfig: Enable Glymur configs for boot to shell
2025-10-08 11:26 ` Pankaj Patil
@ 2025-10-08 12:56 ` Dmitry Baryshkov
0 siblings, 0 replies; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-08 12:56 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Wed, Oct 08, 2025 at 04:56:17PM +0530, Pankaj Patil wrote:
> On 9/25/2025 11:01 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 12:02:10PM +0530, Pankaj Patil wrote:
> >> The serial engine must be properly setup before kernel reaches
> >> "init",so UART driver and its dependencies needs to be built in.
> >> Enable its dependency clocks,interconnect and pinctrl as built-in
> >> to boot Glymur CRD board to UART console with full USB support.
> >>
> >> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> >> ---
> >> arch/arm64/configs/defconfig | 6 ++++++
> >> 1 file changed, 6 insertions(+)
> >>
> >> @@ -1641,6 +1645,7 @@ CONFIG_PHY_QCOM_QMP=m
> >> CONFIG_PHY_QCOM_QUSB2=m
> >> CONFIG_PHY_QCOM_EUSB2_REPEATER=m
> >> CONFIG_PHY_QCOM_M31_USB=m
> >> +CONFIG_PHY_QCOM_M31_EUSB=m
> > Is this also a dependency for UART?
>
> No, it's a dependency for USB, commit message mentions
> full USB support being enabled
Please rephrase the commit message to make it more obvious (yes, I
missed the USB part).
>
> >> CONFIG_PHY_QCOM_USB_HS=m
> >> CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
> >> CONFIG_PHY_QCOM_USB_HS_28NM=m
> >> @@ -1718,6 +1723,7 @@ CONFIG_INTERCONNECT_IMX8MN=m
> >> CONFIG_INTERCONNECT_IMX8MQ=m
> >> CONFIG_INTERCONNECT_IMX8MP=y
> >> CONFIG_INTERCONNECT_QCOM=y
> >> +CONFIG_INTERCONNECT_QCOM_GLYMUR=y
> >> CONFIG_INTERCONNECT_QCOM_MSM8916=m
> >> CONFIG_INTERCONNECT_QCOM_MSM8996=y
> >> CONFIG_INTERCONNECT_QCOM_OSM_L3=m
> >>
> >> --
> >> 2.34.1
> >>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
2025-09-25 6:32 ` [PATCH 01/24] dt-bindings: arm: qcom: Document Glymur SoC and board Pankaj Patil
2025-09-25 6:32 ` [PATCH 02/24] arm64: defconfig: Enable Glymur configs for boot to shell Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 10:16 ` Konrad Dybcio
` (3 more replies)
2025-09-25 6:32 ` [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines Pankaj Patil
` (21 subsequent siblings)
24 siblings, 4 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil
Introduce initial device tree support for Glymur - Qualcomm's
next-generation compute SoC and it's associated Compute Reference
Device (CRD) platform.
The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
geni UART, interrupt controller, TLMM, reserved memory,
interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
SRAM, PSCI and pmu nodes.
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
3 files changed, 1346 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 296688f7cb26550f75bce65826f234bc24110356..15f31a7d3ac4a60224c43cfa52e9cc17dc28c49f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
+dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
new file mode 100644
index 0000000000000000000000000000000000000000..a1714ec8492961b211ec761f16b39245007533b8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "glymur.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Glymur CRD";
+ compatible = "qcom,glymur-crd", "qcom,glymur";
+
+ aliases {
+ serial0 = &uart21;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
+};
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..f1c5a0cb483670e9f8044e250950693b4a015479
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -0,0 +1,1320 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/clock/qcom,glymur-gcc.h>
+#include <dt-bindings/clock/qcom,glymur-tcsr.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu0@0 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu1: cpu1@100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu2: cpu2@200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu3: cpu3@300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu4: cpu4@400 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu5: cpu5@500 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu6: cpu6@10000 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+
+ l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu7: cpu7@10100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu8: cpu8@10200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu9: cpu9@10300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu10: cpu10@10400 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10400>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu11: cpu11@10500 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10500>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu12: cpu12@20000 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20000>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+
+ l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu13: cpu13@20100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ };
+
+ cpu14: cpu14@20200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ };
+
+ cpu15: cpu15@20300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ };
+
+ cpu16: cpu16@20400 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20400>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ };
+
+ cpu17: cpu17@20500 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20500>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ core4 {
+ cpu = <&cpu4>;
+ };
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+ core1 {
+ cpu = <&cpu7>;
+ };
+ core2 {
+ cpu = <&cpu8>;
+ };
+ core3 {
+ cpu = <&cpu9>;
+ };
+ core4 {
+ cpu = <&cpu10>;
+ };
+ core5 {
+ cpu = <&cpu11>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu12>;
+ };
+ core1 {
+ cpu = <&cpu13>;
+ };
+ core2 {
+ cpu = <&cpu14>;
+ };
+ core3 {
+ cpu = <&cpu15>;
+ };
+ core4 {
+ cpu = <&cpu16>;
+ };
+ core5 {
+ cpu = <&cpu17>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-glymur", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x3000>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ llcc_lpi_mem: llcc-lpi-region@80000000 {
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ no-map;
+ };
+
+ llcc_lpi_reserved_mem: llcc-lpi-reserved-region@80900000 {
+ reg = <0x0 0x80900000 0x0 0x500000>;
+ no-map;
+ };
+
+ cpucp_log_mem: cpucp-log-region@80e00000 {
+ reg = <0x0 0x80e00000 0x0 0x40000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw-region@80e40000 {
+ reg = <0x0 0x80e40000 0x0 0x5c0000>;
+ no-map;
+ };
+
+ pdp_mem: pdp-region@81400000 {
+ reg = <0x0 0x81400000 0x0 0x100000>;
+ no-map;
+ };
+
+ tags_mem: tags-region@81500000 {
+ reg = <0x0 0x81500000 0x0 0x360000>;
+ no-map;
+ };
+
+ xbl_dtlog_mem: xbl-dtlog-region@81a00000 {
+ reg = <0x0 0x81a00000 0x0 0x40000>;
+ no-map;
+ };
+
+ xbl_ramdump_mem: xbl-ramdump-region@81a40000 {
+ reg = <0x0 0x81a40000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ no-map;
+ };
+
+ tme_crash_dump_mem: tme-crash-dump-region@81ca0000 {
+ reg = <0x0 0x81ca0000 0x0 0x40000>;
+ no-map;
+ };
+
+ tme_log_mem: tme-log-region@81ce0000 {
+ reg = <0x0 0x81ce0000 0x0 0x10000>;
+ no-map;
+ };
+
+ gpu_prr_mem: gpu-prr-region@81d00000 {
+ reg = <0x0 0x81d00000 0x0 0x10000>;
+ no-map;
+ };
+
+ tpm_control_mem: tpm-control-region@81d10000 {
+ reg = <0x0 0x81d10000 0x0 0x10000>;
+ no-map;
+ };
+
+ usb_ucsi_shared_mem: usb-ucsi-shared-region@81d20000 {
+ reg = <0x0 0x81d20000 0x0 0x10000>;
+ no-map;
+ };
+
+ pld_pep_mem: pld-pep-region@81d30000 {
+ reg = <0x0 0x81d30000 0x0 0x10000>;
+ no-map;
+ };
+
+ pld_gmu_mem: pld-gmu-region@81d40000 {
+ reg = <0x0 0x81d40000 0x0 0x10000>;
+ no-map;
+ };
+
+ pld_pdp_mem: pld-pdp-region@81d50000 {
+ reg = <0x0 0x81d50000 0x0 0x10000>;
+ no-map;
+ };
+
+ secdata_apss_mem: secdata-apss-region@81d60000 {
+ reg = <0x0 0x81d60000 0x0 0x10000>;
+ no-map;
+ };
+
+ qcskext_mem: qcskext-region@81d70000 {
+ reg = <0x0 0x81d70000 0x0 0x20000>;
+ no-map;
+ };
+
+ qup_fw_mem: qup-fw-region@81d90000 {
+ reg = <0x0 0x81d90000 0x0 0x18000>;
+ no-map;
+ };
+
+ softsku_mem: softsku-region@81da8000 {
+ reg = <0x0 0x81da8000 0x0 0x9000>;
+ no-map;
+ };
+
+ pdp_ns_shared_mem: pdp-ns-shared-region@81e00000 {
+ reg = <0x0 0x81e00000 0x0 0x200000>;
+ no-map;
+ };
+
+ acpi_ta_smem_mem: acpi-ta-smem-region@82000000 {
+ reg = <0x0 0x82000000 0x0 0x200000>;
+ no-map;
+ };
+
+ soccp_sdi_mem: soccp-sdi-region@823a0000 {
+ reg = <0x0 0x823a0000 0x0 0x40000>;
+ no-map;
+ };
+
+ lpm_violatordata_smem_mem: lpm-violatordata-smem-region@823e0000 {
+ reg = <0x0 0x823e0000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat-region@82700000 {
+ reg = <0x0 0x82700000 0x0 0x100000>;
+ no-map;
+ };
+
+ no_reclaim_xbl_scratch_buffer2_mem: no-reclaim-xbl-scratch-buffer2-region@82800000 {
+ reg = <0x0 0x82800000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ reclaimable_xbl_scratch_buffer_mem: reclaimable-xbl-scratch-buffer-region@829c0000 {
+ reg = <0x0 0x829c0000 0x0 0x1540000>;
+ no-map;
+ };
+
+ no_reclaim_xbl_scratch_buffer1_mem: no-reclaim-xbl-scratch-buffer1-region@83f00000 {
+ reg = <0x0 0x83f00000 0x0 0x100000>;
+ no-map;
+ };
+
+ ncc_mem: ncc-region@84000000 {
+ reg = <0x0 0x84000000 0x0 0x400000>;
+ no-map;
+ };
+
+ spu_secure_shared_memory_mem: spu-secure-shared-memory-region@84900000 {
+ reg = <0x0 0x84900000 0x0 0x100000>;
+ no-map;
+ };
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@84a00000 {
+ reg = <0x0 0x84a00000 0x0 0x900000>;
+ no-map;
+ };
+
+ smmu_pt_mem: smmu-pt-region@85370000 {
+ reg = <0x0 0x85370000 0x0 0xa20000>;
+ no-map;
+ };
+
+ oobdaretag_mem: oobdaretag-region@86e10000 {
+ reg = <0x0 0x86e10000 0x0 0x360000>;
+ no-map;
+ };
+
+ oob_secure_mem: oob-secure-region@87170000 {
+ reg = <0x0 0x87170000 0x0 0xbc0000>;
+ no-map;
+ };
+
+ oobdtbqc_mem: oobdtbqc-region@87d30000 {
+ reg = <0x0 0x87d30000 0x0 0x20000>;
+ no-map;
+ };
+
+ oobdtboem_mem: oobdtboem-region@87d50000 {
+ reg = <0x0 0x87d50000 0x0 0x20000>;
+ no-map;
+ };
+
+ oob_nonsecure_mem: oob-nonsecure-region@87e00000 {
+ reg = <0x0 0x87e00000 0x0 0xc00000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region-region@88a00000 {
+ reg = <0x0 0x88a00000 0x0 0x400000>;
+ no-map;
+ };
+
+ soccp_boot_mem: soccp-boot-region@88e00000 {
+ reg = <0x0 0x88e00000 0x0 0x400000>;
+ no-map;
+ };
+
+ soccp_boot_dtb_mem: soccp-boot-dtb-region@89200000 {
+ reg = <0x0 0x89200000 0x0 0x20000>;
+ no-map;
+ };
+
+ soccpdtb_mem: soccpdtb-region@892e0000 {
+ reg = <0x0 0x892e0000 0x0 0x20000>;
+ no-map;
+ };
+
+ soccp_mem: soccp-region@89300000 {
+ reg = <0x0 0x89300000 0x0 0x400000>;
+ no-map;
+ };
+
+ cvp_mem: cvp-region@89700000 {
+ reg = <0x0 0x89700000 0x0 0x700000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@89e00000 {
+ reg = <0x0 0x89e00000 0x0 0x3a00000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@8d800000 {
+ reg = <0x0 0x8d800000 0x0 0x80000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@8d900000 {
+ reg = <0x0 0x8d900000 0x0 0x4000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@91900000 {
+ reg = <0x0 0x91900000 0x0 0x80000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode-region@919fe000 {
+ reg = <0x0 0x919fe000 0x0 0x2000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@91a00000 {
+ reg = <0x0 0x91a00000 0x0 0x800000>;
+ no-map;
+ };
+
+ av1_encoder_mem: av1-encoder-region@92200000 {
+ reg = <0x0 0x92200000 0x0 0x700000>;
+ no-map;
+ };
+
+ video_mem: video-region@92900000 {
+ reg = <0x0 0x92900000 0x0 0xc00000>;
+ no-map;
+ };
+
+ reserved_mem: reserved-region@93500000 {
+ reg = <0x0 0x93500000 0x0 0xa00000>;
+ no-map;
+ };
+
+ oob_cached_heap_standalone_mem: oob-cached-heap-standalone-region@a2000000 {
+ reg = <0x0 0xa2000000 0x0 0x5000000>;
+ no-map;
+ };
+
+ bert_mem: bert-region@d6f00000 {
+ reg = <0x0 0xd6f00000 0x0 0x100000>;
+ no-map;
+ };
+
+ hyp_ac_config_mem: hyp-ac-config-region@d7000000 {
+ reg = <0x0 0xd7000000 0x0 0x19000>;
+ no-map;
+ };
+
+ xbl_sc_mem: xbl-sc-region@d7019000 {
+ reg = <0x0 0xd7019000 0x0 0x60000>;
+ no-map;
+ };
+
+ xbl_sc_reserved_mem: xbl-sc-reserved-region@d7079000 {
+ reg = <0x0 0xd7079000 0x0 0x107000>;
+ no-map;
+ };
+
+ qtee_mem: qtee-region@d7180000 {
+ reg = <0x0 0xd7180000 0x0 0x680000>;
+ no-map;
+ };
+
+ ta_mem: ta-region@d7800000 {
+ reg = <0x0 0xd7800000 0x0 0x1c00000>;
+ no-map;
+ };
+
+ tags_mem_2: tags-region-2@d9400000 {
+ reg = <0x0 0xd9400000 0x0 0x9c0000>;
+ no-map;
+ };
+
+ display_buffer_mem: display-buffer-region@f9a20000 {
+ reg = <0x0 0xf9a20000 0x0 0x2300000>;
+ no-map;
+ };
+
+ oob_nc_mdm_standalone_mode_mem: oob-nc-mdm-standalone-mode-region@fc000000 {
+ reg = <0x0 0xfc000000 0x0 0x2000000>;
+ no-map;
+ };
+
+ oob_nc_wlan_standalone_mode_mem: oob-nc-wlan-standalone-mode-region@fe000000 {
+ reg = <0x0 0xfe000000 0x0 0xc00000>;
+ no-map;
+ };
+
+ oob_nc_glink_always_mem: oob-nc-glink-always-region@fec00000 {
+ reg = <0x0 0xfec00000 0x0 0x180000>;
+ no-map;
+ };
+
+ oob_nc_glink_assisted_mode_mem: oob-nc-glink-assisted-mode-region@fed80000 {
+ reg = <0x0 0xfed80000 0x0 0x140000>;
+ no-map;
+ };
+
+ oob_nc_mdm_assisted_mode_mem: oob-nc-mdm-assisted-mode-region@feec0000 {
+ reg = <0x0 0xfeec0000 0x0 0x10000>;
+ no-map;
+ };
+
+ oob_nc_wlan_assisted_mode_mem: oob-nc-wlan-assisted-mode-region@feed0000 {
+ reg = <0x0 0xfeed0000 0x0 0x10000>;
+ no-map;
+ };
+
+ smem_mem: smem-region@ffe00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0xffe00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,glymur-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,glymur-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0 0 0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,glymur-gcc";
+ reg = <0 0x100000 0 0x1f9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ qupv3_2: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x3000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+ iommus = <&apps_smmu 0xd63 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart21: serial@894000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00894000 0x0 0x4000>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ pinctrl-0 = <&qup_uart21_default>;
+ pinctrl-names = "default";
+ };
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,glymur-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x17080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,glymur-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x6600>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,glymur-system-noc";
+ reg = <0x0 0x01680000 0x0 0x1c080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_west_anoc: interconnect@16c0000 {
+ compatible = "qcom,glymur-pcie-west-anoc";
+ reg = <0x0 0x016c0000 0x0 0xf580>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
+ };
+
+ pcie_east_anoc: interconnect@16d0000 {
+ compatible = "qcom,glymur-pcie-east-anoc";
+ reg = <0x0 0x016d0000 0x0 0xf300>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,glymur-aggre1-noc";
+ reg = <0x0 0x016e0000 0x0 0x14400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ aggre2_noc: interconnect@1720000 {
+ compatible = "qcom,glymur-aggre2-noc";
+ reg = <0x0 0x01720000 0x0 0x14400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB4_2_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ };
+
+ aggre3_noc: interconnect@1700000 {
+ compatible = "qcom,glymur-aggre3-noc";
+ reg = <0x0 0x01700000 0x0 0x1d400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ aggre4_noc: interconnect@1740000 {
+ compatible = "qcom,glymur-aggre4-noc";
+ reg = <0x0 0x01740000 0x0 0x14400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,glymur-mmss-noc";
+ reg = <0x0 0x01780000 0x0 0x5b800>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_east_slv_noc: interconnect@1900000 {
+ compatible = "qcom,glymur-pcie-east-slv-noc";
+ reg = <0x0 0x01900000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_west_slv_noc: interconnect@1920000 {
+ compatible = "qcom,glymur-pcie-west-slv-noc";
+ reg = <0x0 0x01920000 0x0 0xf180>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+
+ #hwlock-cells = <1>;
+ };
+
+ tcsrcc: clock-controller@1fd5044 {
+ compatible = "qcom,glymur-tcsr";
+ reg = <0x0 0x1fd5044 0x0 0x48>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ tcsr: syscon@1fd6000 {
+ compatible = "syscon";
+ reg = <0x0 0x1fd6000 0x0 0x20000>;
+ };
+
+ hsc_noc: interconnect@2000000 {
+ compatible = "qcom,glymur-hscnoc";
+ reg = <0x0 0x02000000 0x0 0x93a080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpiaon_noc: interconnect@7400000 {
+ compatible = "qcom,glymur-lpass-lpiaon-noc";
+ reg = <0x0 0x07400000 0x0 0x19080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpicx_noc: interconnect@7420000 {
+ compatible = "qcom,glymur-lpass-lpicx-noc";
+ reg = <0x0 0x07420000 0x0 0x44080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_ag_noc: interconnect@7e40000 {
+ compatible = "qcom,glymur-lpass-ag-noc";
+ reg = <0x0 0x07e40000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,glymur-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x10000>;
+ qcom,pdc-ranges = <0 745 51>,
+ <51 527 47>,
+ <98 609 32>,
+ <130 717 12>,
+ <142 251 5>,
+ <147 796 16>,
+ <171 4104 36>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ sram@c30f000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0 0x0c30f000 0x0 0x400>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,glymur-tlmm";
+ reg = <0x0 0x0f100000 0x0 0xf00000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 249>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart21_default: qup-uart21-default-state {
+ tx-pins {
+ pins = "gpio86";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio87";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,glymur-smmu-500",
+ "qcom,smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-coherent;
+ };
+
+ intc: interrupt-controller@17000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x17000000 0x0 0x10000>,
+ <0x0 0x17080000 0x0 0x480000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: gic-its@17040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17040000 0x0 0x40000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ watchdog@17600000 {
+ compatible = "qcom,kpss-wdt";
+ reg = <0x0 0x17600000 0x0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ timer@17810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17810000 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ frame@17811000 {
+ reg = <0x0 0x17811000 0x0 0x1000>,
+ <0x0 0x17812000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <0>;
+ };
+
+ frame@17813000 {
+ reg = <0x0 0x17813000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <1>;
+
+ status = "disabled";
+ };
+
+ frame@17815000 {
+ reg = <0x0 0x17815000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <2>;
+
+ status = "disabled";
+ };
+
+ frame@17817000 {
+ reg = <0x0 0x17817000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <3>;
+
+ status = "disabled";
+ };
+
+ frame@17819000 {
+ reg = <0x0 0x17819000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <4>;
+
+ status = "disabled";
+ };
+
+ frame@1781b000 {
+ reg = <0x0 0x1781b000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <5>;
+
+ status = "disabled";
+ };
+
+ frame@1781d000 {
+ reg = <0x0 0x1781d000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <6>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@18900000 {
+ compatible = "qcom,rpmh-rsc";
+ label = "apps_rsc";
+ reg = <0x0 0x18900000 0x0 0x10000>,
+ <0x0 0x18910000 0x0 0x10000>,
+ <0x0 0x18920000 0x0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 0>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,glymur-rpmh-clk";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ #clock-cells = <1>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,glymur-rpmhpd";
+
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ #power-domain-cells = <1>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp-48 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_d2: opp-52 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs_d0: opp-60 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_l1: opp-80 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l0: opp-144 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-336 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ nsi_noc: interconnect@1d600000 {
+ compatible = "qcom,glymur-nsinoc";
+ reg = <0x0 0x1d600000 0x0 0x14080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ oobm_ss_noc: interconnect@1f300000 {
+ compatible = "qcom,glymur-oobm-ss-noc";
+ reg = <0x0 0x1f300000 0x0 0x49a00>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ nsp_noc: interconnect@320c0000 {
+ compatible = "qcom,glymur-nsp-noc";
+ reg = <0x0 0x320c0000 0x0 0x21280>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ sram: sram@81e08000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x81e08600 0x0 0x300>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81e08600 0x300>;
+
+ cpu_scp_lpri0: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x180>;
+ };
+
+ cpu_scp_lpri1: scp-sram-section@180 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x180 0x180>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 6:32 ` [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts Pankaj Patil
@ 2025-09-25 10:16 ` Konrad Dybcio
2025-10-29 10:00 ` Taniya Das
2025-09-25 13:02 ` Marc Zyngier
` (2 subsequent siblings)
3 siblings, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:16 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> Introduce initial device tree support for Glymur - Qualcomm's
> next-generation compute SoC and it's associated Compute Reference
> Device (CRD) platform.
>
> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
> geni UART, interrupt controller, TLMM, reserved memory,
> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
> SRAM, PSCI and pmu nodes.
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
[...]
> +#include "glymur.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. Glymur CRD";
> + compatible = "qcom,glymur-crd", "qcom,glymur";
> +
> + aliases {
> + serial0 = &uart21;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
Please add a space between the comment begin/end markers and the content
> +};
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..f1c5a0cb483670e9f8044e250950693b4a015479
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -0,0 +1,1320 @@
> +// SPDX-License-Identifier: GPL-2.0-only
This is different..
[...]
> + cpu0: cpu0@0 {
"cpu@"
> + device_type = "cpu";
> + compatible = "qcom,oryon";
We've beaten this horse to death, over and over again.
This compatible is meaningless, incorrect and shall not be merged
[...]
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
Please ensure a \n between subsequent subnodes
[...]
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
compatible goes first
[...]
> + tcsrcc: clock-controller@1fd5044 {
> + compatible = "qcom,glymur-tcsr";
> + reg = <0x0 0x1fd5044 0x0 0x48>;
We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a
logical subblock (this would require adjusting the driver)
There's also a laaaarge pool of various TCSR_ registers between
the previous node and this one.. but we can leave that in case we
need to describe it in a specific way some day
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + tcsr: syscon@1fd6000 {
> + compatible = "syscon";
"syscon" alone was not allowed by the dt checker at one point..
> + reg = <0x0 0x1fd6000 0x0 0x20000>;
> + };
[...]
> + frame@17811000 {
> + reg = <0x0 0x17811000 0x0 0x1000>,
> + <0x0 0x17812000 0x0 0x1000>;
Odd spacing (more than 1 space after '=')
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 10:16 ` Konrad Dybcio
@ 2025-10-29 10:00 ` Taniya Das
2025-10-29 10:36 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Taniya Das @ 2025-10-29 10:00 UTC (permalink / raw)
To: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 3:46 PM, Konrad Dybcio wrote:
>> + tcsrcc: clock-controller@1fd5044 {
>> + compatible = "qcom,glymur-tcsr";
>> + reg = <0x0 0x1fd5044 0x0 0x48>;
> We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a
> logical subblock (this would require adjusting the driver)
>
Konrad, we encountered issues when trying to map regions beyond just the
clock reference registers. Normally, we map the entire address range of
a clock controller (CC) module in the device tree. However, for TCSRCC
where CLKREF_EN registers are located within shared modules like TCSR or
TLMM—we don't own the whole address space, and mapping the full range
can overlap with other devices.
To avoid this, we propose defining the base address as the first
register actually used, and the size to only include up to the last
register we use. This ensures we only map the relevant subblock,
preventing conflicts with other device nodes.
So want to keep the mapping same from the start of clockref clocks.
> There's also a laaaarge pool of various TCSR_ registers between
> the previous node and this one.. but we can leave that in case we
> need to describe it in a specific way some day
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-10-29 10:00 ` Taniya Das
@ 2025-10-29 10:36 ` Dmitry Baryshkov
2025-10-30 10:44 ` Taniya Das
0 siblings, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-29 10:36 UTC (permalink / raw)
To: Taniya Das
Cc: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On Wed, Oct 29, 2025 at 03:30:54PM +0530, Taniya Das wrote:
>
>
> On 9/25/2025 3:46 PM, Konrad Dybcio wrote:
> >> + tcsrcc: clock-controller@1fd5044 {
> >> + compatible = "qcom,glymur-tcsr";
> >> + reg = <0x0 0x1fd5044 0x0 0x48>;
> > We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a
> > logical subblock (this would require adjusting the driver)
> >
>
> Konrad, we encountered issues when trying to map regions beyond just the
> clock reference registers. Normally, we map the entire address range of
> a clock controller (CC) module in the device tree. However, for TCSRCC
> where CLKREF_EN registers are located within shared modules like TCSR or
> TLMM—we don't own the whole address space, and mapping the full range
> can overlap with other devices.
> To avoid this, we propose defining the base address as the first
> register actually used, and the size to only include up to the last
> register we use. This ensures we only map the relevant subblock,
> preventing conflicts with other device nodes.
Then you need to behave slightly differently: map the full range at the
basic device (TLMM, TCSR, etc.) and then create TCSRCC as a child device
to that node (and use paren't regmap to access the registers).
>
> So want to keep the mapping same from the start of clockref clocks.
>
> > There's also a laaaarge pool of various TCSR_ registers between
> > the previous node and this one.. but we can leave that in case we
> > need to describe it in a specific way some day
> >> + #clock-cells = <1>;
> >> + #reset-cells = <1>;
> >> + };
> >> +
>
> --
> Thanks,
> Taniya Das
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-10-29 10:36 ` Dmitry Baryshkov
@ 2025-10-30 10:44 ` Taniya Das
2025-10-30 11:09 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Taniya Das @ 2025-10-30 10:44 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On 10/29/2025 4:06 PM, Dmitry Baryshkov wrote:
> On Wed, Oct 29, 2025 at 03:30:54PM +0530, Taniya Das wrote:
>>
>>
>> On 9/25/2025 3:46 PM, Konrad Dybcio wrote:
>>>> + tcsrcc: clock-controller@1fd5044 {
>>>> + compatible = "qcom,glymur-tcsr";
>>>> + reg = <0x0 0x1fd5044 0x0 0x48>;
>>> We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a
>>> logical subblock (this would require adjusting the driver)
>>>
>>
>> Konrad, we encountered issues when trying to map regions beyond just the
>> clock reference registers. Normally, we map the entire address range of
>> a clock controller (CC) module in the device tree. However, for TCSRCC
>> where CLKREF_EN registers are located within shared modules like TCSR or
>> TLMM—we don't own the whole address space, and mapping the full range
>> can overlap with other devices.
>> To avoid this, we propose defining the base address as the first
>> register actually used, and the size to only include up to the last
>> register we use. This ensures we only map the relevant subblock,
>> preventing conflicts with other device nodes.
>
> Then you need to behave slightly differently: map the full range at the
> basic device (TLMM, TCSR, etc.) and then create TCSRCC as a child device
> to that node (and use paren't regmap to access the registers).
>
Dmitry, I agree that this approach is ideal. However, the current
hardware implementation isn’t consistent across multiple SoCs, which
means the driver design also needs to adapt. Given these differences, we
decided to strictly map only the range of hardware registers that are
actually used for clocks, rather than the entire module.
>>
>> So want to keep the mapping same from the start of clockref clocks.
>>
>>> There's also a laaaarge pool of various TCSR_ registers between
>>> the previous node and this one.. but we can leave that in case we
>>> need to describe it in a specific way some day
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + };
>>>> +
>>
>> --
>> Thanks,
>> Taniya Das
>>
>
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-10-30 10:44 ` Taniya Das
@ 2025-10-30 11:09 ` Dmitry Baryshkov
2025-10-30 17:10 ` Taniya Das
0 siblings, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-30 11:09 UTC (permalink / raw)
To: Taniya Das
Cc: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On Thu, 30 Oct 2025 at 12:44, Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>
>
>
> On 10/29/2025 4:06 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 29, 2025 at 03:30:54PM +0530, Taniya Das wrote:
> >>
> >>
> >> On 9/25/2025 3:46 PM, Konrad Dybcio wrote:
> >>>> + tcsrcc: clock-controller@1fd5044 {
> >>>> + compatible = "qcom,glymur-tcsr";
> >>>> + reg = <0x0 0x1fd5044 0x0 0x48>;
> >>> We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a
> >>> logical subblock (this would require adjusting the driver)
> >>>
> >>
> >> Konrad, we encountered issues when trying to map regions beyond just the
> >> clock reference registers. Normally, we map the entire address range of
> >> a clock controller (CC) module in the device tree. However, for TCSRCC
> >> where CLKREF_EN registers are located within shared modules like TCSR or
> >> TLMM—we don't own the whole address space, and mapping the full range
> >> can overlap with other devices.
> >> To avoid this, we propose defining the base address as the first
> >> register actually used, and the size to only include up to the last
> >> register we use. This ensures we only map the relevant subblock,
> >> preventing conflicts with other device nodes.
> >
> > Then you need to behave slightly differently: map the full range at the
> > basic device (TLMM, TCSR, etc.) and then create TCSRCC as a child device
> > to that node (and use paren't regmap to access the registers).
> >
>
> Dmitry, I agree that this approach is ideal. However, the current
> hardware implementation isn’t consistent across multiple SoCs, which
> means the driver design also needs to adapt. Given these differences, we
> decided to strictly map only the range of hardware registers that are
> actually used for clocks, rather than the entire module.
You are writing a driver for the platform, not a generic driver for
all the platforms.
>
> >>
> >> So want to keep the mapping same from the start of clockref clocks.
> >>
> >>> There's also a laaaarge pool of various TCSR_ registers between
> >>> the previous node and this one.. but we can leave that in case we
> >>> need to describe it in a specific way some day
> >>>> + #clock-cells = <1>;
> >>>> + #reset-cells = <1>;
> >>>> + };
> >>>> +
> >>
> >> --
> >> Thanks,
> >> Taniya Das
> >>
> >
>
> --
> Thanks,
> Taniya Das
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-10-30 11:09 ` Dmitry Baryshkov
@ 2025-10-30 17:10 ` Taniya Das
0 siblings, 0 replies; 125+ messages in thread
From: Taniya Das @ 2025-10-30 17:10 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On 10/30/2025 4:39 PM, Dmitry Baryshkov wrote:
> On Thu, 30 Oct 2025 at 12:44, Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>>
>>
>>
>> On 10/29/2025 4:06 PM, Dmitry Baryshkov wrote:
>>> On Wed, Oct 29, 2025 at 03:30:54PM +0530, Taniya Das wrote:
>>>>
>>>>
>>>> On 9/25/2025 3:46 PM, Konrad Dybcio wrote:
>>>>>> + tcsrcc: clock-controller@1fd5044 {
>>>>>> + compatible = "qcom,glymur-tcsr";
>>>>>> + reg = <0x0 0x1fd5044 0x0 0x48>;
>>>>> We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a
>>>>> logical subblock (this would require adjusting the driver)
>>>>>
>>>>
>>>> Konrad, we encountered issues when trying to map regions beyond just the
>>>> clock reference registers. Normally, we map the entire address range of
>>>> a clock controller (CC) module in the device tree. However, for TCSRCC
>>>> where CLKREF_EN registers are located within shared modules like TCSR or
>>>> TLMM—we don't own the whole address space, and mapping the full range
>>>> can overlap with other devices.
>>>> To avoid this, we propose defining the base address as the first
>>>> register actually used, and the size to only include up to the last
>>>> register we use. This ensures we only map the relevant subblock,
>>>> preventing conflicts with other device nodes.
>>>
>>> Then you need to behave slightly differently: map the full range at the
>>> basic device (TLMM, TCSR, etc.) and then create TCSRCC as a child device
>>> to that node (and use paren't regmap to access the registers).
>>>
>>
>> Dmitry, I agree that this approach is ideal. However, the current
>> hardware implementation isn’t consistent across multiple SoCs, which
>> means the driver design also needs to adapt. Given these differences, we
>> decided to strictly map only the range of hardware registers that are
>> actually used for clocks, rather than the entire module.
>
> You are writing a driver for the platform, not a generic driver for
> all the platforms.
>
I will map the logical subblock and will update the offsets in the
TCSRCC driver.
>>
>>>>
>>>> So want to keep the mapping same from the start of clockref clocks.
>>>>
>>>>> There's also a laaaarge pool of various TCSR_ registers between
>>>>> the previous node and this one.. but we can leave that in case we
>>>>> need to describe it in a specific way some day
>>>>>> + #clock-cells = <1>;
>>>>>> + #reset-cells = <1>;
>>>>>> + };
>>>>>> +
>>>>
>>>> --
>>>> Thanks,
>>>> Taniya Das
>>>>
>>>
>>
>> --
>> Thanks,
>> Taniya Das
>>
>
>
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 6:32 ` [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts Pankaj Patil
2025-09-25 10:16 ` Konrad Dybcio
@ 2025-09-25 13:02 ` Marc Zyngier
2025-10-08 11:30 ` Pankaj Patil
2025-09-25 17:44 ` Dmitry Baryshkov
2025-10-10 7:50 ` Abel Vesa
3 siblings, 1 reply; 125+ messages in thread
From: Marc Zyngier @ 2025-09-25 13:02 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Thu, 25 Sep 2025 07:32:11 +0100,
Pankaj Patil <pankaj.patil@oss.qualcomm.com> wrote:
>
> Introduce initial device tree support for Glymur - Qualcomm's
> next-generation compute SoC and it's associated Compute Reference
> Device (CRD) platform.
>
> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
> geni UART, interrupt controller, TLMM, reserved memory,
> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
> SRAM, PSCI and pmu nodes.
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
> 3 files changed, 1346 insertions(+)
>
[...]
> + intc: interrupt-controller@17000000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x17000000 0x0 0x10000>,
> + <0x0 0x17080000 0x0 0x480000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + #interrupt-cells = <3>;
> + interrupt-controller;
> +
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x40000>;
Drop these two properties. I assume that your GIC implementation is
compliant with the architecture, and doesn't need hand-holding.
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic_its: gic-its@17040000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x17040000 0x0 0x40000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
[...]
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
You are missing at one interrupt here, as the CPUs have both secure
security state and FEAT_VHE (hint: the EL2 virtual timer also has an
interrupt, usually on PPI 12).
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 13:02 ` Marc Zyngier
@ 2025-10-08 11:30 ` Pankaj Patil
0 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-10-08 11:30 UTC (permalink / raw)
To: Marc Zyngier
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 6:32 PM, Marc Zyngier wrote:
> On Thu, 25 Sep 2025 07:32:11 +0100,
> Pankaj Patil <pankaj.patil@oss.qualcomm.com> wrote:
>> Introduce initial device tree support for Glymur - Qualcomm's
>> next-generation compute SoC and it's associated Compute Reference
>> Device (CRD) platform.
>>
>> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
>> geni UART, interrupt controller, TLMM, reserved memory,
>> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
>> SRAM, PSCI and pmu nodes.
>>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
>> 3 files changed, 1346 insertions(+)
>>
> [...]
>
>> + intc: interrupt-controller@17000000 {
>> + compatible = "arm,gic-v3";
>> + reg = <0x0 0x17000000 0x0 0x10000>,
>> + <0x0 0x17080000 0x0 0x480000>;
>> +
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> +
>> + #redistributor-regions = <1>;
>> + redistributor-stride = <0x0 0x40000>;
> Drop these two properties. I assume that your GIC implementation is
> compliant with the architecture, and doesn't need hand-holding.
>
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + gic_its: gic-its@17040000 {
>> + compatible = "arm,gic-v3-its";
>> + reg = <0x0 0x17040000 0x0 0x40000>;
>> +
>> + msi-controller;
>> + #msi-cells = <1>;
>> + };
>> + };
> [...]
>
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> You are missing at one interrupt here, as the CPUs have both secure
> security state and FEAT_VHE (hint: the EL2 virtual timer also has an
> interrupt, usually on PPI 12).
>
> M.
>
Will fix both nodes
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 6:32 ` [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts Pankaj Patil
2025-09-25 10:16 ` Konrad Dybcio
2025-09-25 13:02 ` Marc Zyngier
@ 2025-09-25 17:44 ` Dmitry Baryshkov
2025-10-08 11:36 ` Pankaj Patil
2025-10-10 7:50 ` Abel Vesa
3 siblings, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 17:44 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Thu, Sep 25, 2025 at 12:02:11PM +0530, Pankaj Patil wrote:
> Introduce initial device tree support for Glymur - Qualcomm's
> next-generation compute SoC and it's associated Compute Reference
> Device (CRD) platform.
>
> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
> geni UART, interrupt controller, TLMM, reserved memory,
> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
> SRAM, PSCI and pmu nodes.
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
I think it's usually two separate patches
> 3 files changed, 1346 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 296688f7cb26550f75bce65826f234bc24110356..15f31a7d3ac4a60224c43cfa52e9cc17dc28c49f 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
> dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..a1714ec8492961b211ec761f16b39245007533b8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +
> +#include "glymur.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. Glymur CRD";
> + compatible = "qcom,glymur-crd", "qcom,glymur";
> +
> + aliases {
> + serial0 = &uart21;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
> +};
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..f1c5a0cb483670e9f8044e250950693b4a015479
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -0,0 +1,1320 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/clock/qcom,glymur-gcc.h>
> +#include <dt-bindings/clock/qcom,glymur-tcsr.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + clock-frequency = <38400000>;
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
Can we please adapt a single style here? I think, at least frequency
should go to the board file.
> + #clock-cells = <0>;
> + };
> + };
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 17:44 ` Dmitry Baryshkov
@ 2025-10-08 11:36 ` Pankaj Patil
2025-10-08 15:55 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Pankaj Patil @ 2025-10-08 11:36 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 11:14 PM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 12:02:11PM +0530, Pankaj Patil wrote:
>> Introduce initial device tree support for Glymur - Qualcomm's
>> next-generation compute SoC and it's associated Compute Reference
>> Device (CRD) platform.
>>
>> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
>> geni UART, interrupt controller, TLMM, reserved memory,
>> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
>> SRAM, PSCI and pmu nodes.
>>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
> I think it's usually two separate patches
Yes, for the next revision planning on separating patches
in a manner where this commit will have bare-bone board
dts so compilation doesn't break and singular commit
to the board dts which enables required functionality.
>> 3 files changed, 1346 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 296688f7cb26550f75bce65826f234bc24110356..15f31a7d3ac4a60224c43cfa52e9cc17dc28c49f 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..a1714ec8492961b211ec761f16b39245007533b8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> @@ -0,0 +1,25 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "glymur.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. Glymur CRD";
>> + compatible = "qcom,glymur-crd", "qcom,glymur";
>> +
>> + aliases {
>> + serial0 = &uart21;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&tlmm {
>> + gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..f1c5a0cb483670e9f8044e250950693b4a015479
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> @@ -0,0 +1,1320 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,glymur-gcc.h>
>> +#include <dt-bindings/clock/qcom,glymur-tcsr.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/dma/qcom-gpi.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interconnect/qcom,icc.h>
>> +#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +#include <dt-bindings/spmi/spmi.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>> + clocks {
>> + xo_board: xo-board {
>> + compatible = "fixed-clock";
>> + clock-frequency = <38400000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + sleep_clk: sleep-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
> Can we please adapt a single style here? I think, at least frequency
> should go to the board file.
Sure, will do.
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-10-08 11:36 ` Pankaj Patil
@ 2025-10-08 15:55 ` Dmitry Baryshkov
0 siblings, 0 replies; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-08 15:55 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Wed, Oct 08, 2025 at 05:06:16PM +0530, Pankaj Patil wrote:
> On 9/25/2025 11:14 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 12:02:11PM +0530, Pankaj Patil wrote:
> >> Introduce initial device tree support for Glymur - Qualcomm's
> >> next-generation compute SoC and it's associated Compute Reference
> >> Device (CRD) platform.
> >>
> >> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
> >> geni UART, interrupt controller, TLMM, reserved memory,
> >> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
> >> SRAM, PSCI and pmu nodes.
> >>
> >> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/Makefile | 1 +
> >> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
> >> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
> > I think it's usually two separate patches
>
> Yes, for the next revision planning on separating patches
> in a manner where this commit will have bare-bone board
> dts so compilation doesn't break and singular commit
> to the board dts which enables required functionality.
One commit for SoC.dtsi and another one for the board.dts.
>
> >> 3 files changed, 1346 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> >> index 296688f7cb26550f75bce65826f234bc24110356..15f31a7d3ac4a60224c43cfa52e9cc17dc28c49f 100644
> >> --- a/arch/arm64/boot/dts/qcom/Makefile
> >> +++ b/arch/arm64/boot/dts/qcom/Makefile
> >> @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> >> +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
> >> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> >> new file mode 100644
> >> index 0000000000000000000000000000000000000000..a1714ec8492961b211ec761f16b39245007533b8
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> >> @@ -0,0 +1,25 @@
> >> +// SPDX-License-Identifier: GPL-2.0-only
> >> +/*
> >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> >> + */
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "glymur.dtsi"
> >> +
> >> +/ {
> >> + model = "Qualcomm Technologies, Inc. Glymur CRD";
> >> + compatible = "qcom,glymur-crd", "qcom,glymur";
> >> +
> >> + aliases {
> >> + serial0 = &uart21;
> >> + };
> >> +
> >> + chosen {
> >> + stdout-path = "serial0:115200n8";
> >> + };
> >> +};
> >> +
> >> +&tlmm {
> >> + gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
> >> +};
> >> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> >> new file mode 100644
> >> index 0000000000000000000000000000000000000000..f1c5a0cb483670e9f8044e250950693b4a015479
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> >> @@ -0,0 +1,1320 @@
> >> +// SPDX-License-Identifier: GPL-2.0-only
> >> +/*
> >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> >> + */
> >> +
> >> +#include <dt-bindings/clock/qcom,glymur-gcc.h>
> >> +#include <dt-bindings/clock/qcom,glymur-tcsr.h>
> >> +#include <dt-bindings/clock/qcom,rpmh.h>
> >> +#include <dt-bindings/dma/qcom-gpi.h>
> >> +#include <dt-bindings/gpio/gpio.h>
> >> +#include <dt-bindings/interconnect/qcom,icc.h>
> >> +#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
> >> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> >> +#include <dt-bindings/power/qcom-rpmpd.h>
> >> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> >> +#include <dt-bindings/spmi/spmi.h>
> >> +
> >> +/ {
> >> + interrupt-parent = <&intc>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> +
> >> + chosen { };
> >> +
> >> + clocks {
> >> + xo_board: xo-board {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <38400000>;
> >> + #clock-cells = <0>;
> >> + };
> >> +
> >> + sleep_clk: sleep-clk {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <32000>;
> > Can we please adapt a single style here? I think, at least frequency
> > should go to the board file.
>
> Sure, will do.
>
> >> + #clock-cells = <0>;
> >> + };
> >> + };
> >> +
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
2025-09-25 6:32 ` [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts Pankaj Patil
` (2 preceding siblings ...)
2025-09-25 17:44 ` Dmitry Baryshkov
@ 2025-10-10 7:50 ` Abel Vesa
3 siblings, 0 replies; 125+ messages in thread
From: Abel Vesa @ 2025-10-10 7:50 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 25-09-25 12:02:11, Pankaj Patil wrote:
> Introduce initial device tree support for Glymur - Qualcomm's
> next-generation compute SoC and it's associated Compute Reference
> Device (CRD) platform.
>
> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
> geni UART, interrupt controller, TLMM, reserved memory,
> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
> SRAM, PSCI and pmu nodes.
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
> 3 files changed, 1346 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 296688f7cb26550f75bce65826f234bc24110356..15f31a7d3ac4a60224c43cfa52e9cc17dc28c49f 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
> dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..a1714ec8492961b211ec761f16b39245007533b8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +
> +#include "glymur.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. Glymur CRD";
> + compatible = "qcom,glymur-crd", "qcom,glymur";
> +
> + aliases {
> + serial0 = &uart21;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
> +};
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..f1c5a0cb483670e9f8044e250950693b4a015479
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -0,0 +1,1320 @@
[...]
> +
> + aggre1_noc: interconnect@16e0000 {
> + compatible = "qcom,glymur-aggre1-noc";
> + reg = <0x0 0x016e0000 0x0 0x14400>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + aggre2_noc: interconnect@1720000 {
> + compatible = "qcom,glymur-aggre2-noc";
> + reg = <0x0 0x01720000 0x0 0x14400>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB4_2_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
> + };
> +
> + aggre3_noc: interconnect@1700000 {
> + compatible = "qcom,glymur-aggre3-noc";
> + reg = <0x0 0x01700000 0x0 0x1d400>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
Nitpick: the sorting needs to be by address based, not label based.
So aggre3_noc needs to go before aggre2_noc.
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (2 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 10:18 ` Konrad Dybcio
` (2 more replies)
2025-09-25 6:32 ` [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states Pankaj Patil
` (20 subsequent siblings)
24 siblings, 3 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Jyothi Kumar Seerapu
From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Glymur.
Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
support of GPI DMA engines.
Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
2 files changed, 2936 insertions(+), 148 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index a1714ec8492961b211ec761f16b39245007533b8..4561c0b87b017cba0a1db8814123a070b37fd434 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -13,6 +13,49 @@ / {
aliases {
serial0 = &uart21;
+ serial1 = &uart14;
+ i2c0 = &i2c16;
+ i2c1 = &i2c17;
+ i2c2 = &i2c18;
+ i2c3 = &i2c19;
+ i2c4 = &i2c20;
+ i2c5 = &i2c22;
+ i2c6 = &i2c23;
+ i2c7 = &i2c8;
+ i2c8 = &i2c9;
+ i2c9 = &i2c10;
+ i2c10 = &i2c11;
+ i2c11 = &i2c12;
+ i2c12 = &i2c13;
+ i2c13 = &i2c15;
+ i2c14 = &i2c0;
+ i2c15 = &i2c1;
+ i2c16 = &i2c2;
+ i2c17 = &i2c3;
+ i2c18 = &i2c4;
+ i2c19 = &i2c5;
+ i2c20 = &i2c6;
+ spi0 = &spi16;
+ spi1 = &spi17;
+ spi2 = &spi18;
+ spi3 = &spi19;
+ spi4 = &spi20;
+ spi5 = &spi22;
+ spi6 = &spi23;
+ spi7 = &spi8;
+ spi8 = &spi9;
+ spi9 = &spi10;
+ spi10 = &spi11;
+ spi11 = &spi12;
+ spi12 = &spi13;
+ spi13 = &spi15;
+ spi14 = &spi0;
+ spi15 = &spi1;
+ spi16 = &spi2;
+ spi17 = &spi3;
+ spi18 = &spi4;
+ spi19 = &spi5;
+ spi20 = &spi6;
};
chosen {
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -707,6 +707,32 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
};
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ dma-channel-mask = <0x3f>;
+ #dma-cells = <3>;
+ iommus = <&apps_smmu 0xd76 0x0>;
+ status = "ok";
+ };
+
qupv3_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x3000>;
@@ -718,6 +744,339 @@ qupv3_2: geniqup@8c0000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ status = "ok";
+
+ i2c16: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00880000 0 0x4000>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c16_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi16: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00880000 0 0x4000>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c17: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00884000 0 0x4000>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c17_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi17: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00884000 0 0x4000>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c18: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00888000 0 0x4000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c18_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi18: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00888000 0 0x4000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c19: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0088c000 0 0x4000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c19_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi19: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0088c000 0 0x4000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart19: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0088c000 0 0x4000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ pinctrl-0 = <&qup_uart19_default>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ i2c20: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00890000 0 0x4000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c20_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi20: spi@890000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00890000 0 0x4000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c21: i2c@894000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00894000 0 0x4000>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c21_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi21: spi@894000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00894000 0 0x4000>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
uart21: serial@894000 {
compatible = "qcom,geni-debug-uart";
@@ -734,181 +1093,2551 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
pinctrl-0 = <&qup_uart21_default>;
pinctrl-names = "default";
};
- };
- cnoc_main: interconnect@1500000 {
- compatible = "qcom,glymur-cnoc-main";
- reg = <0x0 0x01500000 0x0 0x17080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ i2c22: i2c@898000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00898000 0 0x4000>;
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c22_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- config_noc: interconnect@1600000 {
- compatible = "qcom,glymur-cnoc-cfg";
- reg = <0x0 0x01600000 0x0 0x6600>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ spi22: spi@898000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00898000 0 0x4000>;
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- system_noc: interconnect@1680000 {
- compatible = "qcom,glymur-system-noc";
- reg = <0x0 0x01680000 0x0 0x1c080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ uart22: serial@898000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00898000 0 0x4000>;
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ pinctrl-0 = <&qup_uart22_default>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
- pcie_west_anoc: interconnect@16c0000 {
- compatible = "qcom,glymur-pcie-west-anoc";
- reg = <0x0 0x016c0000 0x0 0xf580>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
- };
+ i2c23: i2c@89c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0089c000 0 0x4000>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c23_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- pcie_east_anoc: interconnect@16d0000 {
- compatible = "qcom,glymur-pcie-east-anoc";
- reg = <0x0 0x016d0000 0x0 0xf300>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>;
+ spi23: spi@89c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0089c000 0 0x4000>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
- aggre1_noc: interconnect@16e0000 {
- compatible = "qcom,glymur-aggre1-noc";
- reg = <0x0 0x016e0000 0x0 0x14400>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00a00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ dma-channel-mask = <0x3f>;
+ #dma-cells = <3>;
+ iommus = <&apps_smmu 0xcb6 0x0>;
+ status = "okay";
+ };
+
+ qupv3_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x3000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+ iommus = <&apps_smmu 0xca3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "ok";
- aggre2_noc: interconnect@1720000 {
- compatible = "qcom,glymur-aggre2-noc";
- reg = <0x0 0x01720000 0x0 0x14400>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
- <&gcc GCC_AGGRE_USB4_2_AXI_CLK>,
- <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
- };
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- aggre3_noc: interconnect@1700000 {
- compatible = "qcom,glymur-aggre3-noc";
- reg = <0x0 0x01700000 0x0 0x1d400>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- aggre4_noc: interconnect@1740000 {
- compatible = "qcom,glymur-aggre4-noc";
- reg = <0x0 0x01740000 0x0 0x14400>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
- <&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
- <&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
- };
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- mmss_noc: interconnect@1780000 {
- compatible = "qcom,glymur-mmss-noc";
- reg = <0x0 0x01780000 0x0 0x5b800>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
- pcie_east_slv_noc: interconnect@1900000 {
- compatible = "qcom,glymur-pcie-east-slv-noc";
- reg = <0x0 0x01900000 0x0 0xe080>;
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart14: serial@a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a98000 0 0x4000>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ pinctrl-0 = <&qup_uart14_default>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ gpi_dma0: dma-controller@b00000 {
+ compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00b00000 0 0x60000>;
+ interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ dma-channel-mask = <0x3f>;
+ #dma-cells = <3>;
+ iommus = <&apps_smmu 0xd36 0x0>;
+ status = "ok";
+ };
+
+ qupv3_0: geniqup@bc0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00bc0000 0 0x3000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+ iommus = <&apps_smmu 0xd23 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "ok";
+
+ i2c0: i2c@b80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b80000 0 0x4000>;
+ interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@b80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b80000 0 0x4000>;
+ interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@b84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b84000 0 0x4000>;
+ interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@b84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b84000 0 0x4000>;
+ interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@b88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b88000 0 0x4000>;
+ interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@b88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b88000 0 0x4000>;
+ interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart2: serial@b88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00b88000 0 0x4000>;
+ interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ i2c3: i2c@b8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b8c000 0 0x4000>;
+ interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@b8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b8c000 0 0x4000>;
+ interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@b90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b90000 0 0x4000>;
+ interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@b90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b90000 0 0x4000>;
+ interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@b94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b94000 0 0x4000>;
+ interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@b94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b94000 0 0x4000>;
+ interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@b98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b98000 0 0x4000>;
+ interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@b98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b98000 0 0x4000>;
+ interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@b9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b9c000 0 0x4000>;
+ interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi7: spi@b9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b9c000 0 0x4000>;
+ interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,glymur-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x17080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,glymur-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x6600>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,glymur-system-noc";
+ reg = <0x0 0x01680000 0x0 0x1c080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_west_anoc: interconnect@16c0000 {
+ compatible = "qcom,glymur-pcie-west-anoc";
+ reg = <0x0 0x016c0000 0x0 0xf580>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
+ };
+
+ pcie_east_anoc: interconnect@16d0000 {
+ compatible = "qcom,glymur-pcie-east-anoc";
+ reg = <0x0 0x016d0000 0x0 0xf300>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>;
};
- pcie_west_slv_noc: interconnect@1920000 {
- compatible = "qcom,glymur-pcie-west-slv-noc";
- reg = <0x0 0x01920000 0x0 0xf180>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,glymur-aggre1-noc";
+ reg = <0x0 0x016e0000 0x0 0x14400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ aggre2_noc: interconnect@1720000 {
+ compatible = "qcom,glymur-aggre2-noc";
+ reg = <0x0 0x01720000 0x0 0x14400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB4_2_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ };
+
+ aggre3_noc: interconnect@1700000 {
+ compatible = "qcom,glymur-aggre3-noc";
+ reg = <0x0 0x01700000 0x0 0x1d400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ aggre4_noc: interconnect@1740000 {
+ compatible = "qcom,glymur-aggre4-noc";
+ reg = <0x0 0x01740000 0x0 0x14400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,glymur-mmss-noc";
+ reg = <0x0 0x01780000 0x0 0x5b800>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_east_slv_noc: interconnect@1900000 {
+ compatible = "qcom,glymur-pcie-east-slv-noc";
+ reg = <0x0 0x01900000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_west_slv_noc: interconnect@1920000 {
+ compatible = "qcom,glymur-pcie-west-slv-noc";
+ reg = <0x0 0x01920000 0x0 0xf180>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+
+ #hwlock-cells = <1>;
+ };
+
+ tcsrcc: clock-controller@1fd5044 {
+ compatible = "qcom,glymur-tcsr";
+ reg = <0x0 0x1fd5044 0x0 0x48>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ tcsr: syscon@1fd6000 {
+ compatible = "syscon";
+ reg = <0x0 0x1fd6000 0x0 0x20000>;
+ };
+
+ hsc_noc: interconnect@2000000 {
+ compatible = "qcom,glymur-hscnoc";
+ reg = <0x0 0x02000000 0x0 0x93a080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpiaon_noc: interconnect@7400000 {
+ compatible = "qcom,glymur-lpass-lpiaon-noc";
+ reg = <0x0 0x07400000 0x0 0x19080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpicx_noc: interconnect@7420000 {
+ compatible = "qcom,glymur-lpass-lpicx-noc";
+ reg = <0x0 0x07420000 0x0 0x44080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_ag_noc: interconnect@7e40000 {
+ compatible = "qcom,glymur-lpass-ag-noc";
+ reg = <0x0 0x07e40000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,glymur-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x10000>;
+ qcom,pdc-ranges = <0 745 51>,
+ <51 527 47>,
+ <98 609 32>,
+ <130 717 12>,
+ <142 251 5>,
+ <147 796 16>,
+ <171 4104 36>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ sram@c30f000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0 0x0c30f000 0x0 0x400>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,glymur-tlmm";
+ reg = <0x0 0x0f100000 0x0 0xf00000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 249>;
+ wakeup-parent = <&pdc>;
+
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio0";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio1";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio4";
+ function = "qup0_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio5";
+ function = "qup0_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio8";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio9";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio12";
+ function = "qup0_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio13";
+ function = "qup0_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio16";
+ function = "qup0_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio17";
+ function = "qup0_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio20";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio21";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio6";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio7";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio14";
+ function = "qup0_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio15";
+ function = "qup0_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio32";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio33";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio36";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio37";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio40";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio41";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio44";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio45";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio48";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio52";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio56";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio54";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio55";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c16_data_clk: qup-i2c16-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio64";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio65";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c17_data_clk: qup-i2c17-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio68";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio69";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c18_data_clk: qup-i2c18-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio72";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio73";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c19_data_clk: qup-i2c19-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio76";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio77";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c20_data_clk: qup-i2c20-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio80";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio81";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c21_data_clk: qup-i2c21-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio84";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio85";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c22_data_clk: qup-i2c22-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio88";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio89";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_i2c23_data_clk: qup-i2c23-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio80";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio81";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio3";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio0";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio1";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio2";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio7";
+ function = "qup0_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio4";
+ function = "qup0_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio5";
+ function = "qup0_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio6";
+ function = "qup0_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio11";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio8";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio9";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio10";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio15";
+ function = "qup0_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio12";
+ function = "qup0_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio13";
+ function = "qup0_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio14";
+ function = "qup0_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio19";
+ function = "qup0_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio16";
+ function = "qup0_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio17";
+ function = "qup0_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio18";
+ function = "qup0_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio23";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio20";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio21";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio22";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio5";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio6";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio7";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio4";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi7_cs: qup-spi7-cs-state {
+ pins = "gpio13";
+ function = "qup0_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
+ /* MISO, MOSI, CLK */
+ miso-pins {
+ /* MISO */
+ pins = "gpio14";
+ function = "qup0_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio15";
+ function = "qup0_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio12";
+ function = "qup0_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio35";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio32";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio33";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio34";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio39";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio36";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio37";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio38";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio43";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio40";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio41";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio42";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio47";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio44";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio45";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio46";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi12_cs: qup-spi12-cs-state {
+ pins = "gpio51";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio48";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio49";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio50";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi13_cs: qup-spi13-cs-state {
+ pins = "gpio55";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
- tcsr_mutex: hwlock@1f40000 {
- compatible = "qcom,tcsr-mutex";
- reg = <0x0 0x01f40000 0x0 0x20000>;
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio52";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
- #hwlock-cells = <1>;
- };
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio53";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
- tcsrcc: clock-controller@1fd5044 {
- compatible = "qcom,glymur-tcsr";
- reg = <0x0 0x1fd5044 0x0 0x48>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
+ clk-pins {
+ /* CLK */
+ pins = "gpio54";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
- tcsr: syscon@1fd6000 {
- compatible = "syscon";
- reg = <0x0 0x1fd6000 0x0 0x20000>;
- };
+ qup_spi14_cs: qup-spi14-cs-state {
+ pins = "gpio59";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
- hsc_noc: interconnect@2000000 {
- compatible = "qcom,glymur-hscnoc";
- reg = <0x0 0x02000000 0x0 0x93a080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio56";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio57";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
- lpass_lpiaon_noc: interconnect@7400000 {
- compatible = "qcom,glymur-lpass-lpiaon-noc";
- reg = <0x0 0x07400000 0x0 0x19080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ clk-pins {
+ /* CLK */
+ pins = "gpio58";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
- lpass_lpicx_noc: interconnect@7420000 {
- compatible = "qcom,glymur-lpass-lpicx-noc";
- reg = <0x0 0x07420000 0x0 0x44080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ qup_spi15_cs: qup-spi15-cs-state {
+ pins = "gpio53";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
- lpass_ag_noc: interconnect@7e40000 {
- compatible = "qcom,glymur-lpass-ag-noc";
- reg = <0x0 0x07e40000 0x0 0xe080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio54";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
- pdc: interrupt-controller@b220000 {
- compatible = "qcom,glymur-pdc", "qcom,pdc";
- reg = <0x0 0x0b220000 0x0 0x10000>;
- qcom,pdc-ranges = <0 745 51>,
- <51 527 47>,
- <98 609 32>,
- <130 717 12>,
- <142 251 5>,
- <147 796 16>,
- <171 4104 36>;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupt-controller;
- };
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio55";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
- sram@c30f000 {
- compatible = "qcom,rpmh-stats";
- reg = <0x0 0x0c30f000 0x0 0x400>;
- };
+ clk-pins {
+ /* CLK */
+ pins = "gpio52";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
- tlmm: pinctrl@f100000 {
- compatible = "qcom,glymur-tlmm";
- reg = <0x0 0x0f100000 0x0 0xf00000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 249>;
- wakeup-parent = <&pdc>;
+ qup_spi16_cs: qup-spi16-cs-state {
+ pins = "gpio67";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi16_data_clk: qup-spi16-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio64";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio65";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio66";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi17_cs: qup-spi17-cs-state {
+ pins = "gpio71";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi17_data_clk: qup-spi17-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio68";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio69";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio70";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi18_cs: qup-spi18-cs-state {
+ pins = "gpio75";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi18_data_clk: qup-spi18-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio72";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio73";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio74";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi19_cs: qup-spi19-cs-state {
+ pins = "gpio79";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi19_data_clk: qup-spi19-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio76";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio77";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio78";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi20_cs: qup-spi20-cs-state {
+ pins = "gpio83";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi20_data_clk: qup-spi20-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio80";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio81";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio82";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi21_cs: qup-spi21-cs-state {
+ pins = "gpio87";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi21_data_clk: qup-spi21-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio84";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio85";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio86";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi22_cs: qup-spi22-cs-state {
+ pins = "gpio91";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi22_data_clk: qup-spi22-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio88";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio89";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio90";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_spi23_cs: qup-spi23-cs-state {
+ pins = "gpio83";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi23_data_clk: qup-spi23-data-clk-state {
+ miso-pins {
+ /* MISO */
+ pins = "gpio80";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ mosi-pins {
+ /* MOSI */
+ pins = "gpio81";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ clk-pins {
+ /* CLK */
+ pins = "gpio82";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qup_uart2_default: qup-uart2-default-state {
+ tx-pins {
+ pins = "gpio10";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio11";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qup_uart14_default: qup-uart14-default-state {
+ cts-pins {
+ pins = "gpio56";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rts-pins {
+ pins = "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tx-pins {
+ pins = "gpio58";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio59";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qup_uart19_default: qup-uart19-default-state {
+ cts-pins {
+ pins = "gpio76";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rts-pins {
+ pins = "gpio77";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tx-pins {
+ pins = "gpio78";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio79";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
qup_uart21_default: qup-uart21-default-state {
tx-pins {
@@ -925,6 +3654,22 @@ rx-pins {
bias-disable;
};
};
+
+ qup_uart22_default: qup-uart22-default-state {
+ tx-pins {
+ pins = "gpio90";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio91";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
apps_smmu: iommu@15000000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-09-25 6:32 ` [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines Pankaj Patil
@ 2025-09-25 10:18 ` Konrad Dybcio
2025-09-25 17:46 ` Dmitry Baryshkov
` (2 more replies)
2025-10-11 11:06 ` Abel Vesa
2025-10-11 11:16 ` Abel Vesa
2 siblings, 3 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:18 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Jyothi Kumar Seerapu
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>
> Add device tree support for QUPv3 serial engine protocols on Glymur.
> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> support of GPI DMA engines.
>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
[...]
> + gpi_dma2: dma-controller@800000 {
> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
> + reg = <0 0x00800000 0 0x60000>;
> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <16>;
> + dma-channel-mask = <0x3f>;
> + #dma-cells = <3>;
> + iommus = <&apps_smmu 0xd76 0x0>;
> + status = "ok";
this is implied by default, drop
> + };
> +
> qupv3_2: geniqup@8c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0x0 0x008c0000 0x0 0x3000>;
> @@ -718,6 +744,339 @@ qupv3_2: geniqup@8c0000 {
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> + status = "ok";
ditto
(please resolve all occurences)
[...]
> + cnoc_main: interconnect@1500000 {
> + compatible = "qcom,glymur-cnoc-main";
> + reg = <0x0 0x01500000 0x0 0x17080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + config_noc: interconnect@1600000 {
> + compatible = "qcom,glymur-cnoc-cfg";
> + reg = <0x0 0x01600000 0x0 0x6600>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + system_noc: interconnect@1680000 {
> + compatible = "qcom,glymur-system-noc";
> + reg = <0x0 0x01680000 0x0 0x1c080>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
This diff becomes unreadable really fast.. please play with git
format-patch's --patience option
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-09-25 10:18 ` Konrad Dybcio
@ 2025-09-25 17:46 ` Dmitry Baryshkov
2025-10-15 10:28 ` Jyothi Kumar Seerapu
[not found] ` <5931e2eb-5f2d-49bb-8b9c-b49f77d7fcbf@oss.qualcomm.com>
2 siblings, 0 replies; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 17:46 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Jyothi Kumar Seerapu
On Thu, Sep 25, 2025 at 12:18:29PM +0200, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
> > From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> >
> > Add device tree support for QUPv3 serial engine protocols on Glymur.
> > Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> > support of GPI DMA engines.
> >
> > Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + gpi_dma2: dma-controller@800000 {
> > + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
> > + reg = <0 0x00800000 0 0x60000>;
> > + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-channels = <16>;
> > + dma-channel-mask = <0x3f>;
> > + #dma-cells = <3>;
> > + iommus = <&apps_smmu 0xd76 0x0>;
> > + status = "ok";
>
> this is implied by default, drop
>
> > + };
> > +
> > qupv3_2: geniqup@8c0000 {
> > compatible = "qcom,geni-se-qup";
> > reg = <0x0 0x008c0000 0x0 0x3000>;
> > @@ -718,6 +744,339 @@ qupv3_2: geniqup@8c0000 {
> > #address-cells = <2>;
> > #size-cells = <2>;
> > ranges;
> > + status = "ok";
>
> ditto
>
> (please resolve all occurences)
>
> [...]
>
> > + cnoc_main: interconnect@1500000 {
> > + compatible = "qcom,glymur-cnoc-main";
> > + reg = <0x0 0x01500000 0x0 0x17080>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + #interconnect-cells = <2>;
> > + };
> > +
> > + config_noc: interconnect@1600000 {
> > + compatible = "qcom,glymur-cnoc-cfg";
> > + reg = <0x0 0x01600000 0x0 0x6600>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + #interconnect-cells = <2>;
> > + };
> > +
> > + system_noc: interconnect@1680000 {
> > + compatible = "qcom,glymur-system-noc";
> > + reg = <0x0 0x01680000 0x0 0x1c080>;
> > + qcom,bcm-voters = <&apps_bcm_voter>;
> > + #interconnect-cells = <2>;
> > + };
>
> This diff becomes unreadable really fast.. please play with git
> format-patch's --patience option
That comes as a price of split. I'd totally suggest a bigger chunks of
devices.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-09-25 10:18 ` Konrad Dybcio
2025-09-25 17:46 ` Dmitry Baryshkov
@ 2025-10-15 10:28 ` Jyothi Kumar Seerapu
2025-10-15 13:33 ` Dmitry Baryshkov
2025-10-20 11:54 ` Konrad Dybcio
[not found] ` <5931e2eb-5f2d-49bb-8b9c-b49f77d7fcbf@oss.qualcomm.com>
2 siblings, 2 replies; 125+ messages in thread
From: Jyothi Kumar Seerapu @ 2025-10-15 10:28 UTC (permalink / raw)
To: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 3:48 PM, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>
>> Add device tree support for QUPv3 serial engine protocols on Glymur.
>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
>> support of GPI DMA engines.
>>
>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + gpi_dma2: dma-controller@800000 {
>> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
>> + reg = <0 0x00800000 0 0x60000>;
>> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-channels = <16>;
>> + dma-channel-mask = <0x3f>;
>> + #dma-cells = <3>;
>> + iommus = <&apps_smmu 0xd76 0x0>;
>> + status = "ok";
>
> this is implied by default, drop
Hi Konard,
Do you mean we should remove the status property for all QUPs and
GPI_DMAs from the common device tree (SOC) and enable them only in the
board-specific device tree files?
>
>> + };
>> +
>> qupv3_2: geniqup@8c0000 {
>> compatible = "qcom,geni-se-qup";
>> reg = <0x0 0x008c0000 0x0 0x3000>;
>> @@ -718,6 +744,339 @@ qupv3_2: geniqup@8c0000 {
>> #address-cells = <2>;
>> #size-cells = <2>;
>> ranges;
>> + status = "ok";
>
> ditto
>
> (please resolve all occurences)
>
> [...]
>
>> + cnoc_main: interconnect@1500000 {
>> + compatible = "qcom,glymur-cnoc-main";
>> + reg = <0x0 0x01500000 0x0 0x17080>;
>> + qcom,bcm-voters = <&apps_bcm_voter>;
>> + #interconnect-cells = <2>;
>> + };
>> +
>> + config_noc: interconnect@1600000 {
>> + compatible = "qcom,glymur-cnoc-cfg";
>> + reg = <0x0 0x01600000 0x0 0x6600>;
>> + qcom,bcm-voters = <&apps_bcm_voter>;
>> + #interconnect-cells = <2>;
>> + };
>> +
>> + system_noc: interconnect@1680000 {
>> + compatible = "qcom,glymur-system-noc";
>> + reg = <0x0 0x01680000 0x0 0x1c080>;
>> + qcom,bcm-voters = <&apps_bcm_voter>;
>> + #interconnect-cells = <2>;
>> + };
>
> This diff becomes unreadable really fast.. please play with git
> format-patch's --patience option
>
> Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-15 10:28 ` Jyothi Kumar Seerapu
@ 2025-10-15 13:33 ` Dmitry Baryshkov
2025-10-15 14:12 ` Jyothi Kumar Seerapu
2025-10-20 11:54 ` Konrad Dybcio
1 sibling, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-15 13:33 UTC (permalink / raw)
To: Jyothi Kumar Seerapu
Cc: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On Wed, Oct 15, 2025 at 03:58:31PM +0530, Jyothi Kumar Seerapu wrote:
>
>
> On 9/25/2025 3:48 PM, Konrad Dybcio wrote:
> > On 9/25/25 8:32 AM, Pankaj Patil wrote:
> > > From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> > >
> > > Add device tree support for QUPv3 serial engine protocols on Glymur.
> > > Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> > > support of GPI DMA engines.
> > >
> > > Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > ---
> >
> > [...]
> >
> > > + gpi_dma2: dma-controller@800000 {
> > > + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
> > > + reg = <0 0x00800000 0 0x60000>;
> > > + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
> > > + dma-channels = <16>;
> > > + dma-channel-mask = <0x3f>;
> > > + #dma-cells = <3>;
> > > + iommus = <&apps_smmu 0xd76 0x0>;
> > > + status = "ok";
> >
> > this is implied by default, drop
>
> Hi Konard,
>
> Do you mean we should remove the status property for all QUPs and GPI_DMAs
> from the common device tree (SOC) and enable them only in the board-specific
> device tree files?
Could you please check how it is done for all other platforms?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-15 13:33 ` Dmitry Baryshkov
@ 2025-10-15 14:12 ` Jyothi Kumar Seerapu
2025-10-15 19:53 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Jyothi Kumar Seerapu @ 2025-10-15 14:12 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On 10/15/2025 7:03 PM, Dmitry Baryshkov wrote:
> On Wed, Oct 15, 2025 at 03:58:31PM +0530, Jyothi Kumar Seerapu wrote:
>>
>>
>> On 9/25/2025 3:48 PM, Konrad Dybcio wrote:
>>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>>>
>>>> Add device tree support for QUPv3 serial engine protocols on Glymur.
>>>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
>>>> support of GPI DMA engines.
>>>>
>>>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>>> ---
>>>
>>> [...]
>>>
>>>> + gpi_dma2: dma-controller@800000 {
>>>> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
>>>> + reg = <0 0x00800000 0 0x60000>;
>>>> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
>>>> + dma-channels = <16>;
>>>> + dma-channel-mask = <0x3f>;
>>>> + #dma-cells = <3>;
>>>> + iommus = <&apps_smmu 0xd76 0x0>;
>>>> + status = "ok";
>>>
>>> this is implied by default, drop
>>
>> Hi Konard,
>>
>> Do you mean we should remove the status property for all QUPs and GPI_DMAs
>> from the common device tree (SOC) and enable them only in the board-specific
>> device tree files?
>
> Could you please check how it is done for all other platforms?
In other platforms, the status is set to 'disabled' in the SoC device
tree file and enabled in the board-specific device tree files.
I believe it's fine to make the same change here.
>
>
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-15 14:12 ` Jyothi Kumar Seerapu
@ 2025-10-15 19:53 ` Dmitry Baryshkov
0 siblings, 0 replies; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-15 19:53 UTC (permalink / raw)
To: Jyothi Kumar Seerapu
Cc: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On Wed, 15 Oct 2025 at 17:12, Jyothi Kumar Seerapu
<jyothi.seerapu@oss.qualcomm.com> wrote:
>
>
>
> On 10/15/2025 7:03 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 15, 2025 at 03:58:31PM +0530, Jyothi Kumar Seerapu wrote:
> >>
> >>
> >> On 9/25/2025 3:48 PM, Konrad Dybcio wrote:
> >>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
> >>>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> >>>>
> >>>> Add device tree support for QUPv3 serial engine protocols on Glymur.
> >>>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> >>>> support of GPI DMA engines.
> >>>>
> >>>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> >>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> >>>> ---
> >>>
> >>> [...]
> >>>
> >>>> + gpi_dma2: dma-controller@800000 {
> >>>> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
> >>>> + reg = <0 0x00800000 0 0x60000>;
> >>>> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
> >>>> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
> >>>> + dma-channels = <16>;
> >>>> + dma-channel-mask = <0x3f>;
> >>>> + #dma-cells = <3>;
> >>>> + iommus = <&apps_smmu 0xd76 0x0>;
> >>>> + status = "ok";
> >>>
> >>> this is implied by default, drop
> >>
> >> Hi Konard,
> >>
> >> Do you mean we should remove the status property for all QUPs and GPI_DMAs
> >> from the common device tree (SOC) and enable them only in the board-specific
> >> device tree files?
> >
> > Could you please check how it is done for all other platforms?
> In other platforms, the status is set to 'disabled' in the SoC device
> tree file and enabled in the board-specific device tree files.
> I believe it's fine to make the same change here.
Before implementing something, please, always check how others did it
before you and ask if you really need to deviate from the existing
solutions.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-15 10:28 ` Jyothi Kumar Seerapu
2025-10-15 13:33 ` Dmitry Baryshkov
@ 2025-10-20 11:54 ` Konrad Dybcio
1 sibling, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-20 11:54 UTC (permalink / raw)
To: Jyothi Kumar Seerapu, Pankaj Patil, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/15/25 12:28 PM, Jyothi Kumar Seerapu wrote:
>
>
> On 9/25/2025 3:48 PM, Konrad Dybcio wrote:
>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>>
>>> Add device tree support for QUPv3 serial engine protocols on Glymur.
>>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
>>> support of GPI DMA engines.
>>>
>>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + gpi_dma2: dma-controller@800000 {
>>> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
>>> + reg = <0 0x00800000 0 0x60000>;
>>> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
>>> + dma-channels = <16>;
>>> + dma-channel-mask = <0x3f>;
>>> + #dma-cells = <3>;
>>> + iommus = <&apps_smmu 0xd76 0x0>;
>>> + status = "ok";
>>
>> this is implied by default, drop
>
> Hi Konard,
>
> Do you mean we should remove the status property for all QUPs and GPI_DMAs from the common device tree (SOC) and enable them only in the board-specific device tree files?
Nodes that are not disabled are enabled (i.e. status = "okay" as part
of the initial definition is superfluous)
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
[parent not found: <5931e2eb-5f2d-49bb-8b9c-b49f77d7fcbf@oss.qualcomm.com>]
* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
[not found] ` <5931e2eb-5f2d-49bb-8b9c-b49f77d7fcbf@oss.qualcomm.com>
@ 2025-10-30 10:56 ` Konrad Dybcio
0 siblings, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-30 10:56 UTC (permalink / raw)
To: Jyothi Kumar Seerapu, Pankaj Patil, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/15/25 12:24 PM, Jyothi Kumar Seerapu wrote:
>
> On 9/25/2025 3:48 PM, Konrad Dybcio wrote:
>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>> From: Jyothi Kumar Seerapu<jyothi.seerapu@oss.qualcomm.com>
>>>
>>> Add device tree support for QUPv3 serial engine protocols on Glymur.
>>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
>>> support of GPI DMA engines.
>>>
>>> Signed-off-by: Jyothi Kumar Seerapu<jyothi.seerapu@oss.qualcomm.com>
>>> Signed-off-by: Pankaj Patil<pankaj.patil@oss.qualcomm.com>
>>> ---
>> [...]
>>
>>> + gpi_dma2: dma-controller@800000 {
>>> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
>>> + reg = <0 0x00800000 0 0x60000>;
>>> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
>>> + dma-channels = <16>;
>>> + dma-channel-mask = <0x3f>;
>>> + #dma-cells = <3>;
>>> + iommus = <&apps_smmu 0xd76 0x0>;
>>> + status = "ok";
>> this is implied by default, drop
>
> Hi Konard,
>
> Do you mean we should remove the |status| property for all QUPs and GPI_DMAs from the common device tree (SOC) and enable them only in the board-specific device tree files?
Generally you don't need to specify status = "okay" at all (unless someone
set the status to "disabled"/"reserved" before, such as the initial
definition in the included DTSI)
But I believe you should be able to keep these enabled everywhere, as
the secure configuration which (dis)allows this is SoC-bound 99.9% of
the time
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-09-25 6:32 ` [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines Pankaj Patil
2025-09-25 10:18 ` Konrad Dybcio
@ 2025-10-11 11:06 ` Abel Vesa
2025-10-11 11:11 ` Abel Vesa
2025-10-11 11:16 ` Abel Vesa
2 siblings, 1 reply; 125+ messages in thread
From: Abel Vesa @ 2025-10-11 11:06 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Jyothi Kumar Seerapu
On 25-09-25 12:02:12, Pankaj Patil wrote:
> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>
> Add device tree support for QUPv3 serial engine protocols on Glymur.
> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> support of GPI DMA engines.
>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
> 2 files changed, 2936 insertions(+), 148 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -707,6 +707,32 @@ gcc: clock-controller@100000 {
> #power-domain-cells = <1>;
> };
>
> + gpi_dma2: dma-controller@800000 {
> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
> + reg = <0 0x00800000 0 0x60000>;
> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <16>;
> + dma-channel-mask = <0x3f>;
> + #dma-cells = <3>;
> + iommus = <&apps_smmu 0xd76 0x0>;
> + status = "ok";
s/ok/okay/
Everywhere actually.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-11 11:06 ` Abel Vesa
@ 2025-10-11 11:11 ` Abel Vesa
2025-10-12 2:46 ` Krzysztof Kozlowski
2025-10-15 10:33 ` Jyothi Kumar Seerapu
0 siblings, 2 replies; 125+ messages in thread
From: Abel Vesa @ 2025-10-11 11:11 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Jyothi Kumar Seerapu
On 25-10-11 14:06:44, Abel Vesa wrote:
> On 25-09-25 12:02:12, Pankaj Patil wrote:
> > From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> >
> > Add device tree support for QUPv3 serial engine protocols on Glymur.
> > Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> > support of GPI DMA engines.
> >
> > Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
> > 2 files changed, 2936 insertions(+), 148 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -707,6 +707,32 @@ gcc: clock-controller@100000 {
> > #power-domain-cells = <1>;
> > };
> >
> > + gpi_dma2: dma-controller@800000 {
> > + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
> > + reg = <0 0x00800000 0 0x60000>;
> > + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-channels = <16>;
> > + dma-channel-mask = <0x3f>;
> > + #dma-cells = <3>;
> > + iommus = <&apps_smmu 0xd76 0x0>;
> > + status = "ok";
>
> s/ok/okay/
>
> Everywhere actually.
>
Actually no. Maybe drop entirely like Konrad already suggested.
But then everywhere else you do "ok" please replace with "okay",
otherwise dtbs_check complains.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-11 11:11 ` Abel Vesa
@ 2025-10-12 2:46 ` Krzysztof Kozlowski
2025-10-15 10:33 ` Jyothi Kumar Seerapu
1 sibling, 0 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-12 2:46 UTC (permalink / raw)
To: Abel Vesa, Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Jyothi Kumar Seerapu
On 11/10/2025 13:11, Abel Vesa wrote:
> On 25-10-11 14:06:44, Abel Vesa wrote:
>> On 25-09-25 12:02:12, Pankaj Patil wrote:
>>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>> + dma-channels = <16>;
>>> + dma-channel-mask = <0x3f>;
>>> + #dma-cells = <3>;
>>> + iommus = <&apps_smmu 0xd76 0x0>;
>>> + status = "ok";
>>
>> s/ok/okay/
>>
>> Everywhere actually.
>>
>
> Actually no. Maybe drop entirely like Konrad already suggested.
>
> But then everywhere else you do "ok" please replace with "okay",
> otherwise dtbs_check complains.
I actually wonder how this passed any dtbs tests... or it wasn't tested
at all?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-11 11:11 ` Abel Vesa
2025-10-12 2:46 ` Krzysztof Kozlowski
@ 2025-10-15 10:33 ` Jyothi Kumar Seerapu
1 sibling, 0 replies; 125+ messages in thread
From: Jyothi Kumar Seerapu @ 2025-10-15 10:33 UTC (permalink / raw)
To: Abel Vesa, Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 10/11/2025 4:41 PM, Abel Vesa wrote:
> On 25-10-11 14:06:44, Abel Vesa wrote:
>> On 25-09-25 12:02:12, Pankaj Patil wrote:
>>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>>
>>> Add device tree support for QUPv3 serial engine protocols on Glymur.
>>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
>>> support of GPI DMA engines.
>>>
>>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
>>> arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
>>> 2 files changed, 2936 insertions(+), 148 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> @@ -707,6 +707,32 @@ gcc: clock-controller@100000 {
>>> #power-domain-cells = <1>;
>>> };
>>>
>>> + gpi_dma2: dma-controller@800000 {
>>> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
>>> + reg = <0 0x00800000 0 0x60000>;
>>> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
>>> + dma-channels = <16>;
>>> + dma-channel-mask = <0x3f>;
>>> + #dma-cells = <3>;
>>> + iommus = <&apps_smmu 0xd76 0x0>;
>>> + status = "ok";
>>
>> s/ok/okay/
>>
>> Everywhere actually.
>>
>
> Actually no. Maybe drop entirely like Konrad already suggested.
>
> But then everywhere else you do "ok" please replace with "okay",
> otherwise dtbs_check complains.
Sure, will review it.>
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-09-25 6:32 ` [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines Pankaj Patil
2025-09-25 10:18 ` Konrad Dybcio
2025-10-11 11:06 ` Abel Vesa
@ 2025-10-11 11:16 ` Abel Vesa
2025-10-15 10:53 ` Jyothi Kumar Seerapu
2 siblings, 1 reply; 125+ messages in thread
From: Abel Vesa @ 2025-10-11 11:16 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Jyothi Kumar Seerapu
On 25-09-25 12:02:12, Pankaj Patil wrote:
> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>
> Add device tree support for QUPv3 serial engine protocols on Glymur.
> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> support of GPI DMA engines.
>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
> 2 files changed, 2936 insertions(+), 148 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
[...]
> + qup_i2c22_data_clk: qup-i2c22-data-clk-state {
> + sda_pins {
> + /* SDA */
> + pins = "gpio88";
> + function = "qup2_se6";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + scl-pins {
> + /* SCL */
> + pins = "gpio89";
> + function = "qup2_se6";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> + };
Re-write all of these like the following:
qup_i2c22_data_clk: qup-i2c22-data-clk-state {
/* SDA, SCL */
pins = "gpio88", "gpio89";
function = "qup2_se6";
drive-strength = <2>;
bias-pull-up = <2200>;
};
Just like we did on X1E80100.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
2025-10-11 11:16 ` Abel Vesa
@ 2025-10-15 10:53 ` Jyothi Kumar Seerapu
0 siblings, 0 replies; 125+ messages in thread
From: Jyothi Kumar Seerapu @ 2025-10-15 10:53 UTC (permalink / raw)
To: Abel Vesa, Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 10/11/2025 4:46 PM, Abel Vesa wrote:
> On 25-09-25 12:02:12, Pankaj Patil wrote:
>> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>
>> Add device tree support for QUPv3 serial engine protocols on Glymur.
>> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
>> support of GPI DMA engines.
>>
>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
>> 2 files changed, 2936 insertions(+), 148 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>
> [...]
>
>> + qup_i2c22_data_clk: qup-i2c22-data-clk-state {
>> + sda_pins {
>> + /* SDA */
>> + pins = "gpio88";
>> + function = "qup2_se6";
>> + drive-strength = <2>;
>> + bias-pull-up = <2200>;
>> + };
>> +
>> + scl-pins {
>> + /* SCL */
>> + pins = "gpio89";
>> + function = "qup2_se6";
>> + drive-strength = <2>;
>> + bias-pull-up = <2200>;
>> + };
>> + };
>
> Re-write all of these like the following:
>
> qup_i2c22_data_clk: qup-i2c22-data-clk-state {
> /* SDA, SCL */
> pins = "gpio88", "gpio89";
> function = "qup2_se6";
> drive-strength = <2>;
> bias-pull-up = <2200>;
> };
>
> Just like we did on X1E80100.
Sure, that makes sense, as the same properties apply to both the SCL and
SDA pins.
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (3 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 10:25 ` Konrad Dybcio
2025-10-06 14:26 ` Krzysztof Kozlowski
2025-09-25 6:32 ` [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox Pankaj Patil
` (19 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Maulik Shah
From: Maulik Shah <maulik.shah@oss.qualcomm.com>
Add CPU power domains
Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 235 +++++++++++++++++++++++++++++++++++
1 file changed, 235 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 8674465b22707207523caa8ad635d95a3396497a..66a548400c720474cde8a8b82ee686be507a795f 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -46,6 +46,9 @@ cpu0: cpu0@0 {
compatible = "qcom,oryon";
reg = <0x0 0x0>;
enable-method = "psci";
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
l2_0: l2-cache {
@@ -60,6 +63,9 @@ cpu1: cpu1@100 {
compatible = "qcom,oryon";
reg = <0x0 0x100>;
enable-method = "psci";
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -68,6 +74,9 @@ cpu2: cpu2@200 {
compatible = "qcom,oryon";
reg = <0x0 0x200>;
enable-method = "psci";
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -76,6 +85,9 @@ cpu3: cpu3@300 {
compatible = "qcom,oryon";
reg = <0x0 0x300>;
enable-method = "psci";
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -84,6 +96,9 @@ cpu4: cpu4@400 {
compatible = "qcom,oryon";
reg = <0x0 0x400>;
enable-method = "psci";
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -92,6 +107,9 @@ cpu5: cpu5@500 {
compatible = "qcom,oryon";
reg = <0x0 0x500>;
enable-method = "psci";
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -100,6 +118,9 @@ cpu6: cpu6@10000 {
compatible = "qcom,oryon";
reg = <0x0 0x10000>;
enable-method = "psci";
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
l2_1: l2-cache {
@@ -114,6 +135,9 @@ cpu7: cpu7@10100 {
compatible = "qcom,oryon";
reg = <0x0 0x10100>;
enable-method = "psci";
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -122,6 +146,9 @@ cpu8: cpu8@10200 {
compatible = "qcom,oryon";
reg = <0x0 0x10200>;
enable-method = "psci";
+ power-domains = <&CPU_PD8>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -130,6 +157,9 @@ cpu9: cpu9@10300 {
compatible = "qcom,oryon";
reg = <0x0 0x10300>;
enable-method = "psci";
+ power-domains = <&CPU_PD9>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -138,6 +168,9 @@ cpu10: cpu10@10400 {
compatible = "qcom,oryon";
reg = <0x0 0x10400>;
enable-method = "psci";
+ power-domains = <&CPU_PD10>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -146,6 +179,9 @@ cpu11: cpu11@10500 {
compatible = "qcom,oryon";
reg = <0x0 0x10500>;
enable-method = "psci";
+ power-domains = <&CPU_PD11>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -154,6 +190,9 @@ cpu12: cpu12@20000 {
compatible = "qcom,oryon";
reg = <0x0 0x20000>;
enable-method = "psci";
+ power-domains = <&CPU_PD12>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
l2_2: l2-cache {
@@ -168,6 +207,9 @@ cpu13: cpu13@20100 {
compatible = "qcom,oryon";
reg = <0x0 0x20100>;
enable-method = "psci";
+ power-domains = <&CPU_PD13>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -176,6 +218,9 @@ cpu14: cpu14@20200 {
compatible = "qcom,oryon";
reg = <0x0 0x20200>;
enable-method = "psci";
+ power-domains = <&CPU_PD14>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -184,6 +229,9 @@ cpu15: cpu15@20300 {
compatible = "qcom,oryon";
reg = <0x0 0x20300>;
enable-method = "psci";
+ power-domains = <&CPU_PD15>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -192,6 +240,9 @@ cpu16: cpu16@20400 {
compatible = "qcom,oryon";
reg = <0x0 0x20400>;
enable-method = "psci";
+ power-domains = <&CPU_PD16>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -200,8 +251,78 @@ cpu17: cpu17@20500 {
compatible = "qcom,oryon";
reg = <0x0 0x20500>;
enable-method = "psci";
+ power-domains = <&CPU_PD17>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CLUSTER0_C4: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <180>;
+ exit-latency-us = <320>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER1_C4: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <180>;
+ exit-latency-us = <320>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER2_C4: cpu-sleep-2 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <180>;
+ exit-latency-us = <320>;
+ min-residency-us = <1000>;
+ };
+
+ cluster0_cl5: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <9000>;
+ };
+
+ cluster1_cl5: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <9000>;
+ };
+
+ cluster2_cl5: cluster-sleep-2 {
+ compatible = "domain-idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <9000>;
+ };
+
+ APSS_OFF: cluster-ss3 {
+ compatible = "domain-idle-state";
+ idle-state-name = "apps-pc";
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <10150>;
+ arm,psci-suspend-param = <0x0200C354>;
+ };
+ };
};
cpu-map {
@@ -669,6 +790,119 @@ pmu {
psci {
compatible = "arm,psci-1.0";
method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER0_PD>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER0_PD>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER0_PD>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER0_PD>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER0_PD>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER0_PD>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER1_PD>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER1_PD>;
+ };
+
+ CPU_PD8: power-domain-cpu8 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER1_PD>;
+ };
+
+ CPU_PD9: power-domain-cpu9 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER1_PD>;
+ };
+
+ CPU_PD10: power-domain-cpu10 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER1_PD>;
+ };
+
+ CPU_PD11: power-domain-cpu11 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER1_PD>;
+ };
+
+ CPU_PD12: power-domain-cpu12 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER2_PD>;
+ };
+
+ CPU_PD13: power-domain-cpu13 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER2_PD>;
+ };
+
+ CPU_PD14: power-domain-cpu14 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER2_PD>;
+ };
+
+ CPU_PD15: power-domain-cpu15 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER2_PD>;
+ };
+
+ CPU_PD16: power-domain-cpu16 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER2_PD>;
+ };
+
+ CPU_PD17: power-domain-cpu17 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER2_PD>;
+ };
+
+ CLUSTER0_PD: power-domain-cpu-cluster0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER3_PD>;
+ domain-idle-states = <&cluster0_cl5>;
+ };
+
+ CLUSTER1_PD: power-domain-cpu-cluster1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER3_PD>;
+ domain-idle-states = <&cluster1_cl5>;
+ };
+
+ CLUSTER2_PD: power-domain-cpu-cluster2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER3_PD>;
+ domain-idle-states = <&cluster2_cl5>;
+ };
+
+ CLUSTER3_PD: power-domain-cpu-cluster3 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&APSS_OFF>;
+ };
};
soc: soc@0 {
@@ -3927,6 +4161,7 @@ apps_rsc: rsc@18900000 {
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
+ power-domains = <&CLUSTER3_PD>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states
2025-09-25 6:32 ` [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states Pankaj Patil
@ 2025-09-25 10:25 ` Konrad Dybcio
2025-10-13 9:29 ` Maulik Shah (mkshah)
2025-10-06 14:26 ` Krzysztof Kozlowski
1 sibling, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:25 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Maulik Shah
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Maulik Shah <maulik.shah@oss.qualcomm.com>
>
> Add CPU power domains
The commit message could say something about what kind of states
are being added, what their impact on the running system is, etc..
[...]
> + idle-states {
> + entry-method = "psci";
> +
> + CLUSTER0_C4: cpu-sleep-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "ret";
> + arm,psci-suspend-param = <0x00000004>;
> + entry-latency-us = <180>;
> + exit-latency-us = <320>;
> + min-residency-us = <1000>;
> + };
> +
> + CLUSTER1_C4: cpu-sleep-1 {
> + compatible = "arm,idle-state";
> + idle-state-name = "ret";
> + arm,psci-suspend-param = <0x00000004>;
> + entry-latency-us = <180>;
> + exit-latency-us = <320>;
> + min-residency-us = <1000>;
> + };
> +
> + CLUSTER2_C4: cpu-sleep-2 {
> + compatible = "arm,idle-state";
> + idle-state-name = "ret";
> + arm,psci-suspend-param = <0x00000004>;
> + entry-latency-us = <180>;
> + exit-latency-us = <320>;
> + min-residency-us = <1000>;
> + };
All three are identical (should they be?), just call it CPU_C4 and de-
duplicate it (unless the framework would read that as "all CPUs in the
system must sleep at the same time" which I don't know if it would)
> +
> + cluster0_cl5: cluster-sleep-0 {
> + compatible = "domain-idle-state";
> + idle-state-name = "ret";
> + arm,psci-suspend-param = <0x01000054>;
> + entry-latency-us = <2000>;
> + exit-latency-us = <2000>;
> + min-residency-us = <9000>;
> + };
> +
> + cluster1_cl5: cluster-sleep-1 {
> + compatible = "domain-idle-state";
> + idle-state-name = "ret";
> + arm,psci-suspend-param = <0x01000054>;
> + entry-latency-us = <2000>;
> + exit-latency-us = <2000>;
> + min-residency-us = <9000>;
> + };
> +
> + cluster2_cl5: cluster-sleep-2 {
> + compatible = "domain-idle-state";
> + idle-state-name = "ret";
> + arm,psci-suspend-param = <0x01000054>;
> + entry-latency-us = <2000>;
> + exit-latency-us = <2000>;
> + min-residency-us = <9000>;
> + };
ditto
> +
> + APSS_OFF: cluster-ss3 {
labels must be lowercase
> + compatible = "domain-idle-state";
> + idle-state-name = "apps-pc";
> + entry-latency-us = <2800>;
> + exit-latency-us = <4400>;
> + min-residency-us = <10150>;
> + arm,psci-suspend-param = <0x0200C354>;
lowercase hex, please
also, this node oddly puts arm,psci-suspend-param at a different place,
please align it with the prvious ones
[...]
> + CLUSTER3_PD: power-domain-cpu-cluster3 {
"SYSTEM_PD"?
> + #power-domain-cells = <0>;
> + domain-idle-states = <&APSS_OFF>;
Does it make sense to include some shallower idle states?
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states
2025-09-25 10:25 ` Konrad Dybcio
@ 2025-10-13 9:29 ` Maulik Shah (mkshah)
0 siblings, 0 replies; 125+ messages in thread
From: Maulik Shah (mkshah) @ 2025-10-13 9:29 UTC (permalink / raw)
To: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 3:55 PM, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>> From: Maulik Shah <maulik.shah@oss.qualcomm.com>
>>
>> Add CPU power domains
>
> The commit message could say something about what kind of states
> are being added, what their impact on the running system is, etc..
This will be squashed with cpus node.
>
> [...]
>
>> + idle-states {
>> + entry-method = "psci";
>> +
>> + CLUSTER0_C4: cpu-sleep-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "ret";
>> + arm,psci-suspend-param = <0x00000004>;
>> + entry-latency-us = <180>;
>> + exit-latency-us = <320>;
>> + min-residency-us = <1000>;
>> + };
>> +
>> + CLUSTER1_C4: cpu-sleep-1 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "ret";
>> + arm,psci-suspend-param = <0x00000004>;
>> + entry-latency-us = <180>;
>> + exit-latency-us = <320>;
>> + min-residency-us = <1000>;
>> + };
>> +
>> + CLUSTER2_C4: cpu-sleep-2 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "ret";
>> + arm,psci-suspend-param = <0x00000004>;
>> + entry-latency-us = <180>;
>> + exit-latency-us = <320>;
>> + min-residency-us = <1000>;
>> + };
>
> All three are identical (should they be?), just call it CPU_C4 and de-
> duplicate it (unless the framework would read that as "all CPUs in the
> system must sleep at the same time" which I don't know if it would)
Updated to call cpu_c4, cluster_cl5 and domain_ss3 (inline with SM8750).
>
>> +
>> + cluster0_cl5: cluster-sleep-0 {
>> + compatible = "domain-idle-state";
>> + idle-state-name = "ret";
>> + arm,psci-suspend-param = <0x01000054>;
>> + entry-latency-us = <2000>;
>> + exit-latency-us = <2000>;
>> + min-residency-us = <9000>;
>> + };
>> +
>> + cluster1_cl5: cluster-sleep-1 {
>> + compatible = "domain-idle-state";
>> + idle-state-name = "ret";
>> + arm,psci-suspend-param = <0x01000054>;
>> + entry-latency-us = <2000>;
>> + exit-latency-us = <2000>;
>> + min-residency-us = <9000>;
>> + };
>> +
>> + cluster2_cl5: cluster-sleep-2 {
>> + compatible = "domain-idle-state";
>> + idle-state-name = "ret";
>> + arm,psci-suspend-param = <0x01000054>;
>> + entry-latency-us = <2000>;
>> + exit-latency-us = <2000>;
>> + min-residency-us = <9000>;
>> + };
>
> ditto
Updated in next revision.
>
>> +
>> + APSS_OFF: cluster-ss3 {
>
> labels must be lowercase
Updated in next revision.
>
>> + compatible = "domain-idle-state";
>> + idle-state-name = "apps-pc";
>> + entry-latency-us = <2800>;
>> + exit-latency-us = <4400>;
>> + min-residency-us = <10150>;
>> + arm,psci-suspend-param = <0x0200C354>;
>
> lowercase hex, please
>
> also, this node oddly puts arm,psci-suspend-param at a different place,
> please align it with the prvious ones
Both updated in next revision.
>
> [...]
>
>> + CLUSTER3_PD: power-domain-cpu-cluster3 {
>
> "SYSTEM_PD"?
Updated in next revision.
>> + #power-domain-cells = <0>;
>> + domain-idle-states = <&APSS_OFF>;
>
> Does it make sense to include some shallower idle states?
Shallower idle states for cluster (CL4) and system (SS1) did not give benefits for power/performance.
Thanks,
Maulik
>
> Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states
2025-09-25 6:32 ` [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states Pankaj Patil
2025-09-25 10:25 ` Konrad Dybcio
@ 2025-10-06 14:26 ` Krzysztof Kozlowski
2025-10-08 11:37 ` Pankaj Patil
1 sibling, 1 reply; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 14:26 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Maulik Shah
On 25/09/2025 15:32, Pankaj Patil wrote:
> From: Maulik Shah <maulik.shah@oss.qualcomm.com>
>
> Add CPU power domains
CPUs are part of base SoC. Splitting it makes no sense.
Stop fake-splitting this patchset just to bump your LWN stats (as
admitted in other email)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states
2025-10-06 14:26 ` Krzysztof Kozlowski
@ 2025-10-08 11:37 ` Pankaj Patil
0 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-10-08 11:37 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Maulik Shah
On 10/6/2025 7:56 PM, Krzysztof Kozlowski wrote:
> On 25/09/2025 15:32, Pankaj Patil wrote:
>> From: Maulik Shah <maulik.shah@oss.qualcomm.com>
>>
>> Add CPU power domains
> CPUs are part of base SoC. Splitting it makes no sense.
>
> Stop fake-splitting this patchset just to bump your LWN stats (as
> admitted in other email)
>
> Best regards,
> Krzysztof
Squashing commits 03-08 in next revision.
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (4 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 05/24] arm64: dts: qcom: glymur: Add cpu idle states Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 8:23 ` Krzysztof Kozlowski
2025-09-25 10:29 ` Konrad Dybcio
2025-09-25 6:32 ` [PATCH 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling Pankaj Patil
` (18 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Sibi Sankar
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Enable pdp0 mailbox node on Glymur SoCs.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -4065,6 +4065,14 @@ watchdog@17600000 {
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
+ pdp0_mbox: mailbox@17610000 {
+ compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ qcom,rx-chans = <0x7>;
+ };
+
timer@17810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17810000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
2025-09-25 6:32 ` [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox Pankaj Patil
@ 2025-09-25 8:23 ` Krzysztof Kozlowski
2025-09-25 17:06 ` Bjorn Andersson
2025-09-25 10:29 ` Konrad Dybcio
1 sibling, 1 reply; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:23 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Sibi Sankar
On Thu, 25 Sept 2025 at 15:33, Pankaj Patil
<pankaj.patil@oss.qualcomm.com> wrote:
>
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> Enable pdp0 mailbox node on Glymur SoCs.
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -4065,6 +4065,14 @@ watchdog@17600000 {
> interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> };
>
> + pdp0_mbox: mailbox@17610000 {
> + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <1>;
> + qcom,rx-chans = <0x7>;
> + };
Again one node per patch. this is really pointless, please read
submitting patches before posting.
New Soc is one logical change. One.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
2025-09-25 8:23 ` Krzysztof Kozlowski
@ 2025-09-25 17:06 ` Bjorn Andersson
2025-09-25 18:49 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Bjorn Andersson @ 2025-09-25 17:06 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Pankaj Patil, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Sibi Sankar
On Thu, Sep 25, 2025 at 05:23:07PM +0900, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 15:33, Pankaj Patil
> <pankaj.patil@oss.qualcomm.com> wrote:
> >
> > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> >
> > Enable pdp0 mailbox node on Glymur SoCs.
> >
> > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -4065,6 +4065,14 @@ watchdog@17600000 {
> > interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> > };
> >
> > + pdp0_mbox: mailbox@17610000 {
> > + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> > + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > + #mbox-cells = <1>;
> > + qcom,rx-chans = <0x7>;
> > + };
>
> Again one node per patch. this is really pointless, please read
> submitting patches before posting.
>
In this series I certainly agree with you.
This is most definitely part of the next patch, which is core support
that should have been part of the introduction of the CPU nodes in the
initial patch.
Regards,
Bjorn
> New Soc is one logical change. One.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
2025-09-25 17:06 ` Bjorn Andersson
@ 2025-09-25 18:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 18:49 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Krzysztof Kozlowski, Pankaj Patil, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Sibi Sankar
On Thu, Sep 25, 2025 at 12:06:40PM -0500, Bjorn Andersson wrote:
> On Thu, Sep 25, 2025 at 05:23:07PM +0900, Krzysztof Kozlowski wrote:
> > On Thu, 25 Sept 2025 at 15:33, Pankaj Patil
> > <pankaj.patil@oss.qualcomm.com> wrote:
> > >
> > > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > >
> > > Enable pdp0 mailbox node on Glymur SoCs.
> > >
> > > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > @@ -4065,6 +4065,14 @@ watchdog@17600000 {
> > > interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> > > };
> > >
> > > + pdp0_mbox: mailbox@17610000 {
> > > + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> > > + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> > > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > > + #mbox-cells = <1>;
> > > + qcom,rx-chans = <0x7>;
> > > + };
> >
> > Again one node per patch. this is really pointless, please read
> > submitting patches before posting.
> >
>
> In this series I certainly agree with you.
>
> This is most definitely part of the next patch, which is core support
> that should have been part of the introduction of the CPU nodes in the
> initial patch.
I'd say, all CPU-related patches should be squashed. There is no reqason
to have CPU, CPU idles and CPUfreq in 3 different patches.
>
> Regards,
> Bjorn
>
> > New Soc is one logical change. One.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
2025-09-25 6:32 ` [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox Pankaj Patil
2025-09-25 8:23 ` Krzysztof Kozlowski
@ 2025-09-25 10:29 ` Konrad Dybcio
2025-10-09 10:43 ` Sibi Sankar
1 sibling, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:29 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Sibi Sankar
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> Enable pdp0 mailbox node on Glymur SoCs.
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -4065,6 +4065,14 @@ watchdog@17600000 {
> interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> };
>
> + pdp0_mbox: mailbox@17610000 {
> + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
1 a line, please
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
I see this has 3 channels, with 3 separate IRQs (but one pair of address
spaces) - should we extend this description?
> + #mbox-cells = <1>;
> + qcom,rx-chans = <0x7>;
This further seems to confirm what I found (BIT(0) | BIT(1) | BIT(2) == 0x7)
however this property doesn't exist upstream..
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
2025-09-25 10:29 ` Konrad Dybcio
@ 2025-10-09 10:43 ` Sibi Sankar
2025-10-20 11:51 ` Konrad Dybcio
0 siblings, 1 reply; 125+ messages in thread
From: Sibi Sankar @ 2025-10-09 10:43 UTC (permalink / raw)
To: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 3:59 PM, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>>
>> Enable pdp0 mailbox node on Glymur SoCs.
>>
>> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> @@ -4065,6 +4065,14 @@ watchdog@17600000 {
>> interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
>> };
>>
>> + pdp0_mbox: mailbox@17610000 {
>> + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
>> + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> 1 a line, please
Hey Konrad,
Thanks for taking time to review the series :)
Will fix it in the next re-spin.
>> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> I see this has 3 channels, with 3 separate IRQs (but one pair of address
> spaces) - should we extend this description?
It has a single IRQ and each bit corresponds to a channel. The mbox
theoretically
hold as many channel as the number of bits. The third channel here is
used for
logging and is disabled on devices out in the wild.
>
>> + #mbox-cells = <1>;
>> + qcom,rx-chans = <0x7>;
> This further seems to confirm what I found (BIT(0) | BIT(1) | BIT(2) == 0x7)
> however this property doesn't exist upstream..
Ack, this seems to have picked up erroneously and isn't needed upstream and
can be dropped safely. This was needed downstream because they share the
same rx register space across multiple instances. This wouldn't be possible
upstream and we would be exposing all mailboxes that uses the rx space in
the same instance and extend mbox cells to 2 to support this in case when
it is needed in the future.
> Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox
2025-10-09 10:43 ` Sibi Sankar
@ 2025-10-20 11:51 ` Konrad Dybcio
0 siblings, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-20 11:51 UTC (permalink / raw)
To: Sibi Sankar, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/9/25 12:43 PM, Sibi Sankar wrote:
>
> On 9/25/2025 3:59 PM, Konrad Dybcio wrote:
>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>>>
>>> Enable pdp0 mailbox node on Glymur SoCs.
>>>
>>> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> @@ -4065,6 +4065,14 @@ watchdog@17600000 {
>>> interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
>>> };
>>> + pdp0_mbox: mailbox@17610000 {
>>> + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
>>> + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
>> 1 a line, please
>
> Hey Konrad,
>
> Thanks for taking time to review the series :)
>
> Will fix it in the next re-spin.
>
>>> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> I see this has 3 channels, with 3 separate IRQs (but one pair of address
>> spaces) - should we extend this description?
>
> It has a single IRQ and each bit corresponds to a channel. The mbox theoretically
>
> hold as many channel as the number of bits. The third channel here is used for
>
> logging and is disabled on devices out in the wild.
Your mailing client injects two '\n's every time you press enter
Try setting mailnews.wraplength = 0 in your presumably thunderbird config
Is the logging channel useful for us, on internal devices? We can still
describe it if so
>
>>
>>> + #mbox-cells = <1>;
>>> + qcom,rx-chans = <0x7>;
>> This further seems to confirm what I found (BIT(0) | BIT(1) | BIT(2) == 0x7)
>> however this property doesn't exist upstream..
>
> Ack, this seems to have picked up erroneously and isn't needed upstream and
>
> can be dropped safely. This was needed downstream because they share the
>
> same rx register space across multiple instances. This wouldn't be possible
>
> upstream and we would be exposing all mailboxes that uses the rx space in
>
> the same instance and extend mbox cells to 2 to support this in case when
>
> it is needed in the future.
This won't fly, as you're essentially saying you're introducing knowingly
incomplete bindings, which are supposed to stay immutable..
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (5 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 8:06 ` Krzysztof Kozlowski
2025-09-25 17:26 ` Bjorn Andersson
2025-09-25 6:32 ` [PATCH 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes Pankaj Patil
` (17 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil, Taniya Das,
Sibi Sankar, Taniya Das
From: Taniya Das <taniya.das@oss.qualcomm.com>
Add sram and scmi nodes required to have a functional cpu dvfs
on Glymur SoCs.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 87 +++++++++++++++++++++---------------
1 file changed, 51 insertions(+), 36 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index ae013c64e096b7c90c0aa4cfc50f078a85518acb..d924b4778fd37af8fe7b0bceca466dee73269481 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -46,8 +46,8 @@ cpu0: cpu0@0 {
compatible = "qcom,oryon";
reg = <0x0 0x0>;
enable-method = "psci";
- power-domains = <&CPU_PD0>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD0>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
@@ -63,8 +63,8 @@ cpu1: cpu1@100 {
compatible = "qcom,oryon";
reg = <0x0 0x100>;
enable-method = "psci";
- power-domains = <&CPU_PD1>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD1>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -74,8 +74,8 @@ cpu2: cpu2@200 {
compatible = "qcom,oryon";
reg = <0x0 0x200>;
enable-method = "psci";
- power-domains = <&CPU_PD2>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD2>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -85,8 +85,8 @@ cpu3: cpu3@300 {
compatible = "qcom,oryon";
reg = <0x0 0x300>;
enable-method = "psci";
- power-domains = <&CPU_PD3>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD3>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -96,8 +96,8 @@ cpu4: cpu4@400 {
compatible = "qcom,oryon";
reg = <0x0 0x400>;
enable-method = "psci";
- power-domains = <&CPU_PD4>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD4>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -107,8 +107,8 @@ cpu5: cpu5@500 {
compatible = "qcom,oryon";
reg = <0x0 0x500>;
enable-method = "psci";
- power-domains = <&CPU_PD5>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD5>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER0_C4>;
next-level-cache = <&l2_0>;
};
@@ -118,8 +118,8 @@ cpu6: cpu6@10000 {
compatible = "qcom,oryon";
reg = <0x0 0x10000>;
enable-method = "psci";
- power-domains = <&CPU_PD6>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD6>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
@@ -135,8 +135,8 @@ cpu7: cpu7@10100 {
compatible = "qcom,oryon";
reg = <0x0 0x10100>;
enable-method = "psci";
- power-domains = <&CPU_PD7>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD7>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -146,8 +146,8 @@ cpu8: cpu8@10200 {
compatible = "qcom,oryon";
reg = <0x0 0x10200>;
enable-method = "psci";
- power-domains = <&CPU_PD8>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD8>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -157,8 +157,8 @@ cpu9: cpu9@10300 {
compatible = "qcom,oryon";
reg = <0x0 0x10300>;
enable-method = "psci";
- power-domains = <&CPU_PD9>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD9>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -168,8 +168,8 @@ cpu10: cpu10@10400 {
compatible = "qcom,oryon";
reg = <0x0 0x10400>;
enable-method = "psci";
- power-domains = <&CPU_PD10>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD10>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -179,8 +179,8 @@ cpu11: cpu11@10500 {
compatible = "qcom,oryon";
reg = <0x0 0x10500>;
enable-method = "psci";
- power-domains = <&CPU_PD11>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD11>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER1_C4>;
next-level-cache = <&l2_1>;
};
@@ -190,8 +190,8 @@ cpu12: cpu12@20000 {
compatible = "qcom,oryon";
reg = <0x0 0x20000>;
enable-method = "psci";
- power-domains = <&CPU_PD12>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD12>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
@@ -207,8 +207,8 @@ cpu13: cpu13@20100 {
compatible = "qcom,oryon";
reg = <0x0 0x20100>;
enable-method = "psci";
- power-domains = <&CPU_PD13>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD13>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -218,8 +218,8 @@ cpu14: cpu14@20200 {
compatible = "qcom,oryon";
reg = <0x0 0x20200>;
enable-method = "psci";
- power-domains = <&CPU_PD14>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD14>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -229,8 +229,8 @@ cpu15: cpu15@20300 {
compatible = "qcom,oryon";
reg = <0x0 0x20300>;
enable-method = "psci";
- power-domains = <&CPU_PD15>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD15>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -240,8 +240,8 @@ cpu16: cpu16@20400 {
compatible = "qcom,oryon";
reg = <0x0 0x20400>;
enable-method = "psci";
- power-domains = <&CPU_PD16>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD16>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -251,8 +251,8 @@ cpu17: cpu17@20500 {
compatible = "qcom,oryon";
reg = <0x0 0x20500>;
enable-method = "psci";
- power-domains = <&CPU_PD17>;
- power-domain-names = "psci";
+ power-domains = <&CPU_PD17>, <&scmi_perf 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&CLUSTER2_C4>;
next-level-cache = <&l2_2>;
};
@@ -397,6 +397,21 @@ scm: scm {
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+ };
};
reserved-memory {
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling
2025-09-25 6:32 ` [PATCH 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling Pankaj Patil
@ 2025-09-25 8:06 ` Krzysztof Kozlowski
2025-09-25 17:26 ` Bjorn Andersson
1 sibling, 0 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:06 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, Taniya Das,
Sibi Sankar, Taniya Das
On Thu, 25 Sept 2025 at 15:33, Pankaj Patil
<pankaj.patil@oss.qualcomm.com> wrote:
>
> From: Taniya Das <taniya.das@oss.qualcomm.com>
>
> Add sram and scmi nodes required to have a functional cpu dvfs
> on Glymur SoCs.
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 87 +++++++++++++++++++++---------------
> 1 file changed, 51 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index ae013c64e096b7c90c0aa4cfc50f078a85518acb..d924b4778fd37af8fe7b0bceca466dee73269481 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -46,8 +46,8 @@ cpu0: cpu0@0 {
> compatible = "qcom,oryon";
> reg = <0x0 0x0>;
> enable-method = "psci";
> - power-domains = <&CPU_PD0>;
> - power-domain-names = "psci";
NAK
You just added these lines!
This is some ridiculous way of splitting patches. Sending wrong commit
and then fixing it immediately.
Same as Kaanapali, same broken process which year ago and two years
ago I was already commenting on. You are repeating the same mistakes,
sending wrong code and patches which are unnecessarily difficult to
review. And we discussed exactly this already!
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling
2025-09-25 6:32 ` [PATCH 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling Pankaj Patil
2025-09-25 8:06 ` Krzysztof Kozlowski
@ 2025-09-25 17:26 ` Bjorn Andersson
1 sibling, 0 replies; 125+ messages in thread
From: Bjorn Andersson @ 2025-09-25 17:26 UTC (permalink / raw)
To: Pankaj Patil
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, Taniya Das, Sibi Sankar,
Taniya Das
On Thu, Sep 25, 2025 at 12:02:15PM +0530, Pankaj Patil wrote:
> From: Taniya Das <taniya.das@oss.qualcomm.com>
>
> Add sram and scmi nodes required to have a functional cpu dvfs
> on Glymur SoCs.
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@qualcomm.com>
Checkpatch doesn't approve
Regards,
Bjorn
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 87 +++++++++++++++++++++---------------
> 1 file changed, 51 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index ae013c64e096b7c90c0aa4cfc50f078a85518acb..d924b4778fd37af8fe7b0bceca466dee73269481 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -46,8 +46,8 @@ cpu0: cpu0@0 {
> compatible = "qcom,oryon";
> reg = <0x0 0x0>;
> enable-method = "psci";
> - power-domains = <&CPU_PD0>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD0>, <&scmi_perf 0>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER0_C4>;
> next-level-cache = <&l2_0>;
>
> @@ -63,8 +63,8 @@ cpu1: cpu1@100 {
> compatible = "qcom,oryon";
> reg = <0x0 0x100>;
> enable-method = "psci";
> - power-domains = <&CPU_PD1>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD1>, <&scmi_perf 0>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER0_C4>;
> next-level-cache = <&l2_0>;
> };
> @@ -74,8 +74,8 @@ cpu2: cpu2@200 {
> compatible = "qcom,oryon";
> reg = <0x0 0x200>;
> enable-method = "psci";
> - power-domains = <&CPU_PD2>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD2>, <&scmi_perf 0>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER0_C4>;
> next-level-cache = <&l2_0>;
> };
> @@ -85,8 +85,8 @@ cpu3: cpu3@300 {
> compatible = "qcom,oryon";
> reg = <0x0 0x300>;
> enable-method = "psci";
> - power-domains = <&CPU_PD3>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD3>, <&scmi_perf 0>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER0_C4>;
> next-level-cache = <&l2_0>;
> };
> @@ -96,8 +96,8 @@ cpu4: cpu4@400 {
> compatible = "qcom,oryon";
> reg = <0x0 0x400>;
> enable-method = "psci";
> - power-domains = <&CPU_PD4>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD4>, <&scmi_perf 0>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER0_C4>;
> next-level-cache = <&l2_0>;
> };
> @@ -107,8 +107,8 @@ cpu5: cpu5@500 {
> compatible = "qcom,oryon";
> reg = <0x0 0x500>;
> enable-method = "psci";
> - power-domains = <&CPU_PD5>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD5>, <&scmi_perf 0>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER0_C4>;
> next-level-cache = <&l2_0>;
> };
> @@ -118,8 +118,8 @@ cpu6: cpu6@10000 {
> compatible = "qcom,oryon";
> reg = <0x0 0x10000>;
> enable-method = "psci";
> - power-domains = <&CPU_PD6>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD6>, <&scmi_perf 1>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER1_C4>;
> next-level-cache = <&l2_1>;
>
> @@ -135,8 +135,8 @@ cpu7: cpu7@10100 {
> compatible = "qcom,oryon";
> reg = <0x0 0x10100>;
> enable-method = "psci";
> - power-domains = <&CPU_PD7>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD7>, <&scmi_perf 1>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER1_C4>;
> next-level-cache = <&l2_1>;
> };
> @@ -146,8 +146,8 @@ cpu8: cpu8@10200 {
> compatible = "qcom,oryon";
> reg = <0x0 0x10200>;
> enable-method = "psci";
> - power-domains = <&CPU_PD8>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD8>, <&scmi_perf 1>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER1_C4>;
> next-level-cache = <&l2_1>;
> };
> @@ -157,8 +157,8 @@ cpu9: cpu9@10300 {
> compatible = "qcom,oryon";
> reg = <0x0 0x10300>;
> enable-method = "psci";
> - power-domains = <&CPU_PD9>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD9>, <&scmi_perf 1>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER1_C4>;
> next-level-cache = <&l2_1>;
> };
> @@ -168,8 +168,8 @@ cpu10: cpu10@10400 {
> compatible = "qcom,oryon";
> reg = <0x0 0x10400>;
> enable-method = "psci";
> - power-domains = <&CPU_PD10>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD10>, <&scmi_perf 1>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER1_C4>;
> next-level-cache = <&l2_1>;
> };
> @@ -179,8 +179,8 @@ cpu11: cpu11@10500 {
> compatible = "qcom,oryon";
> reg = <0x0 0x10500>;
> enable-method = "psci";
> - power-domains = <&CPU_PD11>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD11>, <&scmi_perf 1>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER1_C4>;
> next-level-cache = <&l2_1>;
> };
> @@ -190,8 +190,8 @@ cpu12: cpu12@20000 {
> compatible = "qcom,oryon";
> reg = <0x0 0x20000>;
> enable-method = "psci";
> - power-domains = <&CPU_PD12>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD12>, <&scmi_perf 2>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER2_C4>;
> next-level-cache = <&l2_2>;
>
> @@ -207,8 +207,8 @@ cpu13: cpu13@20100 {
> compatible = "qcom,oryon";
> reg = <0x0 0x20100>;
> enable-method = "psci";
> - power-domains = <&CPU_PD13>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD13>, <&scmi_perf 2>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER2_C4>;
> next-level-cache = <&l2_2>;
> };
> @@ -218,8 +218,8 @@ cpu14: cpu14@20200 {
> compatible = "qcom,oryon";
> reg = <0x0 0x20200>;
> enable-method = "psci";
> - power-domains = <&CPU_PD14>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD14>, <&scmi_perf 2>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER2_C4>;
> next-level-cache = <&l2_2>;
> };
> @@ -229,8 +229,8 @@ cpu15: cpu15@20300 {
> compatible = "qcom,oryon";
> reg = <0x0 0x20300>;
> enable-method = "psci";
> - power-domains = <&CPU_PD15>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD15>, <&scmi_perf 2>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER2_C4>;
> next-level-cache = <&l2_2>;
> };
> @@ -240,8 +240,8 @@ cpu16: cpu16@20400 {
> compatible = "qcom,oryon";
> reg = <0x0 0x20400>;
> enable-method = "psci";
> - power-domains = <&CPU_PD16>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD16>, <&scmi_perf 2>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER2_C4>;
> next-level-cache = <&l2_2>;
> };
> @@ -251,8 +251,8 @@ cpu17: cpu17@20500 {
> compatible = "qcom,oryon";
> reg = <0x0 0x20500>;
> enable-method = "psci";
> - power-domains = <&CPU_PD17>;
> - power-domain-names = "psci";
> + power-domains = <&CPU_PD17>, <&scmi_perf 2>;
> + power-domain-names = "psci", "perf";
> cpu-idle-states = <&CLUSTER2_C4>;
> next-level-cache = <&l2_2>;
> };
> @@ -397,6 +397,21 @@ scm: scm {
> interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
> &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> };
> +
> + scmi {
> + compatible = "arm,scmi";
> + mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
> + mbox-names = "tx", "rx";
> + shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + scmi_perf: protocol@13 {
> + reg = <0x13>;
> + #power-domain-cells = <1>;
> + };
> + };
> };
>
> reserved-memory {
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (6 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 11:00 ` Konrad Dybcio
2025-09-25 6:32 ` [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails Pankaj Patil
` (16 subsequent siblings)
24 siblings, 1 reply; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Sibi Sankar
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Enable ipcc and aoss nodes on Glmyur SoCs.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index d924b4778fd37af8fe7b0bceca466dee73269481..2632ef381687c2392f8fad0294901e33887ac4d3 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -2536,6 +2537,17 @@ hsc_noc: interconnect@2000000 {
#interconnect-cells = <2>;
};
+ ipcc: mailbox@3e04000{
+ compatible = "qcom,glymur-ipcc", "qcom,ipcc";
+ reg = <0 0x03e04000 0 0x1000>;
+
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,glymur-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
@@ -2572,6 +2584,17 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x400>;
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc GLYMUR_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc GLYMUR_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
sram@c30f000 {
compatible = "qcom,rpmh-stats";
reg = <0x0 0x0c30f000 0x0 0x400>;
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes
2025-09-25 6:32 ` [PATCH 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes Pankaj Patil
@ 2025-09-25 11:00 ` Konrad Dybcio
0 siblings, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 11:00 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Sibi Sankar
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> Enable ipcc and aoss nodes on Glmyur SoCs.
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index d924b4778fd37af8fe7b0bceca466dee73269481..2632ef381687c2392f8fad0294901e33887ac4d3 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> @@ -2536,6 +2537,17 @@ hsc_noc: interconnect@2000000 {
> #interconnect-cells = <2>;
> };
>
> + ipcc: mailbox@3e04000{
Missing space before '{'
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (7 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 11:01 ` Konrad Dybcio
` (2 more replies)
2025-09-25 6:32 ` [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device Pankaj Patil
` (15 subsequent siblings)
24 siblings, 3 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add RPMH regulator rails for Glymur CRD.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 332 ++++++++++++++++++++++++++++++++
1 file changed, 332 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 4561c0b87b017cba0a1db8814123a070b37fd434..e89b81dcb4f47b78307fa3ab6831657cf6491c89 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "glymur.dtsi"
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
@@ -66,3 +67,334 @@ chosen {
&tlmm {
gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
};
+
+&apps_rsc {
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ regulators-0 {
+ compatible = "qcom,pmh0101-rpmh-regulators";
+ qcom,pmic-id = "B_E0";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l10-l15-supply = <&vreg_s9f_e0_1p9>;
+ vdd-l2-l7-l8-l9-l16-supply = <&vreg_bob1_e0>;
+ vdd-l11-l12-l18-supply = <&vreg_s7f_e0_1p32>;
+ vdd-l17-supply = <&vreg_bob2_e0>;
+
+ vreg_bob1_e0: bob1 {
+ regulator-name = "vreg_bob1_e0";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <4224000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_bob2_e0: bob2 {
+ regulator-name = "vreg_bob2_e0";
+ regulator-min-microvolt = <2540000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l1b_e0_1p8: ldo1 {
+ regulator-name = "vreg_l1b_e0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_e0_2p9: ldo2 {
+ regulator-name = "vreg_l2b_e0_2p9";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_e0_2p79: ldo7 {
+ regulator-name = "vreg_l7b_e0_2p79";
+ regulator-min-microvolt = <2790000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_e0_1p50: ldo8 {
+ regulator-name = "vreg_l8b_e0_1p50";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_e0_2p7: ldo9 {
+ regulator-name = "vreg_l9b_e0_2p7";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_e0_1p8: ldo10 {
+ regulator-name = "vreg_l10b_e0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_e0_1p2: ldo11 {
+ regulator-name = "vreg_l11b_e0_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_e0_1p14: ldo12 {
+ regulator-name = "vreg_l12b_e0_1p14";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_e0_1p8: ldo15 {
+ regulator-name = "vreg_l15b_e0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_e0_2p4: ldo17 {
+ regulator-name = "vreg_l17b_e0_2p4";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_e0_1p2: ldo18 {
+ regulator-name = "vreg_l18b_e0_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmcx0102-rpmh-regulators";
+ qcom,pmic-id = "C_E0";
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vreg_s1c_e0_0p3: smps1 {
+ regulator-name = "vreg_s1c_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_e0_0p3: smps8 {
+ regulator-name = "vreg_s8c_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmcx0102-rpmh-regulators";
+ qcom,pmic-id = "C_E1";
+
+ vdd-l2-supply = <&vreg_s7f_e0_1p32>;
+ vdd-l1-l3-l4-supply = <&vreg_s8f_e0_0p95>;
+
+ vreg_l1c_e1_0p82: ldo1 {
+ regulator-name = "vreg_l1c_e1_0p82";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_e1_1p14: ldo2 {
+ regulator-name = "vreg_l2c_e1_1p14";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_e1_0p89: ldo3 {
+ regulator-name = "vreg_l3c_e1_0p89";
+ regulator-min-microvolt = <890000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_e1_0p72: ldo4 {
+ regulator-name = "vreg_l4c_e1_0p72";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "F_E0";
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l2-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l3-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l4-supply = <&vreg_s8f_e0_0p95>;
+
+ vreg_s7f_e0_1p32: smps7 {
+ regulator-name = "vreg_s7f_e0_1p32";
+ regulator-min-microvolt = <1320000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8f_e0_0p95: smps8 {
+ regulator-name = "vreg_s8f_e0_0p95";
+ regulator-min-microvolt = <952000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9f_e0_1p9: smps9 {
+ regulator-name = "vreg_s9f_e0_1p9";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s10f_e0_0p3: smps10 {
+ regulator-name = "vreg_s10f_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_e0_0p82: ldo2 {
+ regulator-name = "vreg_l2f_e0_0p82";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_e0_0p72: ldo3 {
+ regulator-name = "vreg_l3f_e0_0p72";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4f_e0_0p3: ldo4 {
+ regulator-name = "vreg_l4f_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "F_E1";
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-l1-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l2-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l4-supply = <&vreg_s8f_e0_0p95>;
+
+ vreg_s1f_e1_0p3: smps1 {
+ regulator-name = "vreg_s1f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5f_e1_0p3: smps5 {
+ regulator-name = "vreg_s5f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6f_e1_0p3: smps6 {
+ regulator-name = "vreg_s6f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_e1_0p3: smps7 {
+ regulator-name = "vreg_s7f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_e1_0p82: ldo1 {
+ regulator-name = "vreg_l1f_e1_0p82";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_e1_0p83: ldo2 {
+ regulator-name = "vreg_l2f_e1_0p83";
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4f_e1_1p08: ldo4 {
+ regulator-name = "vreg_l4f_e1_1p08";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "H_E0";
+
+ vdd-l1-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l2-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l3-supply = <&vreg_s9f_e0_1p9>;
+ vdd-l4-supply = <&vreg_s7f_e0_1p32>;
+
+ vreg_l1h_e0_0p89: ldo1 {
+ regulator-name = "vreg_l1h_e0_0p89";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2h_e0_0p72: ldo2 {
+ regulator-name = "vreg_l2h_e0_0p72";
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3h_e0_0p32: ldo3 {
+ regulator-name = "vreg_l3h_e0_0p32";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4h_e0_1p2: ldo4 {
+ regulator-name = "vreg_l4h_e0_1p2";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-09-25 6:32 ` [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails Pankaj Patil
@ 2025-09-25 11:01 ` Konrad Dybcio
2025-10-15 15:40 ` Kamal Wadhwa
2025-09-25 17:09 ` Bjorn Andersson
2025-10-11 11:31 ` Abel Vesa
2 siblings, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 11:01 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add RPMH regulator rails for Glymur CRD.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
[...]
> + regulators-1 {
> + compatible = "qcom,pmcx0102-rpmh-regulators";
> + qcom,pmic-id = "C_E0";
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> +
> + vreg_s1c_e0_0p3: smps1 {
> + regulator-name = "vreg_s1c_e0_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s8c_e0_0p3: smps8 {
> + regulator-name = "vreg_s8c_e0_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>
Both of these regulators, having no consumers, will be parked to 0.3 V
(the lower bound)
There are other similar cases in this patch
Does the board still boot with all the expected functionality with only
patches 1-9 applied?
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-09-25 11:01 ` Konrad Dybcio
@ 2025-10-15 15:40 ` Kamal Wadhwa
2025-10-20 11:53 ` Konrad Dybcio
0 siblings, 1 reply; 125+ messages in thread
From: Kamal Wadhwa @ 2025-10-15 15:40 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On Thu, Sep 25, 2025 at 01:01:56PM +0200, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
> > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >
> > Add RPMH regulator rails for Glymur CRD.
> >
> > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + regulators-1 {
> > + compatible = "qcom,pmcx0102-rpmh-regulators";
> > + qcom,pmic-id = "C_E0";
> > + vdd-s1-supply = <&vph_pwr>;
> > + vdd-s8-supply = <&vph_pwr>;
> > +
> > + vreg_s1c_e0_0p3: smps1 {
> > + regulator-name = "vreg_s1c_e0_0p3";
> > + regulator-min-microvolt = <300000>;
> > + regulator-max-microvolt = <1200000>;
> > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> > + };
> > +
> > + vreg_s8c_e0_0p3: smps8 {
> > + regulator-name = "vreg_s8c_e0_0p3";
> > + regulator-min-microvolt = <300000>;
> > + regulator-max-microvolt = <1200000>
>
> Both of these regulators, having no consumers, will be parked to 0.3 V
> (the lower bound)
>
> There are other similar cases in this patch
Ok. I will remove the unused rails.
But just wanted to let you know currently i have exposed all the rails that
are allowed to be controlled from APPS, mostly these rails will be staying
OFF if no clients in SW are there to vote on them.
But do note that some of the clients may be getting added as more features
get added, as lot of these rails are not unused in the HW. The client driver
just isnt enabled as of now.
So wanted to check if I should remove ALL rails that are unused in SW?
or
Can i keep the ones for which clients will be getting added in near future.
(i would prefer the later option, if that is ok with you?)
>
> Does the board still boot with all the expected functionality with only
> patches 1-9 applied?
No. just tested, it seems not able to boot properly with just 1-9 patches.
is your concern about squashing of the patches?
(just trying to understand)
>
> Konrad
Regards,
Kamal
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-10-15 15:40 ` Kamal Wadhwa
@ 2025-10-20 11:53 ` Konrad Dybcio
0 siblings, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-20 11:53 UTC (permalink / raw)
To: Kamal Wadhwa
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 10/15/25 5:40 PM, Kamal Wadhwa wrote:
> On Thu, Sep 25, 2025 at 01:01:56PM +0200, Konrad Dybcio wrote:
>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>
>>> Add RPMH regulator rails for Glymur CRD.
>>>
>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + regulators-1 {
>>> + compatible = "qcom,pmcx0102-rpmh-regulators";
>>> + qcom,pmic-id = "C_E0";
>>> + vdd-s1-supply = <&vph_pwr>;
>>> + vdd-s8-supply = <&vph_pwr>;
>>> +
>>> + vreg_s1c_e0_0p3: smps1 {
>>> + regulator-name = "vreg_s1c_e0_0p3";
>>> + regulator-min-microvolt = <300000>;
>>> + regulator-max-microvolt = <1200000>;
>>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>>> + };
>>> +
>>> + vreg_s8c_e0_0p3: smps8 {
>>> + regulator-name = "vreg_s8c_e0_0p3";
>>> + regulator-min-microvolt = <300000>;
>>> + regulator-max-microvolt = <1200000>
>>
>> Both of these regulators, having no consumers, will be parked to 0.3 V
>> (the lower bound)
>>
>> There are other similar cases in this patch
>
> Ok. I will remove the unused rails.
> But just wanted to let you know currently i have exposed all the rails that
> are allowed to be controlled from APPS, mostly these rails will be staying
> OFF if no clients in SW are there to vote on them.
>
> But do note that some of the clients may be getting added as more features
> get added, as lot of these rails are not unused in the HW. The client driver
> just isnt enabled as of now.
>
> So wanted to check if I should remove ALL rails that are unused in SW?
> or
> Can i keep the ones for which clients will be getting added in near future.
>
> (i would prefer the later option, if that is ok with you?)
Please keep them but restrict them to the actually useful range, not just
what the hardware can do.
Most of them are presumably hardwired to specific peripherals and need
e.g. 1.8 V
>> Does the board still boot with all the expected functionality with only
>> patches 1-9 applied?
>
> No. just tested, it seems not able to boot properly with just 1-9 patches.
> is your concern about squashing of the patches?
> (just trying to understand)
Yes, all boards must boot and not regress at any point, including at the
introductory commit. Otherwise bisecting is impossible.
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-09-25 6:32 ` [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails Pankaj Patil
2025-09-25 11:01 ` Konrad Dybcio
@ 2025-09-25 17:09 ` Bjorn Andersson
2025-10-08 11:42 ` Pankaj Patil
2025-10-11 11:31 ` Abel Vesa
2 siblings, 1 reply; 125+ messages in thread
From: Bjorn Andersson @ 2025-09-25 17:09 UTC (permalink / raw)
To: Pankaj Patil
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On Thu, Sep 25, 2025 at 12:02:17PM +0530, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add RPMH regulator rails for Glymur CRD.
>
Please don't sprinkle board-specific changes throughout the series.
It's useful to introduce the dts early on, so that any dtsi changes gets
compiled, but you can then group the board-specific changes at the end
of the series; and squash them into one.
Regards,
Bjorn
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 332 ++++++++++++++++++++++++++++++++
> 1 file changed, 332 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index 4561c0b87b017cba0a1db8814123a070b37fd434..e89b81dcb4f47b78307fa3ab6831657cf6491c89 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "glymur.dtsi"
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>
> / {
> model = "Qualcomm Technologies, Inc. Glymur CRD";
> @@ -66,3 +67,334 @@ chosen {
> &tlmm {
> gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
> };
> +
> +&apps_rsc {
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + };
> +
> + regulators-0 {
> + compatible = "qcom,pmh0101-rpmh-regulators";
> + qcom,pmic-id = "B_E0";
> +
> + vdd-bob1-supply = <&vph_pwr>;
> + vdd-bob2-supply = <&vph_pwr>;
> + vdd-l1-l10-l15-supply = <&vreg_s9f_e0_1p9>;
> + vdd-l2-l7-l8-l9-l16-supply = <&vreg_bob1_e0>;
> + vdd-l11-l12-l18-supply = <&vreg_s7f_e0_1p32>;
> + vdd-l17-supply = <&vreg_bob2_e0>;
> +
> + vreg_bob1_e0: bob1 {
> + regulator-name = "vreg_bob1_e0";
> + regulator-min-microvolt = <2200000>;
> + regulator-max-microvolt = <4224000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_bob2_e0: bob2 {
> + regulator-name = "vreg_bob2_e0";
> + regulator-min-microvolt = <2540000>;
> + regulator-max-microvolt = <3600000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + };
> +
> + vreg_l1b_e0_1p8: ldo1 {
> + regulator-name = "vreg_l1b_e0_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2b_e0_2p9: ldo2 {
> + regulator-name = "vreg_l2b_e0_2p9";
> + regulator-min-microvolt = <2900000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7b_e0_2p79: ldo7 {
> + regulator-name = "vreg_l7b_e0_2p79";
> + regulator-min-microvolt = <2790000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l8b_e0_1p50: ldo8 {
> + regulator-name = "vreg_l8b_e0_1p50";
> + regulator-min-microvolt = <1504000>;
> + regulator-max-microvolt = <3544000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l9b_e0_2p7: ldo9 {
> + regulator-name = "vreg_l9b_e0_2p7";
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l10b_e0_1p8: ldo10 {
> + regulator-name = "vreg_l10b_e0_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l11b_e0_1p2: ldo11 {
> + regulator-name = "vreg_l11b_e0_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l12b_e0_1p14: ldo12 {
> + regulator-name = "vreg_l12b_e0_1p14";
> + regulator-min-microvolt = <1140000>;
> + regulator-max-microvolt = <1260000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l15b_e0_1p8: ldo15 {
> + regulator-name = "vreg_l15b_e0_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l17b_e0_2p4: ldo17 {
> + regulator-name = "vreg_l17b_e0_2p4";
> + regulator-min-microvolt = <2400000>;
> + regulator-max-microvolt = <2700000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l18b_e0_1p2: ldo18 {
> + regulator-name = "vreg_l18b_e0_1p2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-1 {
> + compatible = "qcom,pmcx0102-rpmh-regulators";
> + qcom,pmic-id = "C_E0";
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> +
> + vreg_s1c_e0_0p3: smps1 {
> + regulator-name = "vreg_s1c_e0_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s8c_e0_0p3: smps8 {
> + regulator-name = "vreg_s8c_e0_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-2 {
> + compatible = "qcom,pmcx0102-rpmh-regulators";
> + qcom,pmic-id = "C_E1";
> +
> + vdd-l2-supply = <&vreg_s7f_e0_1p32>;
> + vdd-l1-l3-l4-supply = <&vreg_s8f_e0_0p95>;
> +
> + vreg_l1c_e1_0p82: ldo1 {
> + regulator-name = "vreg_l1c_e1_0p82";
> + regulator-min-microvolt = <825000>;
> + regulator-max-microvolt = <958000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2c_e1_1p14: ldo2 {
> + regulator-name = "vreg_l2c_e1_1p14";
> + regulator-min-microvolt = <1140000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3c_e1_0p89: ldo3 {
> + regulator-name = "vreg_l3c_e1_0p89";
> + regulator-min-microvolt = <890000>;
> + regulator-max-microvolt = <980000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4c_e1_0p72: ldo4 {
> + regulator-name = "vreg_l4c_e1_0p72";
> + regulator-min-microvolt = <720000>;
> + regulator-max-microvolt = <980000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-3 {
> + compatible = "qcom,pmh0110-rpmh-regulators";
> + qcom,pmic-id = "F_E0";
> + vdd-s7-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> + vdd-s9-supply = <&vph_pwr>;
> + vdd-s10-supply = <&vph_pwr>;
> + vdd-l2-supply = <&vreg_s8f_e0_0p95>;
> + vdd-l3-supply = <&vreg_s8f_e0_0p95>;
> + vdd-l4-supply = <&vreg_s8f_e0_0p95>;
> +
> + vreg_s7f_e0_1p32: smps7 {
> + regulator-name = "vreg_s7f_e0_1p32";
> + regulator-min-microvolt = <1320000>;
> + regulator-max-microvolt = <1352000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s8f_e0_0p95: smps8 {
> + regulator-name = "vreg_s8f_e0_0p95";
> + regulator-min-microvolt = <952000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s9f_e0_1p9: smps9 {
> + regulator-name = "vreg_s9f_e0_1p9";
> + regulator-min-microvolt = <1900000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s10f_e0_0p3: smps10 {
> + regulator-name = "vreg_s10f_e0_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2f_e0_0p82: ldo2 {
> + regulator-name = "vreg_l2f_e0_0p82";
> + regulator-min-microvolt = <825000>;
> + regulator-max-microvolt = <980000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3f_e0_0p72: ldo3 {
> + regulator-name = "vreg_l3f_e0_0p72";
> + regulator-min-microvolt = <720000>;
> + regulator-max-microvolt = <980000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4f_e0_0p3: ldo4 {
> + regulator-name = "vreg_l4f_e0_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-4 {
> + compatible = "qcom,pmh0110-rpmh-regulators";
> + qcom,pmic-id = "F_E1";
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + vdd-s7-supply = <&vph_pwr>;
> + vdd-l1-supply = <&vreg_s8f_e0_0p95>;
> + vdd-l2-supply = <&vreg_s8f_e0_0p95>;
> + vdd-l4-supply = <&vreg_s8f_e0_0p95>;
> +
> + vreg_s1f_e1_0p3: smps1 {
> + regulator-name = "vreg_s1f_e1_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s5f_e1_0p3: smps5 {
> + regulator-name = "vreg_s5f_e1_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s6f_e1_0p3: smps6 {
> + regulator-name = "vreg_s6f_e1_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_s7f_e1_0p3: smps7 {
> + regulator-name = "vreg_s7f_e1_0p3";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l1f_e1_0p82: ldo1 {
> + regulator-name = "vreg_l1f_e1_0p82";
> + regulator-min-microvolt = <825000>;
> + regulator-max-microvolt = <950000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2f_e1_0p83: ldo2 {
> + regulator-name = "vreg_l2f_e1_0p83";
> + regulator-min-microvolt = <830000>;
> + regulator-max-microvolt = <920000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4f_e1_1p08: ldo4 {
> + regulator-name = "vreg_l4f_e1_1p08";
> + regulator-min-microvolt = <1080000>;
> + regulator-max-microvolt = <1320000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + regulators-5 {
> + compatible = "qcom,pmh0110-rpmh-regulators";
> + qcom,pmic-id = "H_E0";
> +
> + vdd-l1-supply = <&vreg_s8f_e0_0p95>;
> + vdd-l2-supply = <&vreg_s8f_e0_0p95>;
> + vdd-l3-supply = <&vreg_s9f_e0_1p9>;
> + vdd-l4-supply = <&vreg_s7f_e0_1p32>;
> +
> + vreg_l1h_e0_0p89: ldo1 {
> + regulator-name = "vreg_l1h_e0_0p89";
> + regulator-min-microvolt = <825000>;
> + regulator-max-microvolt = <950000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l2h_e0_0p72: ldo2 {
> + regulator-name = "vreg_l2h_e0_0p72";
> + regulator-min-microvolt = <830000>;
> + regulator-max-microvolt = <920000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3h_e0_0p32: ldo3 {
> + regulator-name = "vreg_l3h_e0_0p32";
> + regulator-min-microvolt = <320000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l4h_e0_1p2: ldo4 {
> + regulator-name = "vreg_l4h_e0_1p2";
> + regulator-min-microvolt = <1080000>;
> + regulator-max-microvolt = <1320000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +};
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-09-25 17:09 ` Bjorn Andersson
@ 2025-10-08 11:42 ` Pankaj Patil
0 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-10-08 11:42 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 9/25/2025 10:39 PM, Bjorn Andersson wrote:
> On Thu, Sep 25, 2025 at 12:02:17PM +0530, Pankaj Patil wrote:
>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>
>> Add RPMH regulator rails for Glymur CRD.
>>
> Please don't sprinkle board-specific changes throughout the series.
>
> It's useful to introduce the dts early on, so that any dtsi changes gets
> compiled, but you can then group the board-specific changes at the end
> of the series; and squash them into one.
>
> Regards,
> Bjorn
Sure, will organize the next revision in the same manner.
>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 332 ++++++++++++++++++++++++++++++++
>> 1 file changed, 332 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> index 4561c0b87b017cba0a1db8814123a070b37fd434..e89b81dcb4f47b78307fa3ab6831657cf6491c89 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> @@ -6,6 +6,7 @@
>> /dts-v1/;
>>
>> #include "glymur.dtsi"
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>>
>> / {
>> model = "Qualcomm Technologies, Inc. Glymur CRD";
>> @@ -66,3 +67,334 @@ chosen {
>> &tlmm {
>> gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
>> };
>> +
>> +&apps_rsc {
>> +
>> + vph_pwr: vph-pwr-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> + };
>> +
>> + regulators-0 {
>> + compatible = "qcom,pmh0101-rpmh-regulators";
>> + qcom,pmic-id = "B_E0";
>> +
>> + vdd-bob1-supply = <&vph_pwr>;
>> + vdd-bob2-supply = <&vph_pwr>;
>> + vdd-l1-l10-l15-supply = <&vreg_s9f_e0_1p9>;
>> + vdd-l2-l7-l8-l9-l16-supply = <&vreg_bob1_e0>;
>> + vdd-l11-l12-l18-supply = <&vreg_s7f_e0_1p32>;
>> + vdd-l17-supply = <&vreg_bob2_e0>;
>> +
>> + vreg_bob1_e0: bob1 {
>> + regulator-name = "vreg_bob1_e0";
>> + regulator-min-microvolt = <2200000>;
>> + regulator-max-microvolt = <4224000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
>> + };
>> +
>> + vreg_bob2_e0: bob2 {
>> + regulator-name = "vreg_bob2_e0";
>> + regulator-min-microvolt = <2540000>;
>> + regulator-max-microvolt = <3600000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
>> + };
>> +
>> + vreg_l1b_e0_1p8: ldo1 {
>> + regulator-name = "vreg_l1b_e0_1p8";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l2b_e0_2p9: ldo2 {
>> + regulator-name = "vreg_l2b_e0_2p9";
>> + regulator-min-microvolt = <2900000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l7b_e0_2p79: ldo7 {
>> + regulator-name = "vreg_l7b_e0_2p79";
>> + regulator-min-microvolt = <2790000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l8b_e0_1p50: ldo8 {
>> + regulator-name = "vreg_l8b_e0_1p50";
>> + regulator-min-microvolt = <1504000>;
>> + regulator-max-microvolt = <3544000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l9b_e0_2p7: ldo9 {
>> + regulator-name = "vreg_l9b_e0_2p7";
>> + regulator-min-microvolt = <2700000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l10b_e0_1p8: ldo10 {
>> + regulator-name = "vreg_l10b_e0_1p8";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l11b_e0_1p2: ldo11 {
>> + regulator-name = "vreg_l11b_e0_1p2";
>> + regulator-min-microvolt = <1200000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l12b_e0_1p14: ldo12 {
>> + regulator-name = "vreg_l12b_e0_1p14";
>> + regulator-min-microvolt = <1140000>;
>> + regulator-max-microvolt = <1260000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l15b_e0_1p8: ldo15 {
>> + regulator-name = "vreg_l15b_e0_1p8";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l17b_e0_2p4: ldo17 {
>> + regulator-name = "vreg_l17b_e0_2p4";
>> + regulator-min-microvolt = <2400000>;
>> + regulator-max-microvolt = <2700000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l18b_e0_1p2: ldo18 {
>> + regulator-name = "vreg_l18b_e0_1p2";
>> + regulator-min-microvolt = <1200000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> + };
>> +
>> + regulators-1 {
>> + compatible = "qcom,pmcx0102-rpmh-regulators";
>> + qcom,pmic-id = "C_E0";
>> + vdd-s1-supply = <&vph_pwr>;
>> + vdd-s8-supply = <&vph_pwr>;
>> +
>> + vreg_s1c_e0_0p3: smps1 {
>> + regulator-name = "vreg_s1c_e0_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_s8c_e0_0p3: smps8 {
>> + regulator-name = "vreg_s8c_e0_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> + };
>> +
>> + regulators-2 {
>> + compatible = "qcom,pmcx0102-rpmh-regulators";
>> + qcom,pmic-id = "C_E1";
>> +
>> + vdd-l2-supply = <&vreg_s7f_e0_1p32>;
>> + vdd-l1-l3-l4-supply = <&vreg_s8f_e0_0p95>;
>> +
>> + vreg_l1c_e1_0p82: ldo1 {
>> + regulator-name = "vreg_l1c_e1_0p82";
>> + regulator-min-microvolt = <825000>;
>> + regulator-max-microvolt = <958000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l2c_e1_1p14: ldo2 {
>> + regulator-name = "vreg_l2c_e1_1p14";
>> + regulator-min-microvolt = <1140000>;
>> + regulator-max-microvolt = <1300000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l3c_e1_0p89: ldo3 {
>> + regulator-name = "vreg_l3c_e1_0p89";
>> + regulator-min-microvolt = <890000>;
>> + regulator-max-microvolt = <980000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l4c_e1_0p72: ldo4 {
>> + regulator-name = "vreg_l4c_e1_0p72";
>> + regulator-min-microvolt = <720000>;
>> + regulator-max-microvolt = <980000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> + };
>> +
>> + regulators-3 {
>> + compatible = "qcom,pmh0110-rpmh-regulators";
>> + qcom,pmic-id = "F_E0";
>> + vdd-s7-supply = <&vph_pwr>;
>> + vdd-s8-supply = <&vph_pwr>;
>> + vdd-s9-supply = <&vph_pwr>;
>> + vdd-s10-supply = <&vph_pwr>;
>> + vdd-l2-supply = <&vreg_s8f_e0_0p95>;
>> + vdd-l3-supply = <&vreg_s8f_e0_0p95>;
>> + vdd-l4-supply = <&vreg_s8f_e0_0p95>;
>> +
>> + vreg_s7f_e0_1p32: smps7 {
>> + regulator-name = "vreg_s7f_e0_1p32";
>> + regulator-min-microvolt = <1320000>;
>> + regulator-max-microvolt = <1352000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_s8f_e0_0p95: smps8 {
>> + regulator-name = "vreg_s8f_e0_0p95";
>> + regulator-min-microvolt = <952000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_s9f_e0_1p9: smps9 {
>> + regulator-name = "vreg_s9f_e0_1p9";
>> + regulator-min-microvolt = <1900000>;
>> + regulator-max-microvolt = <2000000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_s10f_e0_0p3: smps10 {
>> + regulator-name = "vreg_s10f_e0_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l2f_e0_0p82: ldo2 {
>> + regulator-name = "vreg_l2f_e0_0p82";
>> + regulator-min-microvolt = <825000>;
>> + regulator-max-microvolt = <980000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l3f_e0_0p72: ldo3 {
>> + regulator-name = "vreg_l3f_e0_0p72";
>> + regulator-min-microvolt = <720000>;
>> + regulator-max-microvolt = <980000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l4f_e0_0p3: ldo4 {
>> + regulator-name = "vreg_l4f_e0_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> + };
>> +
>> + regulators-4 {
>> + compatible = "qcom,pmh0110-rpmh-regulators";
>> + qcom,pmic-id = "F_E1";
>> + vdd-s1-supply = <&vph_pwr>;
>> + vdd-s3-supply = <&vph_pwr>;
>> + vdd-s5-supply = <&vph_pwr>;
>> + vdd-s6-supply = <&vph_pwr>;
>> + vdd-s7-supply = <&vph_pwr>;
>> + vdd-l1-supply = <&vreg_s8f_e0_0p95>;
>> + vdd-l2-supply = <&vreg_s8f_e0_0p95>;
>> + vdd-l4-supply = <&vreg_s8f_e0_0p95>;
>> +
>> + vreg_s1f_e1_0p3: smps1 {
>> + regulator-name = "vreg_s1f_e1_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_s5f_e1_0p3: smps5 {
>> + regulator-name = "vreg_s5f_e1_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_s6f_e1_0p3: smps6 {
>> + regulator-name = "vreg_s6f_e1_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_s7f_e1_0p3: smps7 {
>> + regulator-name = "vreg_s7f_e1_0p3";
>> + regulator-min-microvolt = <300000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l1f_e1_0p82: ldo1 {
>> + regulator-name = "vreg_l1f_e1_0p82";
>> + regulator-min-microvolt = <825000>;
>> + regulator-max-microvolt = <950000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l2f_e1_0p83: ldo2 {
>> + regulator-name = "vreg_l2f_e1_0p83";
>> + regulator-min-microvolt = <830000>;
>> + regulator-max-microvolt = <920000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l4f_e1_1p08: ldo4 {
>> + regulator-name = "vreg_l4f_e1_1p08";
>> + regulator-min-microvolt = <1080000>;
>> + regulator-max-microvolt = <1320000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> + };
>> +
>> + regulators-5 {
>> + compatible = "qcom,pmh0110-rpmh-regulators";
>> + qcom,pmic-id = "H_E0";
>> +
>> + vdd-l1-supply = <&vreg_s8f_e0_0p95>;
>> + vdd-l2-supply = <&vreg_s8f_e0_0p95>;
>> + vdd-l3-supply = <&vreg_s9f_e0_1p9>;
>> + vdd-l4-supply = <&vreg_s7f_e0_1p32>;
>> +
>> + vreg_l1h_e0_0p89: ldo1 {
>> + regulator-name = "vreg_l1h_e0_0p89";
>> + regulator-min-microvolt = <825000>;
>> + regulator-max-microvolt = <950000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l2h_e0_0p72: ldo2 {
>> + regulator-name = "vreg_l2h_e0_0p72";
>> + regulator-min-microvolt = <830000>;
>> + regulator-max-microvolt = <920000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l3h_e0_0p32: ldo3 {
>> + regulator-name = "vreg_l3h_e0_0p32";
>> + regulator-min-microvolt = <320000>;
>> + regulator-max-microvolt = <2000000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> +
>> + vreg_l4h_e0_1p2: ldo4 {
>> + regulator-name = "vreg_l4h_e0_1p2";
>> + regulator-min-microvolt = <1080000>;
>> + regulator-max-microvolt = <1320000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + };
>> + };
>> +};
>>
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-09-25 6:32 ` [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails Pankaj Patil
2025-09-25 11:01 ` Konrad Dybcio
2025-09-25 17:09 ` Bjorn Andersson
@ 2025-10-11 11:31 ` Abel Vesa
2025-10-11 15:56 ` Dmitry Baryshkov
2 siblings, 1 reply; 125+ messages in thread
From: Abel Vesa @ 2025-10-11 11:31 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Kamal Wadhwa
On 25-09-25 12:02:17, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add RPMH regulator rails for Glymur CRD.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 332 ++++++++++++++++++++++++++++++++
> 1 file changed, 332 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index 4561c0b87b017cba0a1db8814123a070b37fd434..e89b81dcb4f47b78307fa3ab6831657cf6491c89 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "glymur.dtsi"
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>
> / {
> model = "Qualcomm Technologies, Inc. Glymur CRD";
> @@ -66,3 +67,334 @@ chosen {
> &tlmm {
> gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
> };
> +
> +&apps_rsc {
> +
> + vph_pwr: vph-pwr-regulator {
dtbs_check gives this:
arch/arm64/boot/dts/qcom/glymur-crd.dtb: rsc@18900000 (qcom,rpmh-rsc): 'vph-pwr-regulator' does not match any of the regexes: '^pinctrl-[0-9]+$', '^regulators(-[0-9])?$'
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
so node name needs to be regulator-vph-pwr instead.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
2025-10-11 11:31 ` Abel Vesa
@ 2025-10-11 15:56 ` Dmitry Baryshkov
0 siblings, 0 replies; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-11 15:56 UTC (permalink / raw)
To: Abel Vesa
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Kamal Wadhwa
On Sat, Oct 11, 2025 at 02:31:27PM +0300, Abel Vesa wrote:
> On 25-09-25 12:02:17, Pankaj Patil wrote:
> > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >
> > Add RPMH regulator rails for Glymur CRD.
> >
> > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/glymur-crd.dts | 332 ++++++++++++++++++++++++++++++++
> > 1 file changed, 332 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> > index 4561c0b87b017cba0a1db8814123a070b37fd434..e89b81dcb4f47b78307fa3ab6831657cf6491c89 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> > @@ -6,6 +6,7 @@
> > /dts-v1/;
> >
> > #include "glymur.dtsi"
> > +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> >
> > / {
> > model = "Qualcomm Technologies, Inc. Glymur CRD";
> > @@ -66,3 +67,334 @@ chosen {
> > &tlmm {
> > gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
> > };
> > +
> > +&apps_rsc {
> > +
> > + vph_pwr: vph-pwr-regulator {
>
> dtbs_check gives this:
>
> arch/arm64/boot/dts/qcom/glymur-crd.dtb: rsc@18900000 (qcom,rpmh-rsc): 'vph-pwr-regulator' does not match any of the regexes: '^pinctrl-[0-9]+$', '^regulators(-[0-9])?$'
> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
>
> so node name needs to be regulator-vph-pwr instead.
Actually not just that. VPH-PWR is not a part of the apps-rsc (why is it
even there??). It should be a part of the board DTS.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (8 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 10:31 ` Konrad Dybcio
2025-10-06 14:27 ` Krzysztof Kozlowski
2025-09-25 6:32 ` [PATCH 11/24] arm64: dts: qcom: Add PMCX0102 pmic dtsi Pankaj Patil
` (14 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add spmi-pmic-arb device for the SPMI PMIC arbiter found on
Glymur. It has three subnodes corresponding to the SPMI0,
SPMI1 & SPMI2 bus controllers.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 62 ++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 2632ef381687c2392f8fad0294901e33887ac4d3..e6e001485747785fd29c606773cba7793bbd2a5c 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2600,6 +2600,68 @@ sram@c30f000 {
reg = <0x0 0x0c30f000 0x0 0x400>;
};
+ pmic_arbiter: arbiter@c400000 {
+ compatible = "qcom,glymur-spmi-pmic-arb";
+ reg = <0x0 0x0c400000 0x0 0x00003000>,
+ <0x0 0x0c900000 0x0 0x00400000>,
+ <0x0 0x0c4c0000 0x0 0x00400000>,
+ <0x0 0x0c403000 0x0 0x00008000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "chnl_map";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ qcom,channel = <0>;
+ qcom,ee = <0>;
+
+ spmi_bus0: spmi@c426000 {
+ reg = <0x0 0x0c426000 0x0 0x00004000>,
+ <0x0 0x0c8c0000 0x0 0x00010000>,
+ <0x0 0x0c42a000 0x0 0x00008000>;
+ reg-names = "cnfg",
+ "intr",
+ "chnl_owner";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ spmi_bus1: spmi@c437000 {
+ reg = <0x0 0x0c437000 0x0 0x00004000>,
+ <0x0 0x0c8d0000 0x0 0x00010000>,
+ <0x0 0x0c43b000 0x0 0x00008000>;
+ reg-names = "cnfg",
+ "intr",
+ "chnl_owner";
+ interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ spmi_bus2: spmi@c48000 {
+ reg = <0x0 0x0c448000 0x0 0x00004000>,
+ <0x0 0x0c8e0000 0x0 0x00010000>,
+ <0x0 0x0c44c000 0x0 0x00008000>;
+ reg-names = "cnfg",
+ "intr",
+ "chnl_owner";
+ interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,glymur-tlmm";
reg = <0x0 0x0f100000 0x0 0xf00000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device
2025-09-25 6:32 ` [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device Pankaj Patil
@ 2025-09-25 10:31 ` Konrad Dybcio
2025-10-06 14:27 ` Krzysztof Kozlowski
1 sibling, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:31 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add spmi-pmic-arb device for the SPMI PMIC arbiter found on
> Glymur. It has three subnodes corresponding to the SPMI0,
> SPMI1 & SPMI2 bus controllers.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 62 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 2632ef381687c2392f8fad0294901e33887ac4d3..e6e001485747785fd29c606773cba7793bbd2a5c 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2600,6 +2600,68 @@ sram@c30f000 {
> reg = <0x0 0x0c30f000 0x0 0x400>;
> };
>
> + pmic_arbiter: arbiter@c400000 {
Is this label going to be used?
> + compatible = "qcom,glymur-spmi-pmic-arb";
> + reg = <0x0 0x0c400000 0x0 0x00003000>,
> + <0x0 0x0c900000 0x0 0x00400000>,
> + <0x0 0x0c4c0000 0x0 0x00400000>,
> + <0x0 0x0c403000 0x0 0x00008000>;
Drop the padding from the size fields, please
Konrad
> + reg-names = "core",
> + "chnls",
> + "obsrvr",
> + "chnl_map";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + qcom,channel = <0>;
> + qcom,ee = <0>;
> +
> + spmi_bus0: spmi@c426000 {
> + reg = <0x0 0x0c426000 0x0 0x00004000>,
> + <0x0 0x0c8c0000 0x0 0x00010000>,
> + <0x0 0x0c42a000 0x0 0x00008000>;
> + reg-names = "cnfg",
> + "intr",
> + "chnl_owner";
> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "periph_irq";
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + spmi_bus1: spmi@c437000 {
> + reg = <0x0 0x0c437000 0x0 0x00004000>,
> + <0x0 0x0c8d0000 0x0 0x00010000>,
> + <0x0 0x0c43b000 0x0 0x00008000>;
> + reg-names = "cnfg",
> + "intr",
> + "chnl_owner";
> + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "periph_irq";
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + spmi_bus2: spmi@c48000 {
> + reg = <0x0 0x0c448000 0x0 0x00004000>,
> + <0x0 0x0c8e0000 0x0 0x00010000>,
> + <0x0 0x0c44c000 0x0 0x00008000>;
> + reg-names = "cnfg",
> + "intr",
> + "chnl_owner";
> + interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "periph_irq";
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> + };
> +
> tlmm: pinctrl@f100000 {
> compatible = "qcom,glymur-tlmm";
> reg = <0x0 0x0f100000 0x0 0xf00000>;
>
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device
2025-09-25 6:32 ` [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device Pankaj Patil
2025-09-25 10:31 ` Konrad Dybcio
@ 2025-10-06 14:27 ` Krzysztof Kozlowski
1 sibling, 0 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 14:27 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 25/09/2025 15:32, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add spmi-pmic-arb device for the SPMI PMIC arbiter found on
> Glymur. It has three subnodes corresponding to the SPMI0,
> SPMI1 & SPMI2 bus controllers.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 62 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 2632ef381687c2392f8fad0294901e33887ac4d3..e6e001485747785fd29c606773cba7793bbd2a5c 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2600,6 +2600,68 @@ sram@c30f000 {
> reg = <0x0 0x0c30f000 0x0 0x400>;
> };
>
> + pmic_arbiter: arbiter@c400000 {
Two nods per patch? One more patch clearly wrongly split. This must be
squashed.
NAK
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 11/24] arm64: dts: qcom: Add PMCX0102 pmic dtsi
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (9 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 6:32 ` [PATCH 12/24] arm64: dts: qcom: Add SMB2370 " Pankaj Patil
` (13 subsequent siblings)
24 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add base DTS file for PMCX0102 along with temp-alarm and GPIO
nodes.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 179 +++++++++++++++++++++++++++++++++
1 file changed, 179 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..839738dda6cd5016df134a2fddd92d3ae7c56133
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus0 {
+ pmcx0102_c_e0: pmic@2 {
+ compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcx0102_c_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmcx0102_c_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmcx0102_c_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmcx0102_d_e0: pmic@3 {
+ compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcx0102_d_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmcx0102_d_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmcx0102_d_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmcx0102_e_e0: pmic@4 {
+ compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcx0102_e_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmcx0102_e_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmcx0102_e_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmcx0102_g_e0: pmic@5 {
+ compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
+ reg = <0x6 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcx0102_g_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmcx0102_g_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmcx0102_g_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+&spmi_bus1 {
+ pmcx0102_c_e1: pmic@2 {
+ compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcx0102_c_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmcx0102_c_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmcx0102_c_e1_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmcx0102_d_e1: pmic@3 {
+ compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcx0102_d_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmcx0102_d_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmcx0102_d_e1_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmcx0102_e_e1: pmic@4 {
+ compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcx0102_e_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmcx0102_e_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmcx0102_e_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* [PATCH 12/24] arm64: dts: qcom: Add SMB2370 pmic dtsi
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (10 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 11/24] arm64: dts: qcom: Add PMCX0102 pmic dtsi Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 6:32 ` [PATCH 13/24] arm64: dts: qcom: Update pmh0104 dtsi for Glymur CRD Pankaj Patil
` (12 subsequent siblings)
24 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add base DTS file for SMB2370 along with the eUSB repeater
node.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 +++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qcom/smb2370.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..80f3fdae5705044b5bd422ac3fc3a6fa6b0fc23c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+&spmi_bus2 {
+ smb2370_j_e2: pmic@9 {
+ compatible = "qcom,smb2370", "qcom,spmi-pmic";
+ reg = <0x9 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ smb2370_j_e2_eusb2_repeater: phy@fd00 {
+ compatible = "qcom,smb2370-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ };
+ };
+
+ smb2370_k_e2: pmic@a {
+ compatible = "qcom,smb2370", "qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ smb2370_k_e2_eusb2_repeater: phy@fd00 {
+ compatible = "qcom,smb2370-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ };
+ };
+
+ smb2370_l_e2: pmic@b {
+ compatible = "qcom,smb2370", "qcom,spmi-pmic";
+ reg = <0xb SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ smb2370_l_e2_eusb2_repeater: phy@fd00 {
+ compatible = "qcom,smb2370-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* [PATCH 13/24] arm64: dts: qcom: Update pmh0104 dtsi for Glymur CRD
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (11 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 12/24] arm64: dts: qcom: Add SMB2370 " Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 6:32 ` [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur Pankaj Patil
` (11 subsequent siblings)
24 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Update the pmh0104.dtsi to include multiple instances of PMH0104
DT nodes, one for each SID assigned to this PMIC on the spmi_bus0
and spmi_bus1 in Glymur CRD board.
Take care to avoid compilation issue with the existing nodes by
gaurding each PMH0104 nodes with `#ifdef` for its corresponding
SID macro. So that only the nodes which have the their SID macro
defined are the only ones picked for compilation.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmh0104.dtsi | 84 +++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmh0104.dtsi b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
index f5393fdebe957ea0caf4bbc16117374b4759bda3..d3ea7486d842ec813a79268fc1466e1513426d78 100644
--- a/arch/arm64/boot/dts/qcom/pmh0104.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
@@ -6,7 +6,63 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
+&spmi_bus0 {
+#ifdef PMH0104_I_E0_SID
+ pmh0104_i_e0: pmic@PMH0104_I_E0_SID {
+ compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+ reg = <PMH0104_I_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0104_i_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0104_I_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0104_i_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
+
+#ifdef PMH0104_J_E0_SID
+ pmh0104_j_e0: pmic@PMH0104_J_E0_SID {
+ compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+ reg = <PMH0104_J_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmh0104_j_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0104_J_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0104_j_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
+};
+
&spmi_bus1 {
+#ifdef PMH0104_J_E1_SID
pmh0104_j_e1: pmic@PMH0104_J_E1_SID {
compatible = "qcom,pmh0104", "qcom,spmi-pmic";
reg = <PMH0104_J_E1_SID SPMI_USID>;
@@ -30,4 +86,32 @@ pmh0104_j_e1_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+
+#ifdef PMH0104_L_E1_SID
+ pmh0104_l_e1: pmic@PMH0104_L_E1_SID {
+ compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+ reg = <PMH0104_L_E1_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0104_l_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0104_L_E1_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0104_l_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (12 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 13/24] arm64: dts: qcom: Update pmh0104 dtsi for Glymur CRD Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 8:08 ` Krzysztof Kozlowski
2025-09-25 6:32 ` [PATCH 15/24] arm64: dts: qcom: glymur: Add PMICs dtsi for CRD Pankaj Patil
` (10 subsequent siblings)
24 siblings, 1 reply; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add multiple instance of PMH0110 DT node, one for each assigned
SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
CRD.
Take care to avoid compilation issue with the existing nodes by
gaurding each PMH0110 nodes with `#ifdef` for its corresponding
SID macro. So that only the nodes which have the their SID macro
defined are the only ones picked for compilation.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
--- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
@@ -7,6 +7,8 @@
#include <dt-bindings/spmi/spmi.h>
&spmi_bus0 {
+
+#ifdef PMH0110_D_E0_SID
pmh0110_d_e0: pmic@PMH0110_D_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_D_E0_SID SPMI_USID>;
@@ -31,13 +33,14 @@ pmh0110_d_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+#ifdef PMH0110_F_E0_SID
pmh0110_f_e0: pmic@PMH0110_F_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_F_E0_SID SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
pmh0110_f_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
@@ -56,7 +59,9 @@ pmh0110_f_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+#ifdef PMH0110_G_E0_SID
pmh0110_g_e0: pmic@PMH0110_G_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_G_E0_SID SPMI_USID>;
@@ -81,7 +86,36 @@ pmh0110_g_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+
+#ifdef PMH0110_H_E0_SID
+ pmh0110_h_e0: pmic@PMH0110_H_E0_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_H_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_h_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_H_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_h_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
+#ifdef PMH0110_I_E0_SID
pmh0110_i_e0: pmic@PMH0110_I_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_I_E0_SID SPMI_USID>;
@@ -106,4 +140,34 @@ pmh0110_i_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+};
+
+&spmi_bus1 {
+#ifdef PMH0110_F_E1_SID
+ pmh0110_f_e1: pmic@PMH0110_F_E1_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_F_E1_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_f_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_F_E1_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_f_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-09-25 6:32 ` [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur Pankaj Patil
@ 2025-09-25 8:08 ` Krzysztof Kozlowski
2025-09-25 13:14 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:08 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Kamal Wadhwa
On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
<pankaj.patil@oss.qualcomm.com> wrote:
>
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add multiple instance of PMH0110 DT node, one for each assigned
> SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
> CRD.
>
> Take care to avoid compilation issue with the existing nodes by
> gaurding each PMH0110 nodes with `#ifdef` for its corresponding
> SID macro. So that only the nodes which have the their SID macro
> defined are the only ones picked for compilation.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
> --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> @@ -7,6 +7,8 @@
> #include <dt-bindings/spmi/spmi.h>
>
> &spmi_bus0 {
> +
> +#ifdef PMH0110_D_E0_SID
NAK
I already explained on IRC in great details why.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-09-25 8:08 ` Krzysztof Kozlowski
@ 2025-09-25 13:14 ` Dmitry Baryshkov
2025-09-25 13:34 ` Krzysztof Kozlowski
0 siblings, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 13:14 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Kamal Wadhwa
On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> <pankaj.patil@oss.qualcomm.com> wrote:
> >
> > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >
> > Add multiple instance of PMH0110 DT node, one for each assigned
> > SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
> > CRD.
> >
> > Take care to avoid compilation issue with the existing nodes by
> > gaurding each PMH0110 nodes with `#ifdef` for its corresponding
> > SID macro. So that only the nodes which have the their SID macro
> > defined are the only ones picked for compilation.
> >
> > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
> > 1 file changed, 65 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
> > --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > @@ -7,6 +7,8 @@
> > #include <dt-bindings/spmi/spmi.h>
> >
> > &spmi_bus0 {
> > +
> > +#ifdef PMH0110_D_E0_SID
>
> NAK
>
> I already explained on IRC in great details why.
A short summary or a link to a channel / date would be nice in order to
include other people into the discussion.
>
> Best regards,
> Krzysztof
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-09-25 13:14 ` Dmitry Baryshkov
@ 2025-09-25 13:34 ` Krzysztof Kozlowski
2025-09-25 14:00 ` Konrad Dybcio
2025-09-25 18:57 ` Dmitry Baryshkov
0 siblings, 2 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 13:34 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Kamal Wadhwa
On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
> > On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> > <pankaj.patil@oss.qualcomm.com> wrote:
> > >
> > > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > >
> > > Add multiple instance of PMH0110 DT node, one for each assigned
> > > SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
> > > CRD.
> > >
> > > Take care to avoid compilation issue with the existing nodes by
> > > gaurding each PMH0110 nodes with `#ifdef` for its corresponding
> > > SID macro. So that only the nodes which have the their SID macro
> > > defined are the only ones picked for compilation.
> > >
> > > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
> > > 1 file changed, 65 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
> > > --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > @@ -7,6 +7,8 @@
> > > #include <dt-bindings/spmi/spmi.h>
> > >
> > > &spmi_bus0 {
> > > +
> > > +#ifdef PMH0110_D_E0_SID
> >
> > NAK
> >
> > I already explained on IRC in great details why.
>
> A short summary or a link to a channel / date would be nice in order to
> include other people into the discussion.
>
Of course but:
1. You were there so maybe you remember the arguments, and:
2. I'm offline, using phone, not having laptop, replying during my
personal time off just before merge window so any emergency time
should be spent on important matters instead these two huge patch
bombs adding such usage I already said: NO, don't do this.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-09-25 13:34 ` Krzysztof Kozlowski
@ 2025-09-25 14:00 ` Konrad Dybcio
2025-09-25 18:57 ` Dmitry Baryshkov
1 sibling, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 14:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Dmitry Baryshkov
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Kamal Wadhwa
On 9/25/25 3:34 PM, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>
>> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>>> <pankaj.patil@oss.qualcomm.com> wrote:
[...]
>>> NAK
>>>
>>> I already explained on IRC in great details why.
>>
>> A short summary or a link to a channel / date would be nice in order to
>> include other people into the discussion.
>>
>
> Of course but:
> 1. You were there so maybe you remember the arguments, and:
> 2. I'm offline, using phone, not having laptop, replying during my
> personal time off just before merge window so any emergency time
> should be spent on important matters instead these two huge patch
> bombs adding such usage I already said: NO, don't do this.
Thanks for being dedicated to the cause - however since we're right
around the merge window, it's safe to assume these larger changes will
not be picked up, and we don't really expect you to reply immediately
There's a lot of code, so we'll definitely want you to take another
look at it after you're back (and before it gets merged)
Enjoy your time off!
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-09-25 13:34 ` Krzysztof Kozlowski
2025-09-25 14:00 ` Konrad Dybcio
@ 2025-09-25 18:57 ` Dmitry Baryshkov
2025-10-08 7:31 ` Kamal Wadhwa
1 sibling, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 18:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Kamal Wadhwa
On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >
> > On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
> > > On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> > > <pankaj.patil@oss.qualcomm.com> wrote:
> > > >
> > > > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > > >
> > > > Add multiple instance of PMH0110 DT node, one for each assigned
> > > > SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
> > > > CRD.
> > > >
> > > > Take care to avoid compilation issue with the existing nodes by
> > > > gaurding each PMH0110 nodes with `#ifdef` for its corresponding
> > > > SID macro. So that only the nodes which have the their SID macro
> > > > defined are the only ones picked for compilation.
> > > >
> > > > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > > ---
> > > > arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
> > > > 1 file changed, 65 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > > index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
> > > > --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > > @@ -7,6 +7,8 @@
> > > > #include <dt-bindings/spmi/spmi.h>
> > > >
> > > > &spmi_bus0 {
> > > > +
> > > > +#ifdef PMH0110_D_E0_SID
> > >
> > > NAK
> > >
> > > I already explained on IRC in great details why.
> >
> > A short summary or a link to a channel / date would be nice in order to
> > include other people into the discussion.
> >
>
> Of course but:
> 1. You were there so maybe you remember the arguments, and:
> 2. I'm offline, using phone, not having laptop, replying during my
> personal time off just before merge window so any emergency time
> should be spent on important matters instead these two huge patch
> bombs adding such usage I already said: NO, don't do this.
Well, If I'm asking, it means I don't rememebr the discussion. And I
defeinitely didn't know that you are spending your personal vacation
time in ML. And if the discussion was with some other people, then
somebody else can drop the response to the question.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-09-25 18:57 ` Dmitry Baryshkov
@ 2025-10-08 7:31 ` Kamal Wadhwa
2025-10-08 8:02 ` Krzysztof Kozlowski
2025-10-08 9:15 ` Konrad Dybcio
0 siblings, 2 replies; 125+ messages in thread
From: Kamal Wadhwa @ 2025-10-08 7:31 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
Hi Krzysztof, Dmitry, Konrad,
On Thu, Sep 25, 2025 at 09:57:02PM +0300, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote:
> > On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
> > <dmitry.baryshkov@oss.qualcomm.com> wrote:
> > >
> > > On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
> > > > On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> > > > <pankaj.patil@oss.qualcomm.com> wrote:
> > > > >
> > > > > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > > > >
> > > > > Add multiple instance of PMH0110 DT node, one for each assigned
> > > > > SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
> > > > > CRD.
> > > > >
> > > > > Take care to avoid compilation issue with the existing nodes by
> > > > > gaurding each PMH0110 nodes with `#ifdef` for its corresponding
> > > > > SID macro. So that only the nodes which have the their SID macro
> > > > > defined are the only ones picked for compilation.
> > > > >
> > > > > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > > > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > > > ---
> > > > > arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
> > > > > 1 file changed, 65 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > > > index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > > > +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> > > > > @@ -7,6 +7,8 @@
> > > > > #include <dt-bindings/spmi/spmi.h>
> > > > >
> > > > > &spmi_bus0 {
> > > > > +
> > > > > +#ifdef PMH0110_D_E0_SID
> > > >
> > > > NAK
> > > >
> > > > I already explained on IRC in great details why.
> > >
> > > A short summary or a link to a channel / date would be nice in order to
> > > include other people into the discussion.
> > >
> >
> > Of course but:
> > 1. You were there so maybe you remember the arguments, and:
> > 2. I'm offline, using phone, not having laptop, replying during my
> > personal time off just before merge window so any emergency time
> > should be spent on important matters instead these two huge patch
> > bombs adding such usage I already said: NO, don't do this.
>
>
> Well, If I'm asking, it means I don't rememebr the discussion. And I
> defeinitely didn't know that you are spending your personal vacation
> time in ML. And if the discussion was with some other people, then
> somebody else can drop the response to the question.
Just wanted to give some background on this patch.
Even though PMH0104 and PMH0110 are common (b/w Kaanapali and Glymur),
they don't share the SIDs. So we tried to use status="disabled" to handle
this but we observed that because of the node name being common in the
two included files, it ends up overwriting the previous node with the
same name.
eg-
#include "pmh0104.dtsi" // assume contains pmic@4 { ...};
#include "pmh0110.dtsi" // assume contains pmic@4 { status=disabled;};
Here intention was to use the pmh0104 on sid-4, but it gets overwritten
with the pmh0110 on sid-4 ( with status disabled). This is why we ended
up using the `#ifdef`, ensuring that we can control the exact pmic that
gets picked by using the PMXXX_SID macro.
side note, i did `grep` in the `/arch/arm64/boot/dts/` and i see a lot
of instances of `#if...` present in that. Assuming the concern here is
about the use of `#ifdef`.
Can you suggest some alternative approach?
or comment on below approaches:-
1. Can I use `pmic@pm0104_d_e0` ?
This may work but looks like a departure from the current format
i.e `pmic@<sid>` used in the arch/arm64/boot/dts/qcom.
2. Create PMIC-ID based pmic dts? `pmh0104_d_e0.dtsi` and likewise add all
pmics? But this could mean creating too many pmic files and end up
bloating the dts/qcom/ directory.
3. Add the nodes directly inside glymur-pmics.dtsi ( not using #include)?
It may make the file too long and IMO it may take slightly more time, to
look at the file and tell what PMICs are present and at what SID.
Please share if you prefer any of the above suggestions? or a completely
different approach to get around this. ( or if the current NAK'ed patch
can somehow be improved still? or share link for old discussion so i can
study it)
Would value any advice that you can share. Thanks in advance!
>
> --
> With best wishes
> Dmitry
Regards,
Kamal
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-10-08 7:31 ` Kamal Wadhwa
@ 2025-10-08 8:02 ` Krzysztof Kozlowski
2025-10-08 11:25 ` Krzysztof Kozlowski
2025-10-08 9:15 ` Konrad Dybcio
1 sibling, 1 reply; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-08 8:02 UTC (permalink / raw)
To: Kamal Wadhwa, Dmitry Baryshkov
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Abel Vesa
On 08/10/2025 16:31, Kamal Wadhwa wrote:
> Hi Krzysztof, Dmitry, Konrad,
>
> On Thu, Sep 25, 2025 at 09:57:02PM +0300, Dmitry Baryshkov wrote:
>> On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote:
>>> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>>
>>>> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
>>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>>>>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>>>>
>>>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>>
>>>>>> Add multiple instance of PMH0110 DT node, one for each assigned
>>>>>> SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
>>>>>> CRD.
>>>>>>
>>>>>> Take care to avoid compilation issue with the existing nodes by
>>>>>> gaurding each PMH0110 nodes with `#ifdef` for its corresponding
>>>>>> SID macro. So that only the nodes which have the their SID macro
>>>>>> defined are the only ones picked for compilation.
>>>>>>
>>>>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
>>>>>> 1 file changed, 65 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>> index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>> @@ -7,6 +7,8 @@
>>>>>> #include <dt-bindings/spmi/spmi.h>
>>>>>>
>>>>>> &spmi_bus0 {
>>>>>> +
>>>>>> +#ifdef PMH0110_D_E0_SID
>>>>>
>>>>> NAK
>>>>>
>>>>> I already explained on IRC in great details why.
>>>>
>>>> A short summary or a link to a channel / date would be nice in order to
>>>> include other people into the discussion.
>>>>
>>>
>>> Of course but:
>>> 1. You were there so maybe you remember the arguments, and:
>>> 2. I'm offline, using phone, not having laptop, replying during my
>>> personal time off just before merge window so any emergency time
>>> should be spent on important matters instead these two huge patch
>>> bombs adding such usage I already said: NO, don't do this.
>>
>>
>> Well, If I'm asking, it means I don't rememebr the discussion. And I
>> defeinitely didn't know that you are spending your personal vacation
>> time in ML. And if the discussion was with some other people, then
>> somebody else can drop the response to the question.
>
> Just wanted to give some background on this patch.
> Even though PMH0104 and PMH0110 are common (b/w Kaanapali and Glymur),
> they don't share the SIDs. So we tried to use status="disabled" to handle
> this but we observed that because of the node name being common in the
> two included files, it ends up overwriting the previous node with the
> same name.
>
> eg-
> #include "pmh0104.dtsi" // assume contains pmic@4 { ...};
> #include "pmh0110.dtsi" // assume contains pmic@4 { status=disabled;};
>
> Here intention was to use the pmh0104 on sid-4, but it gets overwritten
> with the pmh0110 on sid-4 ( with status disabled). This is why we ended
> up using the `#ifdef`, ensuring that we can control the exact pmic that
> gets picked by using the PMXXX_SID macro.
>
> side note, i did `grep` in the `/arch/arm64/boot/dts/` and i see a lot
> of instances of `#if...` present in that. Assuming the concern here is
> about the use of `#ifdef`.
#if are not desired in C code, so why would they be acceptable in DTS?
It is not making the code easier to read at all.
On IRC in these older discussions I was very strongly against any DTSI
which depends on some sort of outside values, except basic usage of
defines. Original pmh0110.dtsi from kaanapali is fine:
pmh0110_d_e0: pmic@PMH0110_D_E0_SID {
but doing ifdefs here that this define depends on something else makes
code ungreppable (lookup unit address from sysfs and then git grep
pmic@4) and difficult to follow.
My recommendation is either duplicate code or change DTSI files to not
contain entire node, but its contents. At least these are
recommendations I remember now.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-10-08 8:02 ` Krzysztof Kozlowski
@ 2025-10-08 11:25 ` Krzysztof Kozlowski
2025-10-10 11:26 ` Kamal Wadhwa
0 siblings, 1 reply; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-08 11:25 UTC (permalink / raw)
To: Kamal Wadhwa, Dmitry Baryshkov
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Abel Vesa
On 08/10/2025 17:02, Krzysztof Kozlowski wrote:
> On 08/10/2025 16:31, Kamal Wadhwa wrote:
>> Hi Krzysztof, Dmitry, Konrad,
>>
>> On Thu, Sep 25, 2025 at 09:57:02PM +0300, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote:
>>>> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
>>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>>>
>>>>> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
>>>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>>>>>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>>>>>
>>>>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>>>
>>>>>>> Add multiple instance of PMH0110 DT node, one for each assigned
>>>>>>> SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
>>>>>>> CRD.
>>>>>>>
>>>>>>> Take care to avoid compilation issue with the existing nodes by
>>>>>>> gaurding each PMH0110 nodes with `#ifdef` for its corresponding
>>>>>>> SID macro. So that only the nodes which have the their SID macro
>>>>>>> defined are the only ones picked for compilation.
>>>>>>>
>>>>>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>>>>>> ---
>>>>>>> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
>>>>>>> 1 file changed, 65 insertions(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>>> index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
>>>>>>> --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>>> @@ -7,6 +7,8 @@
>>>>>>> #include <dt-bindings/spmi/spmi.h>
>>>>>>>
>>>>>>> &spmi_bus0 {
>>>>>>> +
>>>>>>> +#ifdef PMH0110_D_E0_SID
>>>>>>
>>>>>> NAK
>>>>>>
>>>>>> I already explained on IRC in great details why.
>>>>>
>>>>> A short summary or a link to a channel / date would be nice in order to
>>>>> include other people into the discussion.
>>>>>
>>>>
>>>> Of course but:
>>>> 1. You were there so maybe you remember the arguments, and:
>>>> 2. I'm offline, using phone, not having laptop, replying during my
>>>> personal time off just before merge window so any emergency time
>>>> should be spent on important matters instead these two huge patch
>>>> bombs adding such usage I already said: NO, don't do this.
>>>
>>>
>>> Well, If I'm asking, it means I don't rememebr the discussion. And I
>>> defeinitely didn't know that you are spending your personal vacation
>>> time in ML. And if the discussion was with some other people, then
>>> somebody else can drop the response to the question.
>>
>> Just wanted to give some background on this patch.
>> Even though PMH0104 and PMH0110 are common (b/w Kaanapali and Glymur),
>> they don't share the SIDs. So we tried to use status="disabled" to handle
>> this but we observed that because of the node name being common in the
>> two included files, it ends up overwriting the previous node with the
>> same name.
>>
>> eg-
>> #include "pmh0104.dtsi" // assume contains pmic@4 { ...};
>> #include "pmh0110.dtsi" // assume contains pmic@4 { status=disabled;};
>>
>> Here intention was to use the pmh0104 on sid-4, but it gets overwritten
>> with the pmh0110 on sid-4 ( with status disabled). This is why we ended
>> up using the `#ifdef`, ensuring that we can control the exact pmic that
>> gets picked by using the PMXXX_SID macro.
>>
>> side note, i did `grep` in the `/arch/arm64/boot/dts/` and i see a lot
>> of instances of `#if...` present in that. Assuming the concern here is
>> about the use of `#ifdef`.
>
>
> #if are not desired in C code, so why would they be acceptable in DTS?
> It is not making the code easier to read at all.
>
> On IRC in these older discussions I was very strongly against any DTSI
> which depends on some sort of outside values, except basic usage of
> defines. Original pmh0110.dtsi from kaanapali is fine:
> pmh0110_d_e0: pmic@PMH0110_D_E0_SID {
>
> but doing ifdefs here that this define depends on something else makes
> code ungreppable (lookup unit address from sysfs and then git grep
> pmic@4) and difficult to follow.
>
> My recommendation is either duplicate code or change DTSI files to not
> contain entire node, but its contents. At least these are
> recommendations I remember now.
>
One more recommendation:
Different DTSI files per SoC, so pmh0110-kaanapali.dtsi and
pmh0110-glymur.dtsi.
We do not move the QUP engines into separate DTSI file to avoid
duplication. Each SoC has all of them duplicated. And then new SoC also
duplicates them.
We do not move SPI touchscreens or other I2C/SPI devices to separate
DTSI files. Each board duplicates such SPI device (and SPI can have
different <reg> - chip select! I2C as well, although a bit rarer).
Therefore I do not see any need for some #ifdefs in this code, just to
avoid duplication because that duplication is nothing odd.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-10-08 11:25 ` Krzysztof Kozlowski
@ 2025-10-10 11:26 ` Kamal Wadhwa
0 siblings, 0 replies; 125+ messages in thread
From: Kamal Wadhwa @ 2025-10-10 11:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Dmitry Baryshkov, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, Abel Vesa
Hi Krzysztof,
On Wed, Oct 08, 2025 at 08:25:51PM +0900, Krzysztof Kozlowski wrote:
> On 08/10/2025 17:02, Krzysztof Kozlowski wrote:
> > On 08/10/2025 16:31, Kamal Wadhwa wrote:
> >> Hi Krzysztof, Dmitry, Konrad,
> >>
> >> On Thu, Sep 25, 2025 at 09:57:02PM +0300, Dmitry Baryshkov wrote:
> >>> On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote:
> >>>> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
> >>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >>>>>
> >>>>> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
> >>>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> >>>>>> <pankaj.patil@oss.qualcomm.com> wrote:
> >>>>>>>
> >>>>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >>>>>>>
> >>>>>>> Add multiple instance of PMH0110 DT node, one for each assigned
> >>>>>>> SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
> >>>>>>> CRD.
> >>>>>>>
> >>>>>>> Take care to avoid compilation issue with the existing nodes by
> >>>>>>> gaurding each PMH0110 nodes with `#ifdef` for its corresponding
> >>>>>>> SID macro. So that only the nodes which have the their SID macro
> >>>>>>> defined are the only ones picked for compilation.
> >>>>>>>
> >>>>>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >>>>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> >>>>>>> ---
> >>>>>>> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
> >>>>>>> 1 file changed, 65 insertions(+), 1 deletion(-)
> >>>>>>>
> >>>>>>> diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> >>>>>>> index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
> >>>>>>> --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> >>>>>>> +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
> >>>>>>> @@ -7,6 +7,8 @@
> >>>>>>> #include <dt-bindings/spmi/spmi.h>
> >>>>>>>
> >>>>>>> &spmi_bus0 {
> >>>>>>> +
> >>>>>>> +#ifdef PMH0110_D_E0_SID
> >>>>>>
> >>>>>> NAK
> >>>>>>
> >>>>>> I already explained on IRC in great details why.
> >>>>>
> >>>>> A short summary or a link to a channel / date would be nice in order to
> >>>>> include other people into the discussion.
> >>>>>
> >>>>
> >>>> Of course but:
> >>>> 1. You were there so maybe you remember the arguments, and:
> >>>> 2. I'm offline, using phone, not having laptop, replying during my
> >>>> personal time off just before merge window so any emergency time
> >>>> should be spent on important matters instead these two huge patch
> >>>> bombs adding such usage I already said: NO, don't do this.
> >>>
> >>>
> >>> Well, If I'm asking, it means I don't rememebr the discussion. And I
> >>> defeinitely didn't know that you are spending your personal vacation
> >>> time in ML. And if the discussion was with some other people, then
> >>> somebody else can drop the response to the question.
> >>
> >> Just wanted to give some background on this patch.
> >> Even though PMH0104 and PMH0110 are common (b/w Kaanapali and Glymur),
> >> they don't share the SIDs. So we tried to use status="disabled" to handle
> >> this but we observed that because of the node name being common in the
> >> two included files, it ends up overwriting the previous node with the
> >> same name.
> >>
> >> eg-
> >> #include "pmh0104.dtsi" // assume contains pmic@4 { ...};
> >> #include "pmh0110.dtsi" // assume contains pmic@4 { status=disabled;};
> >>
> >> Here intention was to use the pmh0104 on sid-4, but it gets overwritten
> >> with the pmh0110 on sid-4 ( with status disabled). This is why we ended
> >> up using the `#ifdef`, ensuring that we can control the exact pmic that
> >> gets picked by using the PMXXX_SID macro.
> >>
> >> side note, i did `grep` in the `/arch/arm64/boot/dts/` and i see a lot
> >> of instances of `#if...` present in that. Assuming the concern here is
> >> about the use of `#ifdef`.
> >
> >
> > #if are not desired in C code, so why would they be acceptable in DTS?
> > It is not making the code easier to read at all.
> >
> > On IRC in these older discussions I was very strongly against any DTSI
> > which depends on some sort of outside values, except basic usage of
> > defines. Original pmh0110.dtsi from kaanapali is fine:
> > pmh0110_d_e0: pmic@PMH0110_D_E0_SID {
> >
> > but doing ifdefs here that this define depends on something else makes
> > code ungreppable (lookup unit address from sysfs and then git grep
> > pmic@4) and difficult to follow.
> >
> > My recommendation is either duplicate code or change DTSI files to not
> > contain entire node, but its contents. At least these are
> > recommendations I remember now.
> >
> One more recommendation:
> Different DTSI files per SoC, so pmh0110-kaanapali.dtsi and
> pmh0110-glymur.dtsi.
Thanks for this suggestion.
- So for the common pmics between the Kaanapali and Glymur, we are going to
postfix the soc name.
- Files pmk8550.dtsi, pmh0101.dtsi which are exactly same between kaanapali
and glymur we will continue to use the same name.
This is how the #includes will look (after dropping #ifdefs)
+#include "pmk8850.dtsi" /* SPMI0: SID-0 */
+#include "pmh0101.dtsi" /* SPMI0: SID-1 */
+#include "pmcx0102.dtsi" /* SPMI0: SID-2/3/4/6 SPMI1: SID-2/3/4 */
+#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */
+#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */
+#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */
(hope this is alright now?)
Regards,
Kamal
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-10-08 7:31 ` Kamal Wadhwa
2025-10-08 8:02 ` Krzysztof Kozlowski
@ 2025-10-08 9:15 ` Konrad Dybcio
2025-10-10 12:08 ` Aiqun(Maria) Yu
1 sibling, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-08 9:15 UTC (permalink / raw)
To: Kamal Wadhwa, Dmitry Baryshkov
Cc: Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On 10/8/25 9:31 AM, Kamal Wadhwa wrote:
> Hi Krzysztof, Dmitry, Konrad,
>
> On Thu, Sep 25, 2025 at 09:57:02PM +0300, Dmitry Baryshkov wrote:
>> On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote:
>>> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>>
>>>> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
>>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>>>>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>>>>
>>>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>>
>>>>>> Add multiple instance of PMH0110 DT node, one for each assigned
>>>>>> SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
>>>>>> CRD.
>>>>>>
>>>>>> Take care to avoid compilation issue with the existing nodes by
>>>>>> gaurding each PMH0110 nodes with `#ifdef` for its corresponding
>>>>>> SID macro. So that only the nodes which have the their SID macro
>>>>>> defined are the only ones picked for compilation.
>>>>>>
>>>>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
>>>>>> 1 file changed, 65 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>> index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>> @@ -7,6 +7,8 @@
>>>>>> #include <dt-bindings/spmi/spmi.h>
>>>>>>
>>>>>> &spmi_bus0 {
>>>>>> +
>>>>>> +#ifdef PMH0110_D_E0_SID
>>>>>
>>>>> NAK
>>>>>
>>>>> I already explained on IRC in great details why.
>>>>
>>>> A short summary or a link to a channel / date would be nice in order to
>>>> include other people into the discussion.
>>>>
>>>
>>> Of course but:
>>> 1. You were there so maybe you remember the arguments, and:
>>> 2. I'm offline, using phone, not having laptop, replying during my
>>> personal time off just before merge window so any emergency time
>>> should be spent on important matters instead these two huge patch
>>> bombs adding such usage I already said: NO, don't do this.
>>
>>
>> Well, If I'm asking, it means I don't rememebr the discussion. And I
>> defeinitely didn't know that you are spending your personal vacation
>> time in ML. And if the discussion was with some other people, then
>> somebody else can drop the response to the question.
>
> Just wanted to give some background on this patch.
> Even though PMH0104 and PMH0110 are common (b/w Kaanapali and Glymur),
> they don't share the SIDs. So we tried to use status="disabled" to handle
> this but we observed that because of the node name being common in the
> two included files, it ends up overwriting the previous node with the
> same name.
>
> eg-
> #include "pmh0104.dtsi" // assume contains pmic@4 { ...};
> #include "pmh0110.dtsi" // assume contains pmic@4 { status=disabled;};
>
> Here intention was to use the pmh0104 on sid-4, but it gets overwritten
> with the pmh0110 on sid-4 ( with status disabled). This is why we ended
> up using the `#ifdef`, ensuring that we can control the exact pmic that
> gets picked by using the PMXXX_SID macro.
>
> side note, i did `grep` in the `/arch/arm64/boot/dts/` and i see a lot
> of instances of `#if...` present in that. Assuming the concern here is
> about the use of `#ifdef`.
>
> Can you suggest some alternative approach?
> or comment on below approaches:-
>
> 1. Can I use `pmic@pm0104_d_e0` ?
> This may work but looks like a departure from the current format
> i.e `pmic@<sid>` used in the arch/arm64/boot/dts/qcom.
>
> 2. Create PMIC-ID based pmic dts? `pmh0104_d_e0.dtsi` and likewise add all
> pmics? But this could mean creating too many pmic files and end up
> bloating the dts/qcom/ directory.
>
> 3. Add the nodes directly inside glymur-pmics.dtsi ( not using #include)?
This is what we did for x1e after similar conundrums
It adds up to the maintenance cost in theory, but the alternative was worse
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
2025-10-08 9:15 ` Konrad Dybcio
@ 2025-10-10 12:08 ` Aiqun(Maria) Yu
0 siblings, 0 replies; 125+ messages in thread
From: Aiqun(Maria) Yu @ 2025-10-10 12:08 UTC (permalink / raw)
To: Konrad Dybcio, Kamal Wadhwa, Dmitry Baryshkov
Cc: Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On 10/8/2025 5:15 PM, Konrad Dybcio wrote:
> On 10/8/25 9:31 AM, Kamal Wadhwa wrote:
>> Hi Krzysztof, Dmitry, Konrad,
>>
>> On Thu, Sep 25, 2025 at 09:57:02PM +0300, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote:
>>>> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov
>>>> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>>>>>
>>>>> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote:
>>>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>>>>>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>>>>>
>>>>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>>>
>>>>>>> Add multiple instance of PMH0110 DT node, one for each assigned
>>>>>>> SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
>>>>>>> CRD.
>>>>>>>
>>>>>>> Take care to avoid compilation issue with the existing nodes by
>>>>>>> gaurding each PMH0110 nodes with `#ifdef` for its corresponding
>>>>>>> SID macro. So that only the nodes which have the their SID macro
>>>>>>> defined are the only ones picked for compilation.
>>>>>>>
>>>>>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>>>>>> ---
>>>>>>> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
>>>>>>> 1 file changed, 65 insertions(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>>> index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
>>>>>>> --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
>>>>>>> @@ -7,6 +7,8 @@
>>>>>>> #include <dt-bindings/spmi/spmi.h>
>>>>>>>
>>>>>>> &spmi_bus0 {
>>>>>>> +
>>>>>>> +#ifdef PMH0110_D_E0_SID
>>>>>>
>>>>>> NAK
>>>>>>
>>>>>> I already explained on IRC in great details why.
>>>>>
>>>>> A short summary or a link to a channel / date would be nice in order to
>>>>> include other people into the discussion.
>>>>>
>>>>
>>>> Of course but:
>>>> 1. You were there so maybe you remember the arguments, and:
>>>> 2. I'm offline, using phone, not having laptop, replying during my
>>>> personal time off just before merge window so any emergency time
>>>> should be spent on important matters instead these two huge patch
>>>> bombs adding such usage I already said: NO, don't do this.
>>>
>>>
>>> Well, If I'm asking, it means I don't rememebr the discussion. And I
>>> defeinitely didn't know that you are spending your personal vacation
>>> time in ML. And if the discussion was with some other people, then
>>> somebody else can drop the response to the question.
>>
>> Just wanted to give some background on this patch.
>> Even though PMH0104 and PMH0110 are common (b/w Kaanapali and Glymur),
>> they don't share the SIDs. So we tried to use status="disabled" to handle
>> this but we observed that because of the node name being common in the
>> two included files, it ends up overwriting the previous node with the
>> same name.
>>
>> eg-
>> #include "pmh0104.dtsi" // assume contains pmic@4 { ...};
>> #include "pmh0110.dtsi" // assume contains pmic@4 { status=disabled;};
>>
>> Here intention was to use the pmh0104 on sid-4, but it gets overwritten
>> with the pmh0110 on sid-4 ( with status disabled). This is why we ended
>> up using the `#ifdef`, ensuring that we can control the exact pmic that
>> gets picked by using the PMXXX_SID macro.
>>
>> side note, i did `grep` in the `/arch/arm64/boot/dts/` and i see a lot
>> of instances of `#if...` present in that. Assuming the concern here is
>> about the use of `#ifdef`.
>>
>> Can you suggest some alternative approach?
>> or comment on below approaches:-
>>
>> 1. Can I use `pmic@pm0104_d_e0` ?
>> This may work but looks like a departure from the current format
>> i.e `pmic@<sid>` used in the arch/arm64/boot/dts/qcom.
>>
>> 2. Create PMIC-ID based pmic dts? `pmh0104_d_e0.dtsi` and likewise add all
>> pmics? But this could mean creating too many pmic files and end up
>> bloating the dts/qcom/ directory.
>>
>> 3. Add the nodes directly inside glymur-pmics.dtsi ( not using #include)?
>
> This is what we did for x1e after similar conundrums
>
> It adds up to the maintenance cost in theory, but the alternative was worse
It seems a common scenario for different targets!
Considering that a PMIC chip can be reused across different targets—and
even within a single platform multiple instances of the same PMIC may
exist—it might be beneficial to define separate common DTSI files for
each allocated SID."
When the device tree is another language to interpret the hardware,
shall we change the sentence more easily structured?
For example, kaanapali actually have 4*PMH0110 mounted with SPMI0, and
each PMH0110 have different SID(3, 5, 6, 8) allocated like(pseudocode,
not tested, just for better understanding the ideas):
#define PMH0110_D_E0_SID 3
#include "pmh0110_spmi0".dtsi
#define PMH0110_F_E0_SID 5
#include "pmh0110_spmi0".dtsi
#define PMH0110_G_E0_SID 6
#include "pmh0110_spmi0".dtsi
#define PMH0110_I_E0_SID 8
#include "pmh0110_spmi0".dtsi
Glymur actually have 3*PMH0110 mounted 2 with SPMI0,, and the other one
with SPMI1, and each PMH0110 have different SID allocated(pseudocode,
not tested, just for better understanding the ideas):
#define PMH0110_SPMI0 0x1
#include "pmh0110_spmi0".dtsi
#define PMH0110_SPMI0 0x7
#include "pmh0110_spmi0".dtsi
#define PMH0110_SPMI1 0x5
#define "pmh0110_spmi1".dtsi
Request a brainstorming here. Welcome the ideas!
>
> Konrad
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 15/24] arm64: dts: qcom: glymur: Add PMICs dtsi for CRD
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (13 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 6:32 ` [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support Pankaj Patil
` (9 subsequent siblings)
24 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Include all the PMICs present on the Glymur board into
the glymur CRD DTS file.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 1 +
arch/arm64/boot/dts/qcom/glymur-pmics.dtsi | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index e89b81dcb4f47b78307fa3ab6831657cf6491c89..97f6eedd7222368f5cbfdd02e9c4d87261d7f19a 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "glymur.dtsi"
+#include "glymur-pmics.dtsi"
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
/ {
diff --git a/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi b/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..59dcfb67a203a7c576406037377fc9fbdce51a97
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/glymur-pmics.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#define PMH0110_F_E0 0x5
+#define PMH0110_H_E0 0x7
+#define PMH0104_I_E0 0x8
+#define PMH0104_J_E0 0x9
+
+#define PMH0110_F_E1 0x5
+#define PMH0104_L_E1 0xb
+
+#include "pmk8850.dtsi" /* SPMI0: SID-0*/
+#include "pmh0101.dtsi" /* SPMI0: SID-1*/
+#include "pmcx0102.dtsi" /* SPMI0: SID-2/3/4/6 SPMI1: SID-2/3/4 */
+#include "pmh0110.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */
+#include "pmh0104.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */
+#include "smb2370.dtsi" /* SPMI2: SID-9/10/11*/
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (14 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 15/24] arm64: dts: qcom: glymur: Add PMICs dtsi for CRD Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 11:16 ` Konrad Dybcio
2025-10-06 14:28 ` Krzysztof Kozlowski
2025-09-25 6:32 ` [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure Pankaj Patil
` (8 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add Volume Down/Up keys for Glymur CRD.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 97f6eedd7222368f5cbfdd02e9c4d87261d7f19a..d6003ae515e37049fdf17d6b604b974dc8e9fbbc 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -63,12 +63,42 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&key_vol_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
};
&tlmm {
gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
};
+&pmh0101_gpios {
+ key_vol_up_default: key-vol-up-default-state {
+ pins = "gpio6";
+ function = "gpio";
+ output-disable;
+ bias-pull-up;
+ };
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
&apps_rsc {
vph_pwr: vph-pwr-regulator {
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support
2025-09-25 6:32 ` [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support Pankaj Patil
@ 2025-09-25 11:16 ` Konrad Dybcio
2025-10-01 13:48 ` Kamal Wadhwa
2025-10-06 14:28 ` Krzysztof Kozlowski
1 sibling, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 11:16 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add Volume Down/Up keys for Glymur CRD.
Does the CRD have these physical keys, or are they routed to the
debug board?
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support
2025-09-25 11:16 ` Konrad Dybcio
@ 2025-10-01 13:48 ` Kamal Wadhwa
2025-10-06 8:56 ` Konrad Dybcio
0 siblings, 1 reply; 125+ messages in thread
From: Kamal Wadhwa @ 2025-10-01 13:48 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
Hi Konrad,
On Thu, Sep 25, 2025 at 4:46 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
> > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >
> > Add Volume Down/Up keys for Glymur CRD.
>
> Does the CRD have these physical keys, or are they routed to the
> debug board?
Yes, it seems to be routed only over the debug board.
The keyboard too has the vol+ key, but seems no direct key having
vol+/gpio6 on CRD.
(sorry should this patch be dropped then for this reason i guess?)
>
> Konrad
Regards,
Kamal
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support
2025-10-01 13:48 ` Kamal Wadhwa
@ 2025-10-06 8:56 ` Konrad Dybcio
0 siblings, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-06 8:56 UTC (permalink / raw)
To: Kamal Wadhwa
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 10/1/25 3:48 PM, Kamal Wadhwa wrote:
> Hi Konrad,
>
> On Thu, Sep 25, 2025 at 4:46 PM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>
>>> Add Volume Down/Up keys for Glymur CRD.
>>
>> Does the CRD have these physical keys, or are they routed to the
>> debug board?
>
> Yes, it seems to be routed only over the debug board.
> The keyboard too has the vol+ key, but seems no direct key having
> vol+/gpio6 on CRD.
> (sorry should this patch be dropped then for this reason i guess?)
I think it's fine, but it would be nice to mention this
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support
2025-09-25 6:32 ` [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support Pankaj Patil
2025-09-25 11:16 ` Konrad Dybcio
@ 2025-10-06 14:28 ` Krzysztof Kozlowski
1 sibling, 0 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 14:28 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 25/09/2025 15:32, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add Volume Down/Up keys for Glymur CRD.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
You cannot even get subjects right in this big patchset, because of this
weird split of patches.
Squash it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (15 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 8:11 ` Krzysztof Kozlowski
2025-09-25 6:32 ` [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node Pankaj Patil
` (7 subsequent siblings)
24 siblings, 1 reply; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
On Glymur boards, the RTC alarm interrupts are routed to SOCCP
subsystems and are not available to APPS. This can cause the
RTC probe failure as the RTC IRQ registration will fail in
probe.
Fix this issue by adding `no-alarm` property in the RTC DT
node. This will skip the RTC alarm irq registration and
the RTC probe will return success.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index d6003ae515e37049fdf17d6b604b974dc8e9fbbc..b04c0ed28468620673237fffb4013adacc7ef7ba 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -429,3 +429,7 @@ vreg_l4h_e0_1p2: ldo4 {
};
};
};
+
+&pmk8850_rtc {
+ no-alarm;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-09-25 6:32 ` [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure Pankaj Patil
@ 2025-09-25 8:11 ` Krzysztof Kozlowski
2025-10-01 12:23 ` Kamal Wadhwa
0 siblings, 1 reply; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:11 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Kamal Wadhwa
On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
<pankaj.patil@oss.qualcomm.com> wrote:
>
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
> subsystems and are not available to APPS. This can cause the
> RTC probe failure as the RTC IRQ registration will fail in
> probe.
>
> Fix this issue by adding `no-alarm` property in the RTC DT
> node. This will skip the RTC alarm irq registration and
> the RTC probe will return success.
This is ridiculous. You just added glymur CRD and you claim now that
it's broken and you need to fix it. So just fix that commit!
This is gross misinterpretation of splitting patchset, some twisted
LWN stats work.
NAK
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-09-25 8:11 ` Krzysztof Kozlowski
@ 2025-10-01 12:23 ` Kamal Wadhwa
2025-10-06 14:28 ` Konrad Dybcio
2025-10-06 14:32 ` Krzysztof Kozlowski
0 siblings, 2 replies; 125+ messages in thread
From: Kamal Wadhwa @ 2025-10-01 12:23 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
Hi Krzysztof,
On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> <pankaj.patil@oss.qualcomm.com> wrote:
> >
> > From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >
> > On Glymur boards, the RTC alarm interrupts are routed to SOCCP
> > subsystems and are not available to APPS. This can cause the
> > RTC probe failure as the RTC IRQ registration will fail in
> > probe.
> >
> > Fix this issue by adding `no-alarm` property in the RTC DT
> > node. This will skip the RTC alarm irq registration and
> > the RTC probe will return success.
>
>
> This is ridiculous. You just added glymur CRD and you claim now that
> it's broken and you need to fix it. So just fix that commit!
I'm afraid, but this is an actual limitation we have for Glymur
(compared to Kaanapali).
The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
IRQ permission for the RTC peripheral.
So we need this extra change in Glymur explicitly as a workaround to
make RTC register
properly.
But sure, we can squash this into the main DT patch, if you think this
is not a limitation
that needs to be highlighted in a separate patch.
>
> This is a gross misinterpretation of splitting patchset, some twisted
> LWN stats work.
Sorry for this. It was not intentional (definitely not for LWN stats),
mainly this happened
because this is how individual driver owners/teams internally added
their patches. So
this is how they ended up being sent out. But we understand it is an
inconvenience for
reviewers to go over multiple patches and squash it all one patch.
Will take care of this in the next version (and in future).
Again, sorry for the trouble.
>
> NAK
Regards,
Kamal
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-10-01 12:23 ` Kamal Wadhwa
@ 2025-10-06 14:28 ` Konrad Dybcio
2025-10-13 11:04 ` Kamal Wadhwa
2025-10-06 14:32 ` Krzysztof Kozlowski
1 sibling, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-06 14:28 UTC (permalink / raw)
To: Kamal Wadhwa, Krzysztof Kozlowski
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 10/1/25 2:23 PM, Kamal Wadhwa wrote:
> Hi Krzysztof,
>
> On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>
>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>
>>> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
>>> subsystems and are not available to APPS. This can cause the
>>> RTC probe failure as the RTC IRQ registration will fail in
>>> probe.
>>>
>>> Fix this issue by adding `no-alarm` property in the RTC DT
>>> node. This will skip the RTC alarm irq registration and
>>> the RTC probe will return success.
>>
>>
>> This is ridiculous. You just added glymur CRD and you claim now that
>> it's broken and you need to fix it. So just fix that commit!
>
> I'm afraid, but this is an actual limitation we have for Glymur
> (compared to Kaanapali).
> The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
> Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
> IRQ permission for the RTC peripheral.
This is interesting.. is that a physical limitation, or some sort of
a software security policy?
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-10-06 14:28 ` Konrad Dybcio
@ 2025-10-13 11:04 ` Kamal Wadhwa
2025-10-14 10:23 ` Konrad Dybcio
0 siblings, 1 reply; 125+ messages in thread
From: Kamal Wadhwa @ 2025-10-13 11:04 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On Mon, Oct 06, 2025 at 04:28:59PM +0200, Konrad Dybcio wrote:
> On 10/1/25 2:23 PM, Kamal Wadhwa wrote:
> > Hi Krzysztof,
> >
> > On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> >> <pankaj.patil@oss.qualcomm.com> wrote:
> >>>
> >>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >>>
> >>> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
> >>> subsystems and are not available to APPS. This can cause the
> >>> RTC probe failure as the RTC IRQ registration will fail in
> >>> probe.
> >>>
> >>> Fix this issue by adding `no-alarm` property in the RTC DT
> >>> node. This will skip the RTC alarm irq registration and
> >>> the RTC probe will return success.
> >>
> >>
> >> This is ridiculous. You just added glymur CRD and you claim now that
> >> it's broken and you need to fix it. So just fix that commit!
> >
> > I'm afraid, but this is an actual limitation we have for Glymur
> > (compared to Kaanapali).
> > The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
> > Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
> > IRQ permission for the RTC peripheral.
>
> This is interesting.. is that a physical limitation, or some sort of
> a software security policy?
This is mostly a limitation for all compute targets(like Glymur). On compute
targets we need to support ACPI TAD feature[1] this feature uses the RTC alarm.
In a nutshell, this feature implements 2 times - AC ( adaptor power) and
DC (battery power) timers, and based on active power source(AC or DC?) at the
time of timer expiry device will either go for a full bootup or stay in power
down.
This feature is implemented on a different subsystem (SoCCP subsystem), and
since the SPMI `IRQ` permissions can only be assigned to only one subsystem,
so we can't use the alarms on APPS. This is why we use no-alarms DT to register
RTC device without alarm-irq support.
[1] TAD specification - https://uefi.org/sites/default/files/resources/ACPI_5.pdf
section 9.18
Regards,
Kamal
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-10-13 11:04 ` Kamal Wadhwa
@ 2025-10-14 10:23 ` Konrad Dybcio
2025-10-14 12:36 ` Kamal Wadhwa
0 siblings, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-14 10:23 UTC (permalink / raw)
To: Kamal Wadhwa
Cc: Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On 10/13/25 1:04 PM, Kamal Wadhwa wrote:
> On Mon, Oct 06, 2025 at 04:28:59PM +0200, Konrad Dybcio wrote:
>> On 10/1/25 2:23 PM, Kamal Wadhwa wrote:
>>> Hi Krzysztof,
>>>
>>> On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>
>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>>>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>>>
>>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>
>>>>> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
>>>>> subsystems and are not available to APPS. This can cause the
>>>>> RTC probe failure as the RTC IRQ registration will fail in
>>>>> probe.
>>>>>
>>>>> Fix this issue by adding `no-alarm` property in the RTC DT
>>>>> node. This will skip the RTC alarm irq registration and
>>>>> the RTC probe will return success.
>>>>
>>>>
>>>> This is ridiculous. You just added glymur CRD and you claim now that
>>>> it's broken and you need to fix it. So just fix that commit!
>>>
>>> I'm afraid, but this is an actual limitation we have for Glymur
>>> (compared to Kaanapali).
>>> The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
>>> Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
>>> IRQ permission for the RTC peripheral.
>>
>> This is interesting.. is that a physical limitation, or some sort of
>> a software security policy?
>
> This is mostly a limitation for all compute targets(like Glymur). On compute
> targets we need to support ACPI TAD feature[1] this feature uses the RTC alarm.
> In a nutshell, this feature implements 2 times - AC ( adaptor power) and
> DC (battery power) timers, and based on active power source(AC or DC?) at the
> time of timer expiry device will either go for a full bootup or stay in power
> down.
>
> This feature is implemented on a different subsystem (SoCCP subsystem), and
> since the SPMI `IRQ` permissions can only be assigned to only one subsystem,
> so we can't use the alarms on APPS. This is why we use no-alarms DT to register
> RTC device without alarm-irq support.
>
> [1] TAD specification - https://uefi.org/sites/default/files/resources/ACPI_5.pdf
> section 9.18
Hm, is there maybe some sort of an interface to talk to the SoCCP
and set the RTC as we wish, from the OS?
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-10-14 10:23 ` Konrad Dybcio
@ 2025-10-14 12:36 ` Kamal Wadhwa
2025-10-14 19:52 ` Dmitry Baryshkov
2025-10-20 11:54 ` Konrad Dybcio
0 siblings, 2 replies; 125+ messages in thread
From: Kamal Wadhwa @ 2025-10-14 12:36 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
Hi Konrad,
On Tue, Oct 14, 2025 at 12:23:23PM +0200, Konrad Dybcio wrote:
> On 10/13/25 1:04 PM, Kamal Wadhwa wrote:
> > On Mon, Oct 06, 2025 at 04:28:59PM +0200, Konrad Dybcio wrote:
> >> On 10/1/25 2:23 PM, Kamal Wadhwa wrote:
> >>> Hi Krzysztof,
> >>>
> >>> On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>>>
> >>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> >>>> <pankaj.patil@oss.qualcomm.com> wrote:
> >>>>>
> >>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> >>>>>
> >>>>> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
> >>>>> subsystems and are not available to APPS. This can cause the
> >>>>> RTC probe failure as the RTC IRQ registration will fail in
> >>>>> probe.
> >>>>>
> >>>>> Fix this issue by adding `no-alarm` property in the RTC DT
> >>>>> node. This will skip the RTC alarm irq registration and
> >>>>> the RTC probe will return success.
> >>>>
> >>>>
> >>>> This is ridiculous. You just added glymur CRD and you claim now that
> >>>> it's broken and you need to fix it. So just fix that commit!
> >>>
> >>> I'm afraid, but this is an actual limitation we have for Glymur
> >>> (compared to Kaanapali).
> >>> The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
> >>> Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
> >>> IRQ permission for the RTC peripheral.
> >>
> >> This is interesting.. is that a physical limitation, or some sort of
> >> a software security policy?
> >
> > This is mostly a limitation for all compute targets(like Glymur). On compute
> > targets we need to support ACPI TAD feature[1] this feature uses the RTC alarm.
> > In a nutshell, this feature implements 2 times - AC ( adaptor power) and
> > DC (battery power) timers, and based on active power source(AC or DC?) at the
> > time of timer expiry device will either go for a full bootup or stay in power
> > down.
> >
> > This feature is implemented on a different subsystem (SoCCP subsystem), and
> > since the SPMI `IRQ` permissions can only be assigned to only one subsystem,
> > so we can't use the alarms on APPS. This is why we use no-alarms DT to register
> > RTC device without alarm-irq support.
> >
> > [1] TAD specification - https://uefi.org/sites/default/files/resources/ACPI_5.pdf
> > section 9.18
>
> Hm, is there maybe some sort of an interface to talk to the SoCCP
> and set the RTC as we wish, from the OS?
Yes, the developement is almost done and we have done some testing as well, but
that kernel driver needs some more cleanup and testing before posting to
upstream. This will be added in future.
>
> Konrad
Regards,
Kamal
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-10-14 12:36 ` Kamal Wadhwa
@ 2025-10-14 19:52 ` Dmitry Baryshkov
2025-10-20 11:54 ` Konrad Dybcio
1 sibling, 0 replies; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-14 19:52 UTC (permalink / raw)
To: Kamal Wadhwa
Cc: Konrad Dybcio, Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel
On Tue, Oct 14, 2025 at 06:06:58PM +0530, Kamal Wadhwa wrote:
> Hi Konrad,
>
> On Tue, Oct 14, 2025 at 12:23:23PM +0200, Konrad Dybcio wrote:
> > On 10/13/25 1:04 PM, Kamal Wadhwa wrote:
> > > On Mon, Oct 06, 2025 at 04:28:59PM +0200, Konrad Dybcio wrote:
> > >> On 10/1/25 2:23 PM, Kamal Wadhwa wrote:
> > >>> Hi Krzysztof,
> > >>>
> > >>> On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > >>>>
> > >>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> > >>>> <pankaj.patil@oss.qualcomm.com> wrote:
> > >>>>>
> > >>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> > >>>>>
> > >>>>> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
> > >>>>> subsystems and are not available to APPS. This can cause the
> > >>>>> RTC probe failure as the RTC IRQ registration will fail in
> > >>>>> probe.
> > >>>>>
> > >>>>> Fix this issue by adding `no-alarm` property in the RTC DT
> > >>>>> node. This will skip the RTC alarm irq registration and
> > >>>>> the RTC probe will return success.
> > >>>>
> > >>>>
> > >>>> This is ridiculous. You just added glymur CRD and you claim now that
> > >>>> it's broken and you need to fix it. So just fix that commit!
> > >>>
> > >>> I'm afraid, but this is an actual limitation we have for Glymur
> > >>> (compared to Kaanapali).
> > >>> The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
> > >>> Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
> > >>> IRQ permission for the RTC peripheral.
> > >>
> > >> This is interesting.. is that a physical limitation, or some sort of
> > >> a software security policy?
> > >
> > > This is mostly a limitation for all compute targets(like Glymur). On compute
> > > targets we need to support ACPI TAD feature[1] this feature uses the RTC alarm.
> > > In a nutshell, this feature implements 2 times - AC ( adaptor power) and
> > > DC (battery power) timers, and based on active power source(AC or DC?) at the
> > > time of timer expiry device will either go for a full bootup or stay in power
> > > down.
> > >
> > > This feature is implemented on a different subsystem (SoCCP subsystem), and
> > > since the SPMI `IRQ` permissions can only be assigned to only one subsystem,
> > > so we can't use the alarms on APPS. This is why we use no-alarms DT to register
> > > RTC device without alarm-irq support.
> > >
> > > [1] TAD specification - https://uefi.org/sites/default/files/resources/ACPI_5.pdf
> > > section 9.18
> >
> > Hm, is there maybe some sort of an interface to talk to the SoCCP
> > and set the RTC as we wish, from the OS?
>
> Yes, the developement is almost done and we have done some testing as well, but
> that kernel driver needs some more cleanup and testing before posting to
> upstream. This will be added in future.
If the series is reposted, please add a comment, pointing out that this
is a temporal measure and should be removed later.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-10-14 12:36 ` Kamal Wadhwa
2025-10-14 19:52 ` Dmitry Baryshkov
@ 2025-10-20 11:54 ` Konrad Dybcio
1 sibling, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-20 11:54 UTC (permalink / raw)
To: Kamal Wadhwa
Cc: Krzysztof Kozlowski, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel
On 10/14/25 2:36 PM, Kamal Wadhwa wrote:
> Hi Konrad,
>
> On Tue, Oct 14, 2025 at 12:23:23PM +0200, Konrad Dybcio wrote:
>> On 10/13/25 1:04 PM, Kamal Wadhwa wrote:
>>> On Mon, Oct 06, 2025 at 04:28:59PM +0200, Konrad Dybcio wrote:
>>>> On 10/1/25 2:23 PM, Kamal Wadhwa wrote:
>>>>> Hi Krzysztof,
>>>>>
>>>>> On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>>>
>>>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>>>>>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>>>>>
>>>>>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>>>>>
>>>>>>> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
>>>>>>> subsystems and are not available to APPS. This can cause the
>>>>>>> RTC probe failure as the RTC IRQ registration will fail in
>>>>>>> probe.
>>>>>>>
>>>>>>> Fix this issue by adding `no-alarm` property in the RTC DT
>>>>>>> node. This will skip the RTC alarm irq registration and
>>>>>>> the RTC probe will return success.
>>>>>>
>>>>>>
>>>>>> This is ridiculous. You just added glymur CRD and you claim now that
>>>>>> it's broken and you need to fix it. So just fix that commit!
>>>>>
>>>>> I'm afraid, but this is an actual limitation we have for Glymur
>>>>> (compared to Kaanapali).
>>>>> The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
>>>>> Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
>>>>> IRQ permission for the RTC peripheral.
>>>>
>>>> This is interesting.. is that a physical limitation, or some sort of
>>>> a software security policy?
>>>
>>> This is mostly a limitation for all compute targets(like Glymur). On compute
>>> targets we need to support ACPI TAD feature[1] this feature uses the RTC alarm.
>>> In a nutshell, this feature implements 2 times - AC ( adaptor power) and
>>> DC (battery power) timers, and based on active power source(AC or DC?) at the
>>> time of timer expiry device will either go for a full bootup or stay in power
>>> down.
>>>
>>> This feature is implemented on a different subsystem (SoCCP subsystem), and
>>> since the SPMI `IRQ` permissions can only be assigned to only one subsystem,
>>> so we can't use the alarms on APPS. This is why we use no-alarms DT to register
>>> RTC device without alarm-irq support.
>>>
>>> [1] TAD specification - https://uefi.org/sites/default/files/resources/ACPI_5.pdf
>>> section 9.18
>>
>> Hm, is there maybe some sort of an interface to talk to the SoCCP
>> and set the RTC as we wish, from the OS?
>
> Yes, the developement is almost done and we have done some testing as well, but
> that kernel driver needs some more cleanup and testing before posting to
> upstream. This will be added in future.
Thank you. Like Dmitry mentioned, please leave a comment about this
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
2025-10-01 12:23 ` Kamal Wadhwa
2025-10-06 14:28 ` Konrad Dybcio
@ 2025-10-06 14:32 ` Krzysztof Kozlowski
1 sibling, 0 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-06 14:32 UTC (permalink / raw)
To: Kamal Wadhwa
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 01/10/2025 21:23, Kamal Wadhwa wrote:
> Hi Krzysztof,
>
> On Thu, Sep 25, 2025 at 1:41 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
>> <pankaj.patil@oss.qualcomm.com> wrote:
>>>
>>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>
>>> On Glymur boards, the RTC alarm interrupts are routed to SOCCP
>>> subsystems and are not available to APPS. This can cause the
>>> RTC probe failure as the RTC IRQ registration will fail in
>>> probe.
>>>
>>> Fix this issue by adding `no-alarm` property in the RTC DT
>>> node. This will skip the RTC alarm irq registration and
>>> the RTC probe will return success.
>>
>>
>> This is ridiculous. You just added glymur CRD and you claim now that
>> it's broken and you need to fix it. So just fix that commit!
>
> I'm afraid, but this is an actual limitation we have for Glymur
> (compared to Kaanapali).
> The RTC is part of the pmk8850.dtsi that is common between Kaanapali and
> Glymur. On Glymur (unlike Kaanapali) the APPS processor does *not* have the RTC
> IRQ permission for the RTC peripheral.
>
> So we need this extra change in Glymur explicitly as a workaround to
> make RTC register
> properly.
>
> But sure, we can squash this into the main DT patch, if you think this
> is not a limitation
> that needs to be highlighted in a separate patch.
>
>>
>> This is a gross misinterpretation of splitting patchset, some twisted
>> LWN stats work.
>
> Sorry for this. It was not intentional (definitely not for LWN stats),
> mainly this happened
> because this is how individual driver owners/teams internally added
> their patches. So
You upstream all this, so YOU should organize this work for upstream,
not just copy-paste what internal owners/teams did.
Upstream community does not care about owners/teams concept. You must
send logically consistent and organized in sane way patchset, which
means squashing all such stuff so in new code you will never use word
"fix" for something you just added.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (16 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 8:13 ` Krzysztof Kozlowski
2025-09-25 10:32 ` Konrad Dybcio
2025-09-25 6:32 ` [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5 Pankaj Patil
` (6 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Kamal Wadhwa
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add the pmic glink node with connectors.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index b04c0ed28468620673237fffb4013adacc7ef7ba..3f94bdf8b3ccfdff182005d67b8b3f84f956a430 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -79,6 +79,34 @@ key-volume-up {
wakeup-source;
};
};
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
};
&tlmm {
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node
2025-09-25 6:32 ` [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node Pankaj Patil
@ 2025-09-25 8:13 ` Krzysztof Kozlowski
2025-09-25 10:32 ` Konrad Dybcio
1 sibling, 0 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:13 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Kamal Wadhwa
On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
<pankaj.patil@oss.qualcomm.com> wrote:
>
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add the pmic glink node with connectors.
Please stop this. This is not a separate commit!
Same review as year ago, two years ago and three (probably) years ago.
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node
2025-09-25 6:32 ` [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node Pankaj Patil
2025-09-25 8:13 ` Krzysztof Kozlowski
@ 2025-09-25 10:32 ` Konrad Dybcio
2025-10-08 11:55 ` Pankaj Patil
1 sibling, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:32 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add the pmic glink node with connectors.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index b04c0ed28468620673237fffb4013adacc7ef7ba..3f94bdf8b3ccfdff182005d67b8b3f84f956a430 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -79,6 +79,34 @@ key-volume-up {
> wakeup-source;
> };
> };
> +
> + pmic-glink {
> + compatible = "qcom,sm8550-pmic-glink",
You *must* include a glymur compatible
> + "qcom,pmic-glink";
Are you sure this is still compatible with 8550 after this
series landed?
https://lore.kernel.org/linux-arm-msm/20250917-qcom_battmgr_update-v5-0-270ade9ffe13@oss.qualcomm.com/
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node
2025-09-25 10:32 ` Konrad Dybcio
@ 2025-10-08 11:55 ` Pankaj Patil
0 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-10-08 11:55 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Kamal Wadhwa
On 9/25/2025 4:02 PM, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>
>> Add the pmic glink node with connectors.
>>
>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> index b04c0ed28468620673237fffb4013adacc7ef7ba..3f94bdf8b3ccfdff182005d67b8b3f84f956a430 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
>> @@ -79,6 +79,34 @@ key-volume-up {
>> wakeup-source;
>> };
>> };
>> +
>> + pmic-glink {
>> + compatible = "qcom,sm8550-pmic-glink",
> You *must* include a glymur compatible
>
>> + "qcom,pmic-glink";
> Are you sure this is still compatible with 8550 after this
> series landed?
>
> https://lore.kernel.org/linux-arm-msm/20250917-qcom_battmgr_update-v5-0-270ade9ffe13@oss.qualcomm.com/
>
> Konrad
I'll check and add a glymur compatible in next revision
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (17 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 18/24] arm64: dts: qcom: glymur: Add PMIC glink node Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 8:15 ` Krzysztof Kozlowski
` (2 more replies)
2025-09-25 6:32 ` [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5 Pankaj Patil
` (5 subsequent siblings)
24 siblings, 3 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Prudhvi Yarlagadda, Qiang Yu
From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Describe PCIe5 controller and PHY. Also add required system resources like
regulators, clocks, interrupts and registers configuration for PCIe5.
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
1 file changed, 207 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -951,7 +951,7 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <0>;
+ <&pcie5_phy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -2511,6 +2511,212 @@ pcie_west_slv_noc: interconnect@1920000 {
#interconnect-cells = <2>;
};
+ pcie5: pci@1b40000 {
+ device_type = "pci";
+ compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
+ reg = <0x0 0x01b40000 0x0 0x3000>,
+ <0x7 0xa0000000 0x0 0xf20>,
+ <0x7 0xa0000f40 0x0 0xa8>,
+ <0x7 0xb0000000 0x0 0x4000>,
+ <0x7 0xa0100000 0x0 0x100000>,
+ <0x0 0x01b43000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0x7a000000 0 0x7a000000 0 0x4000000>;
+ bus-range = <0 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <5>;
+ num-lanes = <4>;
+ max-link-speed = <5>;
+
+ operating-points-v2 = <&pcie5_opp_table>;
+
+ msi-map = <0x0 &gic_its 0xd0000 0x10000>;
+
+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
+ <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_5_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr";
+
+ assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_5_BCR>,
+ <&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_5_GDSC>;
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+ eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+
+ status = "disabled";
+
+ pcie5_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 1 x4 and GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 2 x4 */
+ opp-20000000 {
+ opp-hz = /bits/ 64 <20000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <2000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 3 x4, GEN 4 x2 and GEN5 x1*/
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <3938000 1>;
+ };
+
+ /* GEN 4 x4 and GEN 5 x2 */
+ opp-64000000 {
+ opp-hz = /bits/ 64 <64000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <7876000 1>;
+ };
+
+ /* GEN 5 x4 */
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <15753000 1>;
+ };
+ };
+
+ pcie5port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ phys = <&pcie5_phy>;
+ };
+ };
+
+ pcie5_phy: phy@1b50000 {
+ compatible = "qcom,glymur-qmp-gen5x4-pcie-phy";
+ reg = <0x0 0x01b50000 0x0 0x10000>;
+
+ clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>,
+ <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
+ <&tcsrcc TCSR_PCIE_1_CLKREF_EN>,
+ <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_5_PIPE_CLK>,
+ <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ resets = <&gcc GCC_PCIE_5_PHY_BCR>,
+ <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie5_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-09-25 6:32 ` [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5 Pankaj Patil
@ 2025-09-25 8:15 ` Krzysztof Kozlowski
2025-09-25 11:32 ` Konrad Dybcio
2025-10-08 13:36 ` Abel Vesa
2 siblings, 0 replies; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:15 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Prudhvi Yarlagadda, Qiang Yu
On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
<pankaj.patil@oss.qualcomm.com> wrote:
>
> From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
>
> Describe PCIe5 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe5.
>
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 207 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -951,7 +951,7 @@ gcc: clock-controller@100000 {
> <0>,
> <0>,
> <0>,
> - <0>;
> + <&pcie5_phy>;
No, you just added this line.
Don't add wrong code just to fix it immediately. Qualcomm received
such comment multiple times from me already.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-09-25 6:32 ` [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5 Pankaj Patil
2025-09-25 8:15 ` Krzysztof Kozlowski
@ 2025-09-25 11:32 ` Konrad Dybcio
2025-10-10 7:02 ` Qiang Yu
2025-10-08 13:36 ` Abel Vesa
2 siblings, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 11:32 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Prudhvi Yarlagadda,
Qiang Yu
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
>
> Describe PCIe5 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe5.
>
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
[...]
> + pcie5: pci@1b40000 {
> + device_type = "pci";
> + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> + reg = <0x0 0x01b40000 0x0 0x3000>,
> + <0x7 0xa0000000 0x0 0xf20>,
> + <0x7 0xa0000f40 0x0 0xa8>,
> + <0x7 0xb0000000 0x0 0x4000>,
> + <0x7 0xa0100000 0x0 0x100000>,
> + <0x0 0x01b43000 0x0 0x1000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config",
> + "mhi";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x02000000 0 0x7a000000 0 0x7a000000 0 0x4000000>;
No I/O space? We can also add the (presumably prefetchable) 64-bit range
> + pcie5port0: pcie@0 {
pcie5_port0:
> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + phys = <&pcie5_phy>;
same comment as on the other patch
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-09-25 11:32 ` Konrad Dybcio
@ 2025-10-10 7:02 ` Qiang Yu
0 siblings, 0 replies; 125+ messages in thread
From: Qiang Yu @ 2025-10-10 7:02 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Prudhvi Yarlagadda
On Thu, Sep 25, 2025 at 01:32:04PM +0200, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
> > From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> >
> > Describe PCIe5 controller and PHY. Also add required system resources like
> > regulators, clocks, interrupts and registers configuration for PCIe5.
> >
> > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + pcie5: pci@1b40000 {
> > + device_type = "pci";
> > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> > + reg = <0x0 0x01b40000 0x0 0x3000>,
> > + <0x7 0xa0000000 0x0 0xf20>,
> > + <0x7 0xa0000f40 0x0 0xa8>,
> > + <0x7 0xb0000000 0x0 0x4000>,
> > + <0x7 0xa0100000 0x0 0x100000>,
> > + <0x0 0x01b43000 0x0 0x1000>;
> > + reg-names = "parf",
> > + "dbi",
> > + "elbi",
> > + "atu",
> > + "config",
> > + "mhi";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + ranges = <0x02000000 0 0x7a000000 0 0x7a000000 0 0x4000000>;
>
> No I/O space? We can also add the (presumably prefetchable) 64-bit range
Will add I/O space and prefetchable mem space since we don't know which
device user may insert.
>
>
> > + pcie5port0: pcie@0 {
>
> pcie5_port0:
>
> > + device_type = "pci";
> > + reg = <0x0 0x0 0x0 0x0 0x0>;
> > + bus-range = <0x01 0xff>;
> > +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + ranges;
> > + phys = <&pcie5_phy>;
>
> same comment as on the other patch
>
Will change the order as you commented for kaanapali patch.
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
- Qiang Yu
> Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-09-25 6:32 ` [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5 Pankaj Patil
2025-09-25 8:15 ` Krzysztof Kozlowski
2025-09-25 11:32 ` Konrad Dybcio
@ 2025-10-08 13:36 ` Abel Vesa
2025-10-10 7:08 ` Qiang Yu
2 siblings, 1 reply; 125+ messages in thread
From: Abel Vesa @ 2025-10-08 13:36 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Prudhvi Yarlagadda, Qiang Yu
On 25-09-25 12:02:27, Pankaj Patil wrote:
> From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
>
> Describe PCIe5 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe5.
>
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 207 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -951,7 +951,7 @@ gcc: clock-controller@100000 {
> <0>,
> <0>,
> <0>,
> - <0>;
> + <&pcie5_phy>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> @@ -2511,6 +2511,212 @@ pcie_west_slv_noc: interconnect@1920000 {
> #interconnect-cells = <2>;
> };
>
> + pcie5: pci@1b40000 {
> + device_type = "pci";
> + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
The first compatible is definitely "qcom,pcie-glymur".
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-10-08 13:36 ` Abel Vesa
@ 2025-10-10 7:08 ` Qiang Yu
2025-10-11 11:43 ` Abel Vesa
0 siblings, 1 reply; 125+ messages in thread
From: Qiang Yu @ 2025-10-10 7:08 UTC (permalink / raw)
To: Abel Vesa
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Prudhvi Yarlagadda
On Wed, Oct 08, 2025 at 04:36:59PM +0300, Abel Vesa wrote:
> On 25-09-25 12:02:27, Pankaj Patil wrote:
> > From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> >
> > Describe PCIe5 controller and PHY. Also add required system resources like
> > regulators, clocks, interrupts and registers configuration for PCIe5.
> >
> > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
> > 1 file changed, 207 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -951,7 +951,7 @@ gcc: clock-controller@100000 {
> > <0>,
> > <0>,
> > <0>,
> > - <0>;
> > + <&pcie5_phy>;
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > #power-domain-cells = <1>;
> > @@ -2511,6 +2511,212 @@ pcie_west_slv_noc: interconnect@1920000 {
> > #interconnect-cells = <2>;
> > };
> >
> > + pcie5: pci@1b40000 {
> > + device_type = "pci";
> > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
>
> The first compatible is definitely "qcom,pcie-glymur".
According to Documentation/devicetree/bindings/arm/qcom-soc.yaml
the preferred order is qcom,socname-ipblock.
- Qiang Yu
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-10-10 7:08 ` Qiang Yu
@ 2025-10-11 11:43 ` Abel Vesa
2025-10-11 15:57 ` Dmitry Baryshkov
0 siblings, 1 reply; 125+ messages in thread
From: Abel Vesa @ 2025-10-11 11:43 UTC (permalink / raw)
To: Qiang Yu
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Prudhvi Yarlagadda
On 25-10-10 00:08:31, Qiang Yu wrote:
> On Wed, Oct 08, 2025 at 04:36:59PM +0300, Abel Vesa wrote:
> > On 25-09-25 12:02:27, Pankaj Patil wrote:
> > > From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > >
> > > Describe PCIe5 controller and PHY. Also add required system resources like
> > > regulators, clocks, interrupts and registers configuration for PCIe5.
> > >
> > > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
> > > 1 file changed, 207 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > @@ -951,7 +951,7 @@ gcc: clock-controller@100000 {
> > > <0>,
> > > <0>,
> > > <0>,
> > > - <0>;
> > > + <&pcie5_phy>;
> > > #clock-cells = <1>;
> > > #reset-cells = <1>;
> > > #power-domain-cells = <1>;
> > > @@ -2511,6 +2511,212 @@ pcie_west_slv_noc: interconnect@1920000 {
> > > #interconnect-cells = <2>;
> > > };
> > >
> > > + pcie5: pci@1b40000 {
> > > + device_type = "pci";
> > > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> >
> > The first compatible is definitely "qcom,pcie-glymur".
>
> According to Documentation/devicetree/bindings/arm/qcom-soc.yaml
> the preferred order is qcom,socname-ipblock.
Fair enough.
Now I wonder what happened when we added the one for x1e80100.
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-10-11 11:43 ` Abel Vesa
@ 2025-10-11 15:57 ` Dmitry Baryshkov
2025-10-11 18:12 ` Abel Vesa
0 siblings, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-10-11 15:57 UTC (permalink / raw)
To: Abel Vesa
Cc: Qiang Yu, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, Prudhvi Yarlagadda
On Sat, Oct 11, 2025 at 02:43:14PM +0300, Abel Vesa wrote:
> On 25-10-10 00:08:31, Qiang Yu wrote:
> > On Wed, Oct 08, 2025 at 04:36:59PM +0300, Abel Vesa wrote:
> > > On 25-09-25 12:02:27, Pankaj Patil wrote:
> > > > From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > > >
> > > > Describe PCIe5 controller and PHY. Also add required system resources like
> > > > regulators, clocks, interrupts and registers configuration for PCIe5.
> > > >
> > > > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > > > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > > ---
> > > > arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
> > > > 1 file changed, 207 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> > > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > @@ -951,7 +951,7 @@ gcc: clock-controller@100000 {
> > > > <0>,
> > > > <0>,
> > > > <0>,
> > > > - <0>;
> > > > + <&pcie5_phy>;
> > > > #clock-cells = <1>;
> > > > #reset-cells = <1>;
> > > > #power-domain-cells = <1>;
> > > > @@ -2511,6 +2511,212 @@ pcie_west_slv_noc: interconnect@1920000 {
> > > > #interconnect-cells = <2>;
> > > > };
> > > >
> > > > + pcie5: pci@1b40000 {
> > > > + device_type = "pci";
> > > > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> > >
> > > The first compatible is definitely "qcom,pcie-glymur".
> >
> > According to Documentation/devicetree/bindings/arm/qcom-soc.yaml
> > the preferred order is qcom,socname-ipblock.
>
> Fair enough.
>
> Now I wonder what happened when we added the one for x1e80100.
Our PCIe hosts mostly follow the legacy approach and nobody wanted to
change it up to now.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5
2025-10-11 15:57 ` Dmitry Baryshkov
@ 2025-10-11 18:12 ` Abel Vesa
0 siblings, 0 replies; 125+ messages in thread
From: Abel Vesa @ 2025-10-11 18:12 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Qiang Yu, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, Prudhvi Yarlagadda
On 25-10-11 18:57:56, Dmitry Baryshkov wrote:
> On Sat, Oct 11, 2025 at 02:43:14PM +0300, Abel Vesa wrote:
> > On 25-10-10 00:08:31, Qiang Yu wrote:
> > > On Wed, Oct 08, 2025 at 04:36:59PM +0300, Abel Vesa wrote:
> > > > On 25-09-25 12:02:27, Pankaj Patil wrote:
> > > > > From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > > > >
> > > > > Describe PCIe5 controller and PHY. Also add required system resources like
> > > > > regulators, clocks, interrupts and registers configuration for PCIe5.
> > > > >
> > > > > Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
> > > > > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > > > > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > > > > ---
> > > > > arch/arm64/boot/dts/qcom/glymur.dtsi | 208 ++++++++++++++++++++++++++++++++++-
> > > > > 1 file changed, 207 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > > index e6e001485747785fd29c606773cba7793bbd2a5c..17a07d33b9396dba00e61a3b4260fa1a535600f2 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > > > @@ -951,7 +951,7 @@ gcc: clock-controller@100000 {
> > > > > <0>,
> > > > > <0>,
> > > > > <0>,
> > > > > - <0>;
> > > > > + <&pcie5_phy>;
> > > > > #clock-cells = <1>;
> > > > > #reset-cells = <1>;
> > > > > #power-domain-cells = <1>;
> > > > > @@ -2511,6 +2511,212 @@ pcie_west_slv_noc: interconnect@1920000 {
> > > > > #interconnect-cells = <2>;
> > > > > };
> > > > >
> > > > > + pcie5: pci@1b40000 {
> > > > > + device_type = "pci";
> > > > > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> > > >
> > > > The first compatible is definitely "qcom,pcie-glymur".
> > >
> > > According to Documentation/devicetree/bindings/arm/qcom-soc.yaml
> > > the preferred order is qcom,socname-ipblock.
> >
> > Fair enough.
> >
> > Now I wonder what happened when we added the one for x1e80100.
>
> Our PCIe hosts mostly follow the legacy approach and nobody wanted to
> change it up to now.
Yeah, makes sense. Thanks.
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (18 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5 Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 11:09 ` Konrad Dybcio
2025-10-09 9:53 ` Abel Vesa
2025-09-25 6:32 ` [PATCH 21/24] arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes Pankaj Patil
` (4 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil, Qiang Yu
From: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add perst, wake and clkreq sideband signals and required regulators in
PCIe5 controller and PHY device tree node.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 68 +++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 3f94bdf8b3ccfdff182005d67b8b3f84f956a430..03aacdb1dd7e2354fe31e63183519e53fa022829 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -107,6 +107,20 @@ port@1 {
};
};
};
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_NVME_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&nvme_reg_en>;
+ pinctrl-names = "default";
+ };
};
&tlmm {
@@ -461,3 +475,57 @@ vreg_l4h_e0_1p2: ldo4 {
&pmk8850_rtc {
no-alarm;
};
+
+&pmh0101_gpios {
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio14";
+ function = "normal";
+ bias-disable;
+ };
+};
+
+&tlmm {
+ pcie5_default: pcie5-default-state {
+ clkreq-n-pins {
+ pins = "gpio153";
+ function = "pcie5_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio152";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio154";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&pcie5 {
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-0 = <&pcie5_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie5_phy {
+ vdda-phy-supply = <&vreg_l2f_e0_0p82>;
+ vdda-pll-supply = <&vreg_l4h_e0_1p2>;
+
+ status = "okay";
+};
+
+&pcie5port0 {
+ perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5
2025-09-25 6:32 ` [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5 Pankaj Patil
@ 2025-09-25 11:09 ` Konrad Dybcio
2025-10-09 9:53 ` Abel Vesa
1 sibling, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 11:09 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Qiang Yu
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> Add perst, wake and clkreq sideband signals and required regulators in
> PCIe5 controller and PHY device tree node.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5
2025-09-25 6:32 ` [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5 Pankaj Patil
2025-09-25 11:09 ` Konrad Dybcio
@ 2025-10-09 9:53 ` Abel Vesa
2025-10-10 7:13 ` Qiang Yu
1 sibling, 1 reply; 125+ messages in thread
From: Abel Vesa @ 2025-10-09 9:53 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, Qiang Yu
On 25-09-25 12:02:28, Pankaj Patil wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> Add perst, wake and clkreq sideband signals and required regulators in
> PCIe5 controller and PHY device tree node.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 68 +++++++++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index 3f94bdf8b3ccfdff182005d67b8b3f84f956a430..03aacdb1dd7e2354fe31e63183519e53fa022829 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -107,6 +107,20 @@ port@1 {
> };
> };
> };
> +
> + vreg_nvme: regulator-nvme {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VREG_NVME_3P3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-0 = <&nvme_reg_en>;
> + pinctrl-names = "default";
> + };
> };
>
> &tlmm {
so tlmm already exists in here, but ...
> @@ -461,3 +475,57 @@ vreg_l4h_e0_1p2: ldo4 {
> &pmk8850_rtc {
> no-alarm;
> };
> +
> +&pmh0101_gpios {
> + nvme_reg_en: nvme-reg-en-state {
> + pins = "gpio14";
> + function = "normal";
> + bias-disable;
> + };
> +};
> +
> +&tlmm {
you add it here again.
> + pcie5_default: pcie5-default-state {
> + clkreq-n-pins {
> + pins = "gpio153";
> + function = "pcie5_clk_req_n";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5
2025-10-09 9:53 ` Abel Vesa
@ 2025-10-10 7:13 ` Qiang Yu
0 siblings, 0 replies; 125+ messages in thread
From: Qiang Yu @ 2025-10-10 7:13 UTC (permalink / raw)
To: Abel Vesa
Cc: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On Thu, Oct 09, 2025 at 12:53:24PM +0300, Abel Vesa wrote:
> On 25-09-25 12:02:28, Pankaj Patil wrote:
> > From: Qiang Yu <qiang.yu@oss.qualcomm.com>
> >
> > Add perst, wake and clkreq sideband signals and required regulators in
> > PCIe5 controller and PHY device tree node.
> >
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/glymur-crd.dts | 68 +++++++++++++++++++++++++++++++++
> > 1 file changed, 68 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> > index 3f94bdf8b3ccfdff182005d67b8b3f84f956a430..03aacdb1dd7e2354fe31e63183519e53fa022829 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> > @@ -107,6 +107,20 @@ port@1 {
> > };
> > };
> > };
> > +
> > + vreg_nvme: regulator-nvme {
> > + compatible = "regulator-fixed";
> > +
> > + regulator-name = "VREG_NVME_3P3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > +
> > + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > +
> > + pinctrl-0 = <&nvme_reg_en>;
> > + pinctrl-names = "default";
> > + };
> > };
> >
> > &tlmm {
>
> so tlmm already exists in here, but ...
>
> > @@ -461,3 +475,57 @@ vreg_l4h_e0_1p2: ldo4 {
> > &pmk8850_rtc {
> > no-alarm;
> > };
> > +
> > +&pmh0101_gpios {
> > + nvme_reg_en: nvme-reg-en-state {
> > + pins = "gpio14";
> > + function = "normal";
> > + bias-disable;
> > + };
> > +};
> > +
> > +&tlmm {
>
> you add it here again.
Will move this part to above tlmm node.
- Qiang Yu
>
> > + pcie5_default: pcie5-default-state {
> > + clkreq-n-pins {
> > + pins = "gpio153";
> > + function = "pcie5_clk_req_n";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 21/24] arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (19 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5 Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 11:15 ` Konrad Dybcio
2025-09-25 6:32 ` [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device Pankaj Patil
` (3 subsequent siblings)
24 siblings, 1 reply; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Manaf Meethalavalappu Pallikunhi
From: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Add tsens and thermal zones nodes for Glymur SoC.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 1998 ++++++++++++++++++++++++++++++++++
1 file changed, 1998 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 17a07d33b9396dba00e61a3b4260fa1a535600f2..986dc385200029071136068ab79ff8dd66d5284a 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2790,6 +2790,134 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ tsens0: thermal-sensor@c22c000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22c000 0 0x1000>, /* TM */
+ <0 0x0c222000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c22d000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22d000 0 0x1000>, /* TM */
+ <0 0x0c223000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <9>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens2: thermal-sensor@c22e000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22e000 0 0x1000>, /* TM */
+ <0 0x0c224000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c22f000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22f000 0 0x1000>, /* TM */
+ <0 0x0c225000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <8>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens4: thermal-sensor@c230000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c230000 0 0x1000>, /* TM */
+ <0 0x0c226000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens5: thermal-sensor@c231000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c231000 0 0x1000>, /* TM */
+ <0 0x0c227000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <8>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens6: thermal-sensor@c232000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c232000 0 0x1000>, /* TM */
+ <0 0x0c228000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens7: thermal-sensor@c233000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c233000 0 0x1000>, /* TM */
+ <0 0x0c229000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <15>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
aoss_qmp: power-management@c300000 {
compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>;
@@ -4611,4 +4739,1874 @@ timer {
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+
+ thermal_zones: thermal-zones {
+ aoss-0-thermal {
+ thermal-sensors = <&tsens0 0>;
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+ aoss-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-0-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-0-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-0-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-1-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-1-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-1-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-0-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-2-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-1-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-2-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-0-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-3-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-1-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-3-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-4-0-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-4-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-4-1-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-4-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-5-0-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ cpu-0-5-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-5-1-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-0-5-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-1-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-0-0-thermal {
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-0-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-0-1-thermal {
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-0-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-0-thermal {
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-0-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-1-thermal {
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-0-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-0-2-thermal {
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-0-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-0-thermal {
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ ddr-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-0-thermal {
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ video-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-1-thermal {
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ video-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-2-thermal {
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-0-thermal {
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-0-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-1-thermal {
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-0-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-0-thermal {
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-1-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-1-thermal {
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-1-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-2-0-thermal {
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-2-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-2-1-thermal {
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-2-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-3-0-thermal {
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-3-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-3-1-thermal {
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-3-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-4-0-thermal {
+ thermal-sensors = <&tsens2 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-4-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-4-1-thermal {
+ thermal-sensors = <&tsens2 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-4-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-5-0-thermal {
+ thermal-sensors = <&tsens2 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-5-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-5-1-thermal {
+ thermal-sensors = <&tsens2 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-1-5-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-3-thermal {
+ thermal-sensors = <&tsens3 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss-3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-1-0-thermal {
+ thermal-sensors = <&tsens3 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-1-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-1-1-thermal {
+ thermal-sensors = <&tsens3 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-1-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-0-thermal {
+ thermal-sensors = <&tsens3 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-1-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-1-thermal {
+ thermal-sensors = <&tsens3 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-1-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-2-thermal {
+ thermal-sensors = <&tsens3 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-1-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-3-thermal {
+ thermal-sensors = <&tsens3 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-1-3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-1-4-thermal {
+ thermal-sensors = <&tsens3 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-1-4-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-4-thermal {
+ thermal-sensors = <&tsens4 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss-4-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-0-0-thermal {
+ thermal-sensors = <&tsens4 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-0-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-0-1-thermal {
+ thermal-sensors = <&tsens4 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-0-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-1-0-thermal {
+ thermal-sensors = <&tsens4 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-1-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-1-1-thermal {
+ thermal-sensors = <&tsens4 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-1-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-2-0-thermal {
+ thermal-sensors = <&tsens4 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-2-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-2-1-thermal {
+ thermal-sensors = <&tsens4 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-2-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-3-0-thermal {
+ thermal-sensors = <&tsens4 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-3-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-3-1-thermal {
+ thermal-sensors = <&tsens4 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-3-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-4-0-thermal {
+ thermal-sensors = <&tsens4 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-4-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-4-1-thermal {
+ thermal-sensors = <&tsens4 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-4-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-5-0-thermal {
+ thermal-sensors = <&tsens4 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-5-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-2-5-1-thermal {
+ thermal-sensors = <&tsens4 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu-2-5-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-5-thermal {
+ thermal-sensors = <&tsens5 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss-5-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpullc-2-0-thermal {
+ thermal-sensors = <&tsens5 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-2-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuillc-2-1-thermal {
+ thermal-sensors = <&tsens5 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpullc-2-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-2-0-thermal {
+ thermal-sensors = <&tsens5 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-2-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-2-1-thermal {
+ thermal-sensors = <&tsens5 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-2-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-2-2-thermal {
+ thermal-sensors = <&tsens5 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-2-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-2-3-thermal {
+ thermal-sensors = <&tsens5 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-2-3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ qmx-2-4-thermal {
+ thermal-sensors = <&tsens5 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ qmx-2-4-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-6-thermal {
+ thermal-sensors = <&tsens6 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss-6-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-0-thermal {
+ thermal-sensors = <&tsens6 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphvx-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-1-thermal {
+ thermal-sensors = <&tsens6 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphvx-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-2-thermal {
+ thermal-sensors = <&tsens6 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphvx-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx-3-thermal {
+ thermal-sensors = <&tsens6 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphvx-3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-0-thermal {
+ thermal-sensors = <&tsens6 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphmx-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-1-thermal {
+ thermal-sensors = <&tsens6 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphmx-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-2-thermal {
+ thermal-sensors = <&tsens6 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphmx-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx-3-thermal {
+ thermal-sensors = <&tsens6 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsphmx-3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-0-thermal {
+ thermal-sensors = <&tsens6 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ camera-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-1-thermal {
+ thermal-sensors = <&tsens6 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ camera-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-1-thermal {
+ thermal-sensors = <&tsens6 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ ddr-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-2-thermal {
+ thermal-sensors = <&tsens6 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ ddr-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-7-thermal {
+ thermal-sensors = <&tsens7 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss-7-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-0-thermal {
+ thermal-sensors = <&tsens7 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-1-thermal {
+ thermal-sensors = <&tsens7 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-0-2-thermal {
+ thermal-sensors = <&tsens7 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-0-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-0-thermal {
+ thermal-sensors = <&tsens7 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-1-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-1-thermal {
+ thermal-sensors = <&tsens7 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-1-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-1-2-thermal {
+ thermal-sensors = <&tsens7 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-1-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-0-thermal {
+ thermal-sensors = <&tsens7 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-2-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-1-thermal {
+ thermal-sensors = <&tsens7 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-2-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-2-2-thermal {
+ thermal-sensors = <&tsens7 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-2-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-3-0-thermal {
+ thermal-sensors = <&tsens7 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-3-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-3-1-thermal {
+ thermal-sensors = <&tsens7 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-3-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-3-2-thermal {
+ thermal-sensors = <&tsens7 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpu-3-2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ thermal-sensors = <&tsens7 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ thermal-sensors = <&tsens7 14>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 21/24] arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes
2025-09-25 6:32 ` [PATCH 21/24] arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes Pankaj Patil
@ 2025-09-25 11:15 ` Konrad Dybcio
0 siblings, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 11:15 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Manaf Meethalavalappu Pallikunhi
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>
> Add tsens and thermal zones nodes for Glymur SoC.
>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 1998 ++++++++++++++++++++++++++++++++++
> 1 file changed, 1998 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 17a07d33b9396dba00e61a3b4260fa1a535600f2..986dc385200029071136068ab79ff8dd66d5284a 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2790,6 +2790,134 @@ pdc: interrupt-controller@b220000 {
> interrupt-controller;
> };
>
> + tsens0: thermal-sensor@c22c000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c22c000 0 0x1000>, /* TM */
> + <0 0x0c222000 0 0x1000>; /* SROT */
These comments are not useful
I noticed that some patches use reg = <0x0, while others use reg = <0
please unify them for the former
> +
> + interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
pdc 26
> + <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <13>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens1: thermal-sensor@c22d000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c22d000 0 0x1000>, /* TM */
> + <0 0x0c223000 0 0x1000>; /* SROT */
> +
> + interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
pdc 27
> + <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <9>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens2: thermal-sensor@c22e000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c22e000 0 0x1000>, /* TM */
> + <0 0x0c224000 0 0x1000>; /* SROT */
> +
> + interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
pdc 28
> + <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <13>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens3: thermal-sensor@c22f000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c22f000 0 0x1000>, /* TM */
> + <0 0x0c225000 0 0x1000>; /* SROT */
> +
> + interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
pdc 29
> + <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <8>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens4: thermal-sensor@c230000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c230000 0 0x1000>, /* TM */
> + <0 0x0c226000 0 0x1000>; /* SROT */
> +
> + interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
pdc 46
> + <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <13>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens5: thermal-sensor@c231000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c231000 0 0x1000>, /* TM */
> + <0 0x0c227000 0 0x1000>; /* SROT */
> +
> + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>,
pdc 108
> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <8>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens6: thermal-sensor@c232000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c232000 0 0x1000>, /* TM */
> + <0 0x0c228000 0 0x1000>; /* SROT */
> +
> + interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
pdc 109
> + <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <13>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens7: thermal-sensor@c233000 {
> + compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
> + reg = <0 0x0c233000 0 0x1000>, /* TM */
> + <0 0x0c229000 0 0x1000>; /* SROT */
> +
> + interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>,
pdc 110
> + <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "uplow",
> + "critical";
> +
> + #qcom,sensors = <15>;
> +
> + #thermal-sensor-cells = <1>;
> + };
> +
> aoss_qmp: power-management@c300000 {
> compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp";
> reg = <0 0x0c300000 0 0x400>;
> @@ -4611,4 +4739,1874 @@ timer {
> <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> };
> +
> + thermal_zones: thermal-zones {
> + aoss-0-thermal {
> + thermal-sensors = <&tsens0 0>;
You need one more \t here
> + trips {
> + trip-point0 {
> + temperature = <90000>;
> + hysteresis = <5000>;
> + type = "hot";
> + };
> + aoss-0-critical {
Please keep a \n between subnodes and between the last property and
following subnodes
> + temperature = <110000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> + };
> +
> + cpu-0-0-0-thermal {
> + thermal-sensors = <&tsens0 1>;
> +
> + trips {
> + trip-point0 {
> + temperature = <90000>;
> + hysteresis = <5000>;
> + type = "passive";
> + };
> +
> + trip-point1 {
> + temperature = <95000>;
> + hysteresis = <5000>;
> + type = "passive";
> + };
See:
06eadce93697 ("arm64: dts: qcom: x1e80100: Drop unused passive thermal trip points for CPU")
It also only makes sense to keep "hot" trips for devices where we
can actually apply some cooling (e.g. the GPU)
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (20 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 21/24] arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 8:18 ` Krzysztof Kozlowski
2025-09-25 10:33 ` Konrad Dybcio
2025-09-25 6:32 ` [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support Pankaj Patil
` (2 subsequent siblings)
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil, Taniya Das
From: Taniya Das <taniya.das@oss.qualcomm.com>
Support the display clock controller for GLYMUR SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 986dc385200029071136068ab79ff8dd66d5284a..8a563d55bdd4902222039946dd75eaf4d3a4895b 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <dt-bindings/clock/qcom,glymur-dispcc.h>
#include <dt-bindings/clock/qcom,glymur-gcc.h>
#include <dt-bindings/clock/qcom,glymur-tcsr.h>
#include <dt-bindings/clock/qcom,rpmh.h>
@@ -13,6 +14,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
@@ -2775,6 +2777,34 @@ lpass_ag_noc: interconnect@7e40000 {
#interconnect-cells = <2>;
};
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,glymur-dispcc";
+ reg = <0 0x0af00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>, /* dp0 */
+ <0>,
+ <0>, /* dp1 */
+ <0>,
+ <0>, /* dp2 */
+ <0>,
+ <0>, /* dp3 */
+ <0>,
+ <0>, /* dsi0 */
+ <0>,
+ <0>, /* dsi1 */
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,glymur-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device
2025-09-25 6:32 ` [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device Pankaj Patil
@ 2025-09-25 8:18 ` Krzysztof Kozlowski
2025-09-29 3:57 ` Taniya Das
2025-09-25 10:33 ` Konrad Dybcio
1 sibling, 1 reply; 125+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-25 8:18 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, Taniya Das
On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
<pankaj.patil@oss.qualcomm.com> wrote:
>
> From: Taniya Das <taniya.das@oss.qualcomm.com>
>
> Support the display clock controller for GLYMUR SoC.
One clock controller is not a separate commit.
Stop inflating patch count, you just makes it difficult for us to see
complete picture.
Is this somehow for LWN stats? That's why one node per patch?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device
2025-09-25 8:18 ` Krzysztof Kozlowski
@ 2025-09-29 3:57 ` Taniya Das
0 siblings, 0 replies; 125+ messages in thread
From: Taniya Das @ 2025-09-29 3:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 1:48 PM, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil
> <pankaj.patil@oss.qualcomm.com> wrote:
>>
>> From: Taniya Das <taniya.das@oss.qualcomm.com>
>>
>> Support the display clock controller for GLYMUR SoC.
>
> One clock controller is not a separate commit.
>
> Stop inflating patch count, you just makes it difficult for us to see
> complete picture.
>
Sorry about that Krzysztof. As the display clock controller was enabled
later point of time probably it was kept as a separate patch and not
merged.
> Is this somehow for LWN stats? That's why one node per patch?
>
That is definitely not the intention. As it was enabled later, it was
left as a separate patch.
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 125+ messages in thread
* Re: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device
2025-09-25 6:32 ` [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device Pankaj Patil
2025-09-25 8:18 ` Krzysztof Kozlowski
@ 2025-09-25 10:33 ` Konrad Dybcio
2025-09-29 3:54 ` Taniya Das
1 sibling, 1 reply; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:33 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Taniya Das
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Taniya Das <taniya.das@oss.qualcomm.com>
>
> Support the display clock controller for GLYMUR SoC.
>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
[...]
> + dispcc: clock-controller@af00000 {
> + compatible = "qcom,glymur-dispcc";
> + reg = <0 0x0af00000 0 0x20000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>,
> + <0>, /* dp0 */
> + <0>,
> + <0>, /* dp1 */
> + <0>,
> + <0>, /* dp2 */
> + <0>,
> + <0>, /* dp3 */
> + <0>,
> + <0>, /* dsi0 */
> + <0>,
> + <0>, /* dsi1 */
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> + required-opps = <&rpmhpd_opp_turbo>;
Really odd!
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device
2025-09-25 10:33 ` Konrad Dybcio
@ 2025-09-29 3:54 ` Taniya Das
2025-10-09 5:12 ` Taniya Das
0 siblings, 1 reply; 125+ messages in thread
From: Taniya Das @ 2025-09-29 3:54 UTC (permalink / raw)
To: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 4:03 PM, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>> From: Taniya Das <taniya.das@oss.qualcomm.com>
>>
>> Support the display clock controller for GLYMUR SoC.
>>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + dispcc: clock-controller@af00000 {
>> + compatible = "qcom,glymur-dispcc";
>> + reg = <0 0x0af00000 0 0x20000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&sleep_clk>,
>> + <0>, /* dp0 */
>> + <0>,
>> + <0>, /* dp1 */
>> + <0>,
>> + <0>, /* dp2 */
>> + <0>,
>> + <0>, /* dp3 */
>> + <0>,
>> + <0>, /* dsi0 */
>> + <0>,
>> + <0>, /* dsi1 */
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
>> + required-opps = <&rpmhpd_opp_turbo>;
The SVS level didn't work when Abel tried out. I will check with Abel again.
>
> Really odd!
>
> Konrad
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device
2025-09-29 3:54 ` Taniya Das
@ 2025-10-09 5:12 ` Taniya Das
2025-10-09 8:30 ` Konrad Dybcio
0 siblings, 1 reply; 125+ messages in thread
From: Taniya Das @ 2025-10-09 5:12 UTC (permalink / raw)
To: Konrad Dybcio, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/29/2025 9:24 AM, Taniya Das wrote:
>
>
> On 9/25/2025 4:03 PM, Konrad Dybcio wrote:
>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>> From: Taniya Das <taniya.das@oss.qualcomm.com>
>>>
>>> Support the display clock controller for GLYMUR SoC.
>>>
>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + dispcc: clock-controller@af00000 {
>>> + compatible = "qcom,glymur-dispcc";
>>> + reg = <0 0x0af00000 0 0x20000>;
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> + <&sleep_clk>,
>>> + <0>, /* dp0 */
>>> + <0>,
>>> + <0>, /* dp1 */
>>> + <0>,
>>> + <0>, /* dp2 */
>>> + <0>,
>>> + <0>, /* dp3 */
>>> + <0>,
>>> + <0>, /* dsi0 */
>>> + <0>,
>>> + <0>, /* dsi1 */
>>> + <0>,
>>> + <0>,
>>> + <0>,
>>> + <0>,
>>> + <0>;
>>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
>>> + required-opps = <&rpmhpd_opp_turbo>;
>
> The SVS level didn't work when Abel tried out. I will check with Abel again.
>
Abel offline confirmed LOW SVS level worked for him and I will update
the level to use "rpmhpd_opp_low_svs".
>>
>> Really odd!
>>
>> Konrad
>
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device
2025-10-09 5:12 ` Taniya Das
@ 2025-10-09 8:30 ` Konrad Dybcio
0 siblings, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-10-09 8:30 UTC (permalink / raw)
To: Taniya Das, Pankaj Patil, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/9/25 7:12 AM, Taniya Das wrote:
>
>
> On 9/29/2025 9:24 AM, Taniya Das wrote:
>>
>>
>> On 9/25/2025 4:03 PM, Konrad Dybcio wrote:
>>> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>>>> From: Taniya Das <taniya.das@oss.qualcomm.com>
>>>>
>>>> Support the display clock controller for GLYMUR SoC.
>>>>
>>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>>> ---
>>>
>>> [...]
>>>
>>>> + dispcc: clock-controller@af00000 {
>>>> + compatible = "qcom,glymur-dispcc";
>>>> + reg = <0 0x0af00000 0 0x20000>;
>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>> + <&sleep_clk>,
>>>> + <0>, /* dp0 */
>>>> + <0>,
>>>> + <0>, /* dp1 */
>>>> + <0>,
>>>> + <0>, /* dp2 */
>>>> + <0>,
>>>> + <0>, /* dp3 */
>>>> + <0>,
>>>> + <0>, /* dsi0 */
>>>> + <0>,
>>>> + <0>, /* dsi1 */
>>>> + <0>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>;
>>>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
>>>> + required-opps = <&rpmhpd_opp_turbo>;
>>
>> The SVS level didn't work when Abel tried out. I will check with Abel again.
>>
>
> Abel offline confirmed LOW SVS level worked for him and I will update
> the level to use "rpmhpd_opp_low_svs".
Thanks!
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (21 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 11:06 ` Konrad Dybcio
2025-09-25 13:19 ` Abel Vesa
2025-09-25 6:32 ` [PATCH 24/24] arm64: dts: qcom: glymur: Add remoteprocs Pankaj Patil
2025-09-25 17:30 ` [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Dmitry Baryshkov
24 siblings, 2 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Wesley Cheng
From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
The Glymur USB system contains 3 USB type C ports, and 1 USB multiport
controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 5
M31 eUSB2 PHYs. The controllers are SNPS DWC3 based, and will use the
flattened DWC3 QCOM design.
Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 243 ++++++++++++++
arch/arm64/boot/dts/qcom/glymur.dtsi | 569 ++++++++++++++++++++++++++++++++
2 files changed, 812 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 03aacdb1dd7e2354fe31e63183519e53fa022829..100519aa5a7cd905285d3aa41ebe5f63ae00aeef 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -99,10 +99,74 @@ ports {
port@0 {
reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in1: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
};
port@1 {
reg = <1>;
+
+ pmic_glink_ss_in1: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ connector@2 {
+ compatible = "usb-c-connector";
+ reg = <2>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in2: endpoint {
+ remote-endpoint = <&usb_2_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in2: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+ };
};
};
};
@@ -529,3 +593,182 @@ &pcie5port0 {
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
+
+&i2c5 {
+ status = "ok";
+
+ clock-frequency = <400000>;
+
+ ptn3222_0: redriver@43 {
+ compatible = "nxp,ptn3222";
+ reg = <0x43>;
+
+ reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
+
+ vdd3v3-supply = <&vreg_l8b_e0_1p50>;
+ vdd1v8-supply = <&vreg_l15b_e0_1p8>;
+
+ #phy-cells = <0>;
+ };
+
+ ptn3222_1: redriver@4f {
+ compatible = "nxp,ptn3222";
+ reg = <0x4f>;
+
+ reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
+
+ vdd3v3-supply = <&vreg_l8b_e0_1p50>;
+ vdd1v8-supply = <&vreg_l15b_e0_1p8>;
+
+ #phy-cells = <0>;
+ };
+};
+
+&smb2370_j_e2_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_e0_1p8>;
+ vdd3-supply = <&vreg_l7b_e0_2p79>;
+};
+
+&smb2370_k_e2_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_e0_1p8>;
+ vdd3-supply = <&vreg_l7b_e0_2p79>;
+};
+
+&smb2370_l_e2_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_e0_1p8>;
+ vdd3-supply = <&vreg_l7b_e0_2p79>;
+};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l3f_e0_0p72>;
+ vdda12-supply = <&vreg_l4h_e0_1p2>;
+
+ phys = <&smb2370_j_e2_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ vdda-phy-supply = <&vreg_l4h_e0_1p2>;
+ vdda-pll-supply = <&vreg_l3f_e0_0p72>;
+ refgen-supply = <&vreg_l2f_e0_0p82>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_ss0 {
+ dr_mode = "otg";
+ usb-role-switch;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in1>;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in1>;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l3f_e0_0p72>;
+ vdda12-supply = <&vreg_l4h_e0_1p2>;
+
+ phys = <&smb2370_k_e2_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ vdda-phy-supply = <&vreg_l4h_e0_1p2>;
+ vdda-pll-supply = <&vreg_l1h_e0_0p89>;
+ refgen-supply = <&vreg_l2f_e0_0p82>;
+
+ status = "okay";
+};
+
+&usb1_ss1 {
+ dr_mode = "otg";
+ usb-role-switch;
+
+ status = "okay";
+};
+
+&usb_1_ss2_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in2>;
+};
+
+&usb_2_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in2>;
+};
+
+&usb_1_ss2_hsphy {
+ vdd-supply = <&vreg_l4c_e1_0p72>;
+ vdda12-supply = <&vreg_l4f_e1_1p08>;
+
+ phys = <&smb2370_l_e2_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l4f_e1_1p08>;
+ vdda-pll-supply = <&vreg_l4c_e1_0p72>;
+ refgen-supply = <&vreg_l1c_e1_0p82>;
+
+ status = "okay";
+};
+
+&usb1_ss2 {
+ dr_mode = "otg";
+ usb-role-switch;
+
+ status = "okay";
+};
+
+&usb_mp_hsphy0 {
+ vdd-supply = <&vreg_l2h_e0_0p72>;
+ vdda12-supply = <&vreg_l4h_e0_1p2>;
+
+ phys = <&ptn3222_0>;
+
+ status = "okay";
+};
+
+&usb_mp_hsphy1 {
+ vdd-supply = <&vreg_l2h_e0_0p72>;
+ vdda12-supply = <&vreg_l4h_e0_1p2>;
+
+ phys = <&ptn3222_1>;
+
+ status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+ vdda-phy-supply = <&vreg_l4h_e0_1p2>;
+ vdda-pll-supply = <&vreg_l2h_e0_0p72>;
+ refgen-supply = <&vreg_l4f_e1_1p08>;
+
+ status = "okay";
+};
+
+&usb_mp_qmpphy1 {
+ vdda-phy-supply = <&vreg_l4h_e0_1p2>;
+ vdda-pll-supply = <&vreg_l2h_e0_0p72>;
+ refgen-supply = <&vreg_l4f_e1_1p08>;
+
+ status = "okay";
+};
+
+&usb_mp {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 8a563d55bdd4902222039946dd75eaf4d3a4895b..c48d3a70820e551822c5322761528159da127ca6 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2417,6 +2417,231 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ usb_mp_hsphy0: phy@fa1000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fa1000 0 0x29c>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsrcc TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_mp_hsphy1: phy@fa2000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fa2000 0 0x29c>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsrcc TCSR_USB2_2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_mp_qmpphy0: phy@fa3000 {
+ compatible = "qcom,glymur-qmp-usb3-uni-phy";
+ reg = <0 0x00fa3000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_0_CLKREF_EN>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux",
+ "clkref",
+ "ref",
+ "com_aux",
+ "pipe";
+
+ power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ clock-output-names = "usb3_uni_phy_0_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_mp_qmpphy1: phy@fa5000 {
+ compatible = "qcom,glymur-qmp-usb3-uni-phy";
+ reg = <0 0x00fa5000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_1_CLKREF_EN>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
+ clock-names = "aux",
+ "clkref",
+ "ref",
+ "com_aux",
+ "pipe";
+
+ power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ clock-output-names = "usb3_uni_phy_1_pipe_clk_src";
+
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss0_hsphy: phy@fd3000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fd3000 0 0x29c>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss0_qmpphy: phy@fd5000 {
+ compatible = "qcom,glymur-qmp-usb3-dp-phy";
+ reg = <0 0x00fd5000 0 0x8000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+
+ reset-names = "phy",
+ "common";
+
+ power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_dp_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_dp_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1_ss1_hsphy: phy@fdd000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fdd000 0 0x29c>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss1_qmpphy: phy@fde000 {
+ compatible = "qcom,glymur-qmp-usb3-dp-phy";
+ reg = <0 0x00fde000 0 0x8000>;
+
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+ <&tcsrcc TCSR_USB4_1_CLKREF_EN>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe",
+ "clkref";
+
+ power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb1_ss1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss1_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,glymur-cnoc-main";
reg = <0x0 0x01500000 0x0 0x17080>;
@@ -2777,6 +3002,350 @@ lpass_ag_noc: interconnect@7e40000 {
#interconnect-cells = <2>;
};
+ usb_1_ss2_hsphy: phy@88e0000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x088e0000 0 0x29c>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsrcc TCSR_USB2_4_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss2_qmpphy: phy@88e1000 {
+ compatible = "qcom,glymur-qmp-usb3-dp-phy";
+ reg = <0 0x088e1000 0 0x8000>;
+
+ clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>,
+ <&tcsrcc TCSR_USB4_2_CLKREF_EN>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe",
+ "clkref";
+
+ power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
+ <&gcc GCC_USB3PHY_PHY_TERT_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss2_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss2_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb1_ss2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss2_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1_ss0: usb@a600000 {
+ compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a600000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 90 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ iommus = <&apps_smmu 0x1420 0x0>;
+ phys = <&usb_1_ss0_hsphy>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ dr_mode = "peripheral";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
+ usb1_ss1: usb@a800000 {
+ compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a800000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 88 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 87 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 76 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ resets = <&gcc GCC_USB30_SEC_BCR>;
+ power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+
+ iommus = <&apps_smmu 0x1460 0x0>;
+
+ phys = <&usb_1_ss1_hsphy>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
+ usb1_ss2: usb@a000000 {
+ compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a000000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_SLEEP_CLK>,
+ <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 89 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 81 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 75 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ resets = <&gcc GCC_USB30_TERT_BCR>;
+ power-domains = <&gcc GCC_USB30_TERT_GDSC>;
+
+ iommus = <&apps_smmu 0x420 0x0>;
+
+ phys = <&usb_1_ss2_hsphy>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_2_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_2_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
+ usb_mp: usb@a400000 {
+ compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3";
+ reg = <0 0x0a400000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_SLEEP_CLK>,
+ <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 12 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 11 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 13 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 78 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event_1",
+ "pwr_event_2",
+ "hs_phy_1",
+ "hs_phy_2",
+ "dp_hs_phy_1",
+ "dm_hs_phy_1",
+ "dp_hs_phy_2",
+ "dm_hs_phy_2",
+ "ss_phy_1",
+ "ss_phy_2";
+
+ resets = <&gcc GCC_USB30_MP_BCR>;
+ power-domains = <&gcc GCC_USB30_MP_GDSC>;
+
+ iommus = <&apps_smmu 0xda0 0x0>;
+
+ phys = <&usb_mp_hsphy0>,
+ <&usb_mp_qmpphy0>,
+ <&usb_mp_hsphy1>,
+ <&usb_mp_qmpphy1>;
+ phy-names = "usb2-0",
+ "usb3-0",
+ "usb2-1",
+ "usb3-1";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ dr_mode = "host";
+
+ status = "disabled";
+
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,glymur-dispcc";
reg = <0 0x0af00000 0 0x20000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support
2025-09-25 6:32 ` [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support Pankaj Patil
@ 2025-09-25 11:06 ` Konrad Dybcio
2025-09-25 13:19 ` Abel Vesa
1 sibling, 0 replies; 125+ messages in thread
From: Konrad Dybcio @ 2025-09-25 11:06 UTC (permalink / raw)
To: Pankaj Patil, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Wesley Cheng
On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>
> The Glymur USB system contains 3 USB type C ports, and 1 USB multiport
> controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 5
> M31 eUSB2 PHYs. The controllers are SNPS DWC3 based, and will use the
> flattened DWC3 QCOM design.
>
> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 243 ++++++++++++++
> arch/arm64/boot/dts/qcom/glymur.dtsi | 569 ++++++++++++++++++++++++++++++++
Please split this into two commits
[...]
> +&i2c5 {
> + status = "ok";
"okay" is preferred:
$ rg '"ok"' arch | wc -l
6
$ rg '"okay"' arch | wc -l
33019
on a random recent next tree
'status' is also expected to come as the last property (but still before
subnodes)
[...]
> +&usb_1_ss0 {
> + dr_mode = "otg";
> + usb-role-switch;
usb-role-switch should be in the SoC DT, and I think "otg" is the
default dr_mode
[...]
> + usb_1_ss0: usb@a600000 {
the nodes should be sorted by unit address
Konrad
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support
2025-09-25 6:32 ` [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support Pankaj Patil
2025-09-25 11:06 ` Konrad Dybcio
@ 2025-09-25 13:19 ` Abel Vesa
1 sibling, 0 replies; 125+ messages in thread
From: Abel Vesa @ 2025-09-25 13:19 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Wesley Cheng
On 25-09-25 12:02:31, Pankaj Patil wrote:
> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>
> The Glymur USB system contains 3 USB type C ports, and 1 USB multiport
> controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 5
> M31 eUSB2 PHYs. The controllers are SNPS DWC3 based, and will use the
> flattened DWC3 QCOM design.
>
> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 243 ++++++++++++++
> arch/arm64/boot/dts/qcom/glymur.dtsi | 569 ++++++++++++++++++++++++++++++++
> 2 files changed, 812 insertions(+)
>
[...]
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 8a563d55bdd4902222039946dd75eaf4d3a4895b..c48d3a70820e551822c5322761528159da127ca6 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2417,6 +2417,231 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> };
> };
>
Also, as part of this patch, you need to attach the pipe clocks of the
PHY to the GCC.
^ permalink raw reply [flat|nested] 125+ messages in thread
* [PATCH 24/24] arm64: dts: qcom: glymur: Add remoteprocs
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (22 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support Pankaj Patil
@ 2025-09-25 6:32 ` Pankaj Patil
2025-09-25 17:30 ` [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Dmitry Baryshkov
24 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-09-25 6:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pankaj Patil,
Sibi Sankar
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Add remoteproc PAS loader for ADSP, CDSP and SoCCP with its SMP2P nodes.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 21 +++
arch/arm64/boot/dts/qcom/glymur.dtsi | 234 ++++++++++++++++++++++++++++++++
2 files changed, 255 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 100519aa5a7cd905285d3aa41ebe5f63ae00aeef..17c8f1a4f4061303982a210b7690783c96ef80b2 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -548,6 +548,27 @@ nvme_reg_en: nvme-reg-en-state {
};
};
+&remoteproc_adsp {
+ firmware-name = "qcom/glymur/adsp.mbn",
+ "qcom/glymur/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/glymur/cdsp.mbn",
+ "qcom/glymur/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_soccp {
+ firmware-name = "qcom/glymur/soccp.mbn",
+ "qcom/glymur/soccp_dtb.mbn";
+
+ status = "okay";
+};
+
&tlmm {
pcie5_default: pcie5-default-state {
clkreq-n-pins {
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index c48d3a70820e551822c5322761528159da127ca6..a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -782,6 +782,82 @@ smem_mem: smem-region@ffe00000 {
};
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc GLYMUR_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc GLYMUR_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <443>, <429>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc GLYMUR_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc GLYMUR_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <94>, <432>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-soccp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc GLYMUR_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc GLYMUR_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <617>, <616>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <19>;
+
+ soccp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ soccp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
clk_virt: interconnect-0 {
compatible = "qcom,glymur-clk-virt";
#interconnect-cells = <2>;
@@ -2417,6 +2493,59 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ remoteproc_soccp: remoteproc-soccp@d00000 {
+ compatible = "qcom,glymur-soccp-pas", "qcom,kaanapali-soccp-pas";
+ reg = <0x0 0x00d00000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>,
+ <&soccp_smp2p_in 10 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "pong",
+ "wake-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&soccp_mem>,
+ <&soccpdtb_mem>;
+
+ qcom,smem-states = <&soccp_smp2p_out 0>,
+ <&soccp_smp2p_out 10>,
+ <&soccp_smp2p_out 9>,
+ <&soccp_smp2p_out 8>;
+ qcom,smem-state-names = "stop",
+ "wakeup",
+ "sleep",
+ "ping";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc GLYMUR_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc GLYMUR_MPROC_SOCCP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ qcom,remote-pid = <19>;
+ label = "soccp";
+
+ };
+ };
+
usb_mp_hsphy0: phy@fa1000 {
compatible = "qcom,glymur-m31-eusb2-phy",
"qcom,sm8750-m31-eusb2-phy";
@@ -2944,6 +3073,57 @@ pcie5_phy: phy@1b50000 {
status = "disabled";
};
+ remoteproc_adsp: remoteproc@6800000 {
+ compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas";
+ reg = <0x0 0x06800000 0x0 0x10000>;
+
+ iommus = <&apps_smmu 0x1000 0x0>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc GLYMUR_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc GLYMUR_MPROC_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ };
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
@@ -5311,6 +5491,60 @@ nsp_noc: interconnect@320c0000 {
#interconnect-cells = <2>;
};
+ remoteproc_cdsp: remoteproc@32300000 {
+ compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas";
+ reg = <0x0 0x32300000 0x0 0x10000>;
+
+ iommus = <&apps_smmu 0x2000 0x400>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_NSP>;
+ power-domain-names = "cx",
+ "mxc",
+ "nsp";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&cdsp_mem>,
+ <&q6_cdsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc GLYMUR_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc GLYMUR_MPROC_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "cdsp";
+ qcom,remote-pid = <5>;
+ };
+ };
+
sram: sram@81e08000 {
compatible = "mmio-sram";
reg = <0x0 0x81e08600 0x0 0x300>;
--
2.34.1
^ permalink raw reply related [flat|nested] 125+ messages in thread* Re: [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts
2025-09-25 6:32 [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
` (23 preceding siblings ...)
2025-09-25 6:32 ` [PATCH 24/24] arm64: dts: qcom: glymur: Add remoteprocs Pankaj Patil
@ 2025-09-25 17:30 ` Dmitry Baryshkov
2025-10-08 12:18 ` Pankaj Patil
24 siblings, 1 reply; 125+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 17:30 UTC (permalink / raw)
To: Pankaj Patil
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Jyothi Kumar Seerapu, Maulik Shah, Sibi Sankar, Taniya Das,
Taniya Das, Kamal Wadhwa, Prudhvi Yarlagadda, Qiang Yu,
Manaf Meethalavalappu Pallikunhi, Wesley Cheng
On Thu, Sep 25, 2025 at 12:02:08PM +0530, Pankaj Patil wrote:
> Introduce dt-bindings and initial device tree support for Glymur,
> Qualcomm's next-generation compute SoC and it's associated
> Compute Reference Device (CRD) platform.
>
> https://www.qualcomm.com/products/mobile/snapdragon/laptops-and-tablets/snapdragon-x2-elite
> https://www.qualcomm.com/news/releases/2025/09/new-snapdragon-x2-elite-extreme-and-snapdragon-x2-elite-are-the-
>
> The base support enables booting to shell with rootfs on NVMe,
> demonstrating functionality for PCIe and NVMe subsystems.
> DCVS is also enabled, allowing dynamic frequency scaling for the CPUs.
> TSENS (Thermal Sensors) enabled for monitoring SoC temperature and
> thermal management. The platform is capable of booting kernel at EL2
> with kvm-unit tests performed on it for sanity.
>
> Features enabled in this patchset:
> 1. DCVS: CPU DCVS with scmi perf protocol
> 2. PCIe controller and PCIe PHY
> 3. NVMe storage support
> 4. Clocks and reset controllers - GCC, TCSRCC, DISPCC, RPMHCC
> 5. Interrupt controller
> 6. TLMM (Top-Level Mode Multiplexer)
> 7. QUP Block
> 8. Reserved memory regions
> 9. PMIC support with regulators
> 10. CPU Power Domains
> 11. TSENS (Thermal Sensors)
> 12. Remoteproc - SOCCP, ADSP and CDSP
> 13. RPMH Regulators
> 14. USB
>
> Dependencies:
>
> dt-bindings:
> 1. https://lore.kernel.org/all/20250918140249.2497794-1-pankaj.patil@oss.qualcomm.com/
> 2. https://lore.kernel.org/all/20250918141738.2524269-1-pankaj.patil@oss.qualcomm.com/
> 3. https://lore.kernel.org/all/20250919133439.965595-1-pankaj.patil@oss.qualcomm.com/
> 4. https://lore.kernel.org/all/20250919140952.1057737-1-pankaj.patil@oss.qualcomm.com/
> 5. https://lore.kernel.org/all/20250919141440.1068770-1-pankaj.patil@oss.qualcomm.com/
> 6. https://lore.kernel.org/all/20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com/
> 7. https://lore.kernel.org/all/20250920113052.151370-1-pankaj.patil@oss.qualcomm.com/
> 8. https://lore.kernel.org/all/20250924-knp-pmic-binding-v1-1-b9cce48b8460@oss.qualcomm.com/
> 9. https://lore.kernel.org/linux-arm-msm/20250924183726.509202-1-sibi.sankar@oss.qualcomm.com/T/#m46501fe9edb880fc11f69442eaf4d2855f7e4608
> 10. https://lore.kernel.org/linux-arm-msm/20250925002034.856692-1-sibi.sankar@oss.qualcomm.com/
> 11. https://lore.kernel.org/linux-arm-msm/20250924144831.336367-1-sibi.sankar@oss.qualcomm.com/
Please, don't list all the possible series. List only the patches which
define the bindings which are required to _build_ the dtb files and
which are not a part of linux-next. And also please include them into
`b4 prep --edit-deps` so that all the bots can pick them up.
>
> rpmh-regulators:
> 1. https://lore.kernel.org/all/20250918-glymur-rpmh-regulator-driver-v3-0-184c09678be3@oss.qualcomm.com/
This, for example, totally isn't a dependency for building the DT.
>
> PMICs:
> 1. https://lore.kernel.org/linux-arm-msm/20250924-knp-dts-v1-0-3fdbc4b9e1b1@oss.qualcomm.com/ (Patch 8-11)
>
> PMIC-Glink:
> 1. https://lore.kernel.org/all/20250919175025.2988948-1-anjelique.melendez@oss.qualcomm.com/
> 2. https://lore.kernel.org/all/20250924232631.644234-1-anjelique.melendez@oss.qualcomm.com/
>
> spmi/pinctrl:
> 1. https://lore.kernel.org/all/20250920-glymur-spmi-v8-gpio-driver-v1-0-23df93b7818a@oss.qualcomm.com/
>
> PCI:
> 1. https://lore.kernel.org/all/20250903-glymur_pcie5-v4-0-c187c2d9d3bd@oss.qualcomm.com/
>
> Remoteproc:
> 1. https://lore.kernel.org/all/20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com/
> 2. https://lore.kernel.org/linux-arm-msm/20250924-knp-remoteproc-v1-0-611bf7be8329@oss.qualcomm.com/T/#t
> 3. https://lore.kernel.org/linux-arm-msm/20250924-knp-remoteproc-v1-0-611bf7be8329@oss.qualcomm.com/T/#t
>
> USB:
> 1. https://lore.kernel.org/all/20250925005228.4035927-1-wesley.cheng@oss.qualcomm.com/T/#mb7879fdba16496554a53c3726d90f94b6063dd09
>
> Linux-next based git tree containing all Glymur related patches is available at:
> https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/glymur?ref_type=heads
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> Jyothi Kumar Seerapu (1):
> arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
>
> Kamal Wadhwa (10):
> arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
> arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device
> arm64: dts: qcom: Add PMCX0102 pmic dtsi
> arm64: dts: qcom: Add SMB2370 pmic dtsi
> arm64: dts: qcom: Update pmh0104 dtsi for Glymur CRD
> arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
> arm64: dts: qcom: glymur: Add PMICs dtsi for CRD
> arm64: boot: dts: glymur-crd: Add Volume down/up keys support
> arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
> arm64: dts: qcom: glymur: Add PMIC glink node
>
> Manaf Meethalavalappu Pallikunhi (1):
> arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes
>
> Maulik Shah (1):
> arm64: dts: qcom: glymur: Add cpu idle states
>
> Pankaj Patil (3):
> dt-bindings: arm: qcom: Document Glymur SoC and board
> arm64: defconfig: Enable Glymur configs for boot to shell
> arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
>
> Prudhvi Yarlagadda (1):
> arm64: dts: qcom: glymur: Add support for PCIe5
>
> Qiang Yu (1):
> arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5
>
> Sibi Sankar (3):
> arm64: dts: qcom: glymur: Enable pdp0 mailbox
> arm64: dts: qcom: glymur: Enable ipcc and aoss nodes
> arm64: dts: qcom: glymur: Add remoteprocs
>
> Taniya Das (2):
> arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling
> arm64: dts: qcom: glymur: Add display clock controller device
>
> Wesley Cheng (1):
> arm64: dts: qcom: glymur: Add USB support
>
> Documentation/devicetree/bindings/arm/qcom.yaml | 5 +
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 795 +++
> arch/arm64/boot/dts/qcom/glymur-pmics.dtsi | 19 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 7445 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 179 +
> arch/arm64/boot/dts/qcom/pmh0104.dtsi | 84 +
> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 +-
> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 +
> arch/arm64/configs/defconfig | 6 +
> 10 files changed, 8644 insertions(+), 1 deletion(-)
> ---
> base-commit: fdcd2cfdf0db0a8b8299de79302465f790edea27
> change-id: 20250923-v3_glymur_introduction-e22ae3c868a2
>
> Best regards,
> --
> Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 125+ messages in thread* Re: [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts
2025-09-25 17:30 ` [PATCH 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Dmitry Baryshkov
@ 2025-10-08 12:18 ` Pankaj Patil
0 siblings, 0 replies; 125+ messages in thread
From: Pankaj Patil @ 2025-10-08 12:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 9/25/2025 11:00 PM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 12:02:08PM +0530, Pankaj Patil wrote:
>> Introduce dt-bindings and initial device tree support for Glymur,
>> Qualcomm's next-generation compute SoC and it's associated
>> Compute Reference Device (CRD) platform.
>>
>> https://www.qualcomm.com/products/mobile/snapdragon/laptops-and-tablets/snapdragon-x2-elite
>> https://www.qualcomm.com/news/releases/2025/09/new-snapdragon-x2-elite-extreme-and-snapdragon-x2-elite-are-the-
>>
>> The base support enables booting to shell with rootfs on NVMe,
>> demonstrating functionality for PCIe and NVMe subsystems.
>> DCVS is also enabled, allowing dynamic frequency scaling for the CPUs.
>> TSENS (Thermal Sensors) enabled for monitoring SoC temperature and
>> thermal management. The platform is capable of booting kernel at EL2
>> with kvm-unit tests performed on it for sanity.
>>
>> Features enabled in this patchset:
>> 1. DCVS: CPU DCVS with scmi perf protocol
>> 2. PCIe controller and PCIe PHY
>> 3. NVMe storage support
>> 4. Clocks and reset controllers - GCC, TCSRCC, DISPCC, RPMHCC
>> 5. Interrupt controller
>> 6. TLMM (Top-Level Mode Multiplexer)
>> 7. QUP Block
>> 8. Reserved memory regions
>> 9. PMIC support with regulators
>> 10. CPU Power Domains
>> 11. TSENS (Thermal Sensors)
>> 12. Remoteproc - SOCCP, ADSP and CDSP
>> 13. RPMH Regulators
>> 14. USB
>>
>> Dependencies:
>>
>> dt-bindings:
>> 1. https://lore.kernel.org/all/20250918140249.2497794-1-pankaj.patil@oss.qualcomm.com/
>> 2. https://lore.kernel.org/all/20250918141738.2524269-1-pankaj.patil@oss.qualcomm.com/
>> 3. https://lore.kernel.org/all/20250919133439.965595-1-pankaj.patil@oss.qualcomm.com/
>> 4. https://lore.kernel.org/all/20250919140952.1057737-1-pankaj.patil@oss.qualcomm.com/
>> 5. https://lore.kernel.org/all/20250919141440.1068770-1-pankaj.patil@oss.qualcomm.com/
>> 6. https://lore.kernel.org/all/20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com/
>> 7. https://lore.kernel.org/all/20250920113052.151370-1-pankaj.patil@oss.qualcomm.com/
>> 8. https://lore.kernel.org/all/20250924-knp-pmic-binding-v1-1-b9cce48b8460@oss.qualcomm.com/
>> 9. https://lore.kernel.org/linux-arm-msm/20250924183726.509202-1-sibi.sankar@oss.qualcomm.com/T/#m46501fe9edb880fc11f69442eaf4d2855f7e4608
>> 10. https://lore.kernel.org/linux-arm-msm/20250925002034.856692-1-sibi.sankar@oss.qualcomm.com/
>> 11. https://lore.kernel.org/linux-arm-msm/20250924144831.336367-1-sibi.sankar@oss.qualcomm.com/
> Please, don't list all the possible series. List only the patches which
> define the bindings which are required to _build_ the dtb files and
> which are not a part of linux-next. And also please include them into
> `b4 prep --edit-deps` so that all the bots can pick them up.
Sure, I'll add singular patches using `b4 prep --edit-deps`
Bindings dependencies were added to avoid checkpatch warnings
about undocumented strings, dt can be built without the listed
dependencies except 9. patch 2/5.
>> rpmh-regulators:
>> 1. https://lore.kernel.org/all/20250918-glymur-rpmh-regulator-driver-v3-0-184c09678be3@oss.qualcomm.com/
> This, for example, totally isn't a dependency for building the DT.
>
>> PMICs:
>> 1. https://lore.kernel.org/linux-arm-msm/20250924-knp-dts-v1-0-3fdbc4b9e1b1@oss.qualcomm.com/ (Patch 8-11)
>>
>> PMIC-Glink:
>> 1. https://lore.kernel.org/all/20250919175025.2988948-1-anjelique.melendez@oss.qualcomm.com/
>> 2. https://lore.kernel.org/all/20250924232631.644234-1-anjelique.melendez@oss.qualcomm.com/
>>
>> spmi/pinctrl:
>> 1. https://lore.kernel.org/all/20250920-glymur-spmi-v8-gpio-driver-v1-0-23df93b7818a@oss.qualcomm.com/
>>
>> PCI:
>> 1. https://lore.kernel.org/all/20250903-glymur_pcie5-v4-0-c187c2d9d3bd@oss.qualcomm.com/
>>
>> Remoteproc:
>> 1. https://lore.kernel.org/all/20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com/
>> 2. https://lore.kernel.org/linux-arm-msm/20250924-knp-remoteproc-v1-0-611bf7be8329@oss.qualcomm.com/T/#t
>> 3. https://lore.kernel.org/linux-arm-msm/20250924-knp-remoteproc-v1-0-611bf7be8329@oss.qualcomm.com/T/#t
>>
>> USB:
>> 1. https://lore.kernel.org/all/20250925005228.4035927-1-wesley.cheng@oss.qualcomm.com/T/#mb7879fdba16496554a53c3726d90f94b6063dd09
>>
>> Linux-next based git tree containing all Glymur related patches is available at:
>> https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/glymur?ref_type=heads
>>
>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>> ---
>> Jyothi Kumar Seerapu (1):
>> arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
>>
>> Kamal Wadhwa (10):
>> arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
>> arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device
>> arm64: dts: qcom: Add PMCX0102 pmic dtsi
>> arm64: dts: qcom: Add SMB2370 pmic dtsi
>> arm64: dts: qcom: Update pmh0104 dtsi for Glymur CRD
>> arm64: dts: qcom: Update the pmh0110.dtsi for Glymur
>> arm64: dts: qcom: glymur: Add PMICs dtsi for CRD
>> arm64: boot: dts: glymur-crd: Add Volume down/up keys support
>> arm64: dts: qcom: glymur-crd: Avoid RTC probe failure
>> arm64: dts: qcom: glymur: Add PMIC glink node
>>
>> Manaf Meethalavalappu Pallikunhi (1):
>> arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes
>>
>> Maulik Shah (1):
>> arm64: dts: qcom: glymur: Add cpu idle states
>>
>> Pankaj Patil (3):
>> dt-bindings: arm: qcom: Document Glymur SoC and board
>> arm64: defconfig: Enable Glymur configs for boot to shell
>> arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts
>>
>> Prudhvi Yarlagadda (1):
>> arm64: dts: qcom: glymur: Add support for PCIe5
>>
>> Qiang Yu (1):
>> arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5
>>
>> Sibi Sankar (3):
>> arm64: dts: qcom: glymur: Enable pdp0 mailbox
>> arm64: dts: qcom: glymur: Enable ipcc and aoss nodes
>> arm64: dts: qcom: glymur: Add remoteprocs
>>
>> Taniya Das (2):
>> arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling
>> arm64: dts: qcom: glymur: Add display clock controller device
>>
>> Wesley Cheng (1):
>> arm64: dts: qcom: glymur: Add USB support
>>
>> Documentation/devicetree/bindings/arm/qcom.yaml | 5 +
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 795 +++
>> arch/arm64/boot/dts/qcom/glymur-pmics.dtsi | 19 +
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 7445 +++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 179 +
>> arch/arm64/boot/dts/qcom/pmh0104.dtsi | 84 +
>> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 +-
>> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 +
>> arch/arm64/configs/defconfig | 6 +
>> 10 files changed, 8644 insertions(+), 1 deletion(-)
>> ---
>> base-commit: fdcd2cfdf0db0a8b8299de79302465f790edea27
>> change-id: 20250923-v3_glymur_introduction-e22ae3c868a2
>>
>> Best regards,
>> --
>> Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>
^ permalink raw reply [flat|nested] 125+ messages in thread