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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7810239136dsm952962b3a.5.2025.09.24.23.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 23:29:41 -0700 (PDT) From: Pankaj Patil Date: Thu, 25 Sep 2025 11:58:20 +0530 Subject: [PATCH v2 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250925-v3_glymur_introduction-v2-14-8e1533a58d2d@oss.qualcomm.com> References: <20250925-v3_glymur_introduction-v2-0-8e1533a58d2d@oss.qualcomm.com> In-Reply-To: <20250925-v3_glymur_introduction-v2-0-8e1533a58d2d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , Kamal Wadhwa X-Mailer: b4 0.14.2 X-Proofpoint-GUID: ujXTlgL64YTBGP-fqutrsa_KTHw4d6_j X-Authority-Analysis: v=2.4 cv=YMOfyQGx c=1 sm=1 tr=0 ts=68d4e157 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=EOUZnPL1Ke5HISHMaDUA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAwNCBTYWx0ZWRfX2btfLHppxSSi Fb69XRbWiIoWypeliGXmQskpqbWyN2zow0JEbiEaW1IvfY6EjGIziJrAgRrWa6/dTPwSZgsI0yr +kWX3yFNq5Ln0wVsbCJR7uN4W2CnxrWkxo+iYkXYh045oeNVd5BbhtceAZzsncL+cSsgFvfLnY2 +fXPiIYKkvhqRO7JIszIqhL129x+xvKNlffQqHqOt1v2FpoyUB/UaA9wWQmFCLkT+KBeGXxhEWD 2yPYo5Qe8HKXJWyg+94/oFiWivw2GRlb2XOTRihi/72CEEmsjybOIlz6+sQY57igjU853UYAjn0 HMIfWkBTWuyXQWUWnQmA4TrSmr4AohzKZjcMouLmJ5q8oUGe4o6xnfsHZYUbLOlz/GT5qvHMAxS lOOOmJvv X-Proofpoint-ORIG-GUID: ujXTlgL64YTBGP-fqutrsa_KTHw4d6_j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_07,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200004 From: Kamal Wadhwa Add multiple instance of PMH0110 DT node, one for each assigned SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur CRD. Take care to avoid compilation issue with the existing nodes by gaurding each PMH0110 nodes with `#ifdef` for its corresponding SID macro. So that only the nodes which have the their SID macro defined are the only ones picked for compilation. Signed-off-by: Kamal Wadhwa Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644 --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi @@ -7,6 +7,8 @@ #include &spmi_bus0 { + +#ifdef PMH0110_D_E0_SID pmh0110_d_e0: pmic@PMH0110_D_E0_SID { compatible = "qcom,pmh0110", "qcom,spmi-pmic"; reg = ; @@ -31,13 +33,14 @@ pmh0110_d_e0_gpios: gpio@8800 { #interrupt-cells = <2>; }; }; +#endif +#ifdef PMH0110_F_E0_SID pmh0110_f_e0: pmic@PMH0110_F_E0_SID { compatible = "qcom,pmh0110", "qcom,spmi-pmic"; reg = ; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; pmh0110_f_e0_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -56,7 +59,9 @@ pmh0110_f_e0_gpios: gpio@8800 { #interrupt-cells = <2>; }; }; +#endif +#ifdef PMH0110_G_E0_SID pmh0110_g_e0: pmic@PMH0110_G_E0_SID { compatible = "qcom,pmh0110", "qcom,spmi-pmic"; reg = ; @@ -81,7 +86,36 @@ pmh0110_g_e0_gpios: gpio@8800 { #interrupt-cells = <2>; }; }; +#endif + +#ifdef PMH0110_H_E0_SID + pmh0110_h_e0: pmic@PMH0110_H_E0_SID { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pmh0110_h_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = ; + #thermal-sensor-cells = <0>; + }; + + pmh0110_h_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +#endif +#ifdef PMH0110_I_E0_SID pmh0110_i_e0: pmic@PMH0110_I_E0_SID { compatible = "qcom,pmh0110", "qcom,spmi-pmic"; reg = ; @@ -106,4 +140,34 @@ pmh0110_i_e0_gpios: gpio@8800 { #interrupt-cells = <2>; }; }; +#endif +}; + +&spmi_bus1 { +#ifdef PMH0110_F_E1_SID + pmh0110_f_e1: pmic@PMH0110_F_E1_SID { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pmh0110_f_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = ; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +#endif }; -- 2.34.1