* [PATCH v3 0/4] PCI: mediatek: add support AN7583 + YAML rework
@ 2025-09-25 16:23 Christian Marangi
2025-09-25 16:23 ` [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 Christian Marangi
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Christian Marangi @ 2025-09-25 16:23 UTC (permalink / raw)
To: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Christian Marangi,
linux-pci, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, upstream
This little series convert the PCIe GEN2 Documentation to YAML schema
and adds support for Airoha AN7583 GEN2 PCIe Controller.
Changes v3:
- Rework patch 1 to drop syscon compatible
Changes v2:
- Add cover letter
- Describe skip_pcie_rstb variable
- Fix hifsys schema (missing syscon)
- Address comments on the YAML schema for PCIe GEN2
- Keep alphabetical order for AN7583
Christian Marangi (4):
ARM: dts: mediatek: drop wrong syscon hifsys compatible for
MT2701/7623
dt-bindings: PCI: mediatek: Convert to YAML schema
dt-bindings: PCI: mediatek: Add support for Airoha AN7583
PCI: mediatek: add support for Airoha AN7583 SoC
.../bindings/pci/mediatek-pcie-mt7623.yaml | 173 ++++++
.../devicetree/bindings/pci/mediatek-pcie.txt | 289 ----------
.../bindings/pci/mediatek-pcie.yaml | 514 ++++++++++++++++++
arch/arm/boot/dts/mediatek/mt2701.dtsi | 2 +-
arch/arm/boot/dts/mediatek/mt7623.dtsi | 3 +-
drivers/pci/controller/pcie-mediatek.c | 85 ++-
6 files changed, 752 insertions(+), 314 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
--
2.51.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 2025-09-25 16:23 [PATCH v3 0/4] PCI: mediatek: add support AN7583 + YAML rework Christian Marangi @ 2025-09-25 16:23 ` Christian Marangi 2025-09-26 20:53 ` Bjorn Helgaas 2025-09-29 10:10 ` AngeloGioacchino Del Regno 2025-09-25 16:23 ` [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema Christian Marangi ` (2 subsequent siblings) 3 siblings, 2 replies; 12+ messages in thread From: Christian Marangi @ 2025-09-25 16:23 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Christian Marangi, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream The syscon compatible for the hifsys node for Mediatek MT2701/MT7623 SoC was wrongly added following the pattern of other clock node but it's actually not needed as the register are not used by other device on the SoC. On top of this it does against the schema for hifsys amnd cause dtbs_check warning. Drop the "syscon" compatible to mute the warning and reflect the compatible property described in the mediatek,mt2701-hifsys.yaml schema. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- arch/arm/boot/dts/mediatek/mt2701.dtsi | 2 +- arch/arm/boot/dts/mediatek/mt7623.dtsi | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi index ce6a4015fed5..128b87229f3d 100644 --- a/arch/arm/boot/dts/mediatek/mt2701.dtsi +++ b/arch/arm/boot/dts/mediatek/mt2701.dtsi @@ -597,7 +597,7 @@ larb1: larb@16010000 { }; hifsys: syscon@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; + compatible = "mediatek,mt2701-hifsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index fd7a89cc337d..4b1685b93989 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -744,8 +744,7 @@ vdecsys: syscon@16000000 { hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; + "mediatek,mt2701-hifsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 2025-09-25 16:23 ` [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 Christian Marangi @ 2025-09-26 20:53 ` Bjorn Helgaas 2025-09-29 10:10 ` AngeloGioacchino Del Regno 1 sibling, 0 replies; 12+ messages in thread From: Bjorn Helgaas @ 2025-09-26 20:53 UTC (permalink / raw) To: Christian Marangi Cc: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream On Thu, Sep 25, 2025 at 06:23:15PM +0200, Christian Marangi wrote: > The syscon compatible for the hifsys node for Mediatek MT2701/MT7623 SoC > was wrongly added following the pattern of other clock node but it's > actually not needed as the register are not used by other device on the > SoC. > > On top of this it does against the schema for hifsys amnd cause > dtbs_check warning. s/does/<something else, not sure what you mean>/ s/amnd/and/ ? s/cause/causes a/ > Drop the "syscon" compatible to mute the warning and reflect the > compatible property described in the mediatek,mt2701-hifsys.yaml schema. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > arch/arm/boot/dts/mediatek/mt2701.dtsi | 2 +- > arch/arm/boot/dts/mediatek/mt7623.dtsi | 3 +-- > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/mediatek/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi > index ce6a4015fed5..128b87229f3d 100644 > --- a/arch/arm/boot/dts/mediatek/mt2701.dtsi > +++ b/arch/arm/boot/dts/mediatek/mt2701.dtsi > @@ -597,7 +597,7 @@ larb1: larb@16010000 { > }; > > hifsys: syscon@1a000000 { > - compatible = "mediatek,mt2701-hifsys", "syscon"; > + compatible = "mediatek,mt2701-hifsys"; > reg = <0 0x1a000000 0 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi > index fd7a89cc337d..4b1685b93989 100644 > --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi > +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi > @@ -744,8 +744,7 @@ vdecsys: syscon@16000000 { > > hifsys: syscon@1a000000 { > compatible = "mediatek,mt7623-hifsys", > - "mediatek,mt2701-hifsys", > - "syscon"; > + "mediatek,mt2701-hifsys"; > reg = <0 0x1a000000 0 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > -- > 2.51.0 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 2025-09-25 16:23 ` [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 Christian Marangi 2025-09-26 20:53 ` Bjorn Helgaas @ 2025-09-29 10:10 ` AngeloGioacchino Del Regno 1 sibling, 0 replies; 12+ messages in thread From: AngeloGioacchino Del Regno @ 2025-09-29 10:10 UTC (permalink / raw) To: Christian Marangi, Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream Il 25/09/25 18:23, Christian Marangi ha scritto: > The syscon compatible for the hifsys node for Mediatek MT2701/MT7623 SoC > was wrongly added following the pattern of other clock node but it's > actually not needed as the register are not used by other device on the > SoC. > > On top of this it does against the schema for hifsys amnd cause > dtbs_check warning. > > Drop the "syscon" compatible to mute the warning and reflect the > compatible property described in the mediatek,mt2701-hifsys.yaml schema. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema 2025-09-25 16:23 [PATCH v3 0/4] PCI: mediatek: add support AN7583 + YAML rework Christian Marangi 2025-09-25 16:23 ` [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 Christian Marangi @ 2025-09-25 16:23 ` Christian Marangi 2025-09-26 13:09 ` Rob Herring (Arm) 2025-09-26 21:26 ` Rob Herring 2025-09-25 16:23 ` [PATCH v3 3/4] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Christian Marangi 2025-09-25 16:23 ` [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Christian Marangi 3 siblings, 2 replies; 12+ messages in thread From: Christian Marangi @ 2025-09-25 16:23 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Christian Marangi, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream Convert the PCI mediatek Documentation to YAML schema to enable validation of the supported GEN1/2 Mediatek PCIe controller. While converting, lots of cleanup were done from the .txt with better specifying what is supported by the various PCIe controller variant and drop of redundant info that are part of the standard PCIe Host Bridge schema. To reduce schema complexity the .txt is split in 2 YAML, one for mt7623/mt2701 and the other for every other compatible. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- .../bindings/pci/mediatek-pcie-mt7623.yaml | 173 ++++++++ .../devicetree/bindings/pci/mediatek-pcie.txt | 289 ------------- .../bindings/pci/mediatek-pcie.yaml | 404 ++++++++++++++++++ 3 files changed, 577 insertions(+), 289 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml delete mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml new file mode 100644 index 000000000000..2f201c84e29a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +properties: + compatible: + enum: + - mediatek,mt2701-pcie + - mediatek,mt7623-pcie + + reg: + minItems: 4 + maxItems: 4 + + reg-names: + items: + - const: subsys + - const: port0 + - const: port1 + - const: port2 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: free_ck + - const: sys_ck0 + - const: sys_ck1 + - const: sys_ck2 + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: pcie-rst0 + - const: pcie-rst1 + - const: pcie-rst2 + + phys: + minItems: 3 + maxItems: 3 + + phy-names: + items: + - const: pcie-phy0 + - const: pcie-phy1 + - const: pcie-phy2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - resets + - reset-names + - phys + - phy-names + - power-domains + - pcie@0,0 + - pcie@1,0 + - pcie@2,0 + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + # MT7623 + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mt2701-clk.h> + #include <dt-bindings/reset/mt2701-resets.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/power/mt2701-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "mediatek,mt2701-hifsys", + "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ + + pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@1,0 { + device_type = "pci"; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@2,0 { + device_type = "pci"; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt deleted file mode 100644 index 684227522267..000000000000 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ /dev/null @@ -1,289 +0,0 @@ -MediaTek Gen2 PCIe controller - -Required properties: -- compatible: Should contain one of the following strings: - "mediatek,mt2701-pcie" - "mediatek,mt2712-pcie" - "mediatek,mt7622-pcie" - "mediatek,mt7623-pcie" - "mediatek,mt7629-pcie" - "airoha,en7523-pcie" -- device_type: Must be "pci" -- reg: Base addresses and lengths of the root ports. -- reg-names: Names of the above areas to use during resource lookup. -- #address-cells: Address representation for root ports (must be 3) -- #size-cells: Size representation for root ports (must be 2) -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: - Mandatory entries: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys - Required entries for MT2712/MT7622: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access - Required entries for MT7622: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off - - obff_ckN :OBFF functional block operating clock - - pipe_ckN :LTSSM and PHY/MAC layer operating clock - where N starting from 0 to one less than the number of root ports. -- phys: List of PHY specifiers (used by generic PHY framework). -- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of PHYs as specified in *phys* property. -- power-domains: A phandle and power domain specifier pair to the power domain - which is responsible for collapsing and restoring power to the peripheral. -- bus-range: Range of bus numbers associated with this controller. -- ranges: Ranges for the PCI memory and I/O regions. - -Required properties for MT7623/MT2701: -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - -Required properties for MT2712/MT7622/MT7629: --interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port -- interrupt-names: Must include the following entries: - - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received -- linux,pci-domain: PCI domain ID. Should be unique for each host controller - -In addition, the device tree node must have sub-nodes describing each -PCIe port interface, having the following mandatory properties: - -Required properties: -- device_type: Must be "pci" -- reg: Only the first four bytes are used to refer to the correct bus number - and device number. -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- #interrupt-cells: Must be 1 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. - -Examples for MT7623: - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7623-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names = "subsys", "port0", "port1", "port2"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 0>; - interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, - <&pcie2_phy PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@2,0 { - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - }; - -Examples for MT2712: - - pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; - reg = <0 0x112ff000 0 0x1000>; - reg-names = "port1"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pcie_irq"; - clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; - clock-names = "sys_ck1", "ahb_ck1"; - phys = <&u3port1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie0: pcie@11700000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; - reg = <0 0x11700000 0 0x1000>; - reg-names = "port0"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pcie_irq"; - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&pericfg CLK_PERI_PCIE0>; - clock-names = "sys_ck0", "ahb_ck0"; - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy0"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - -Examples for MT7622: - - pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0 0x1a143000 0 0x1000>; - reg-names = "port0"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>; - clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", - "axi_ck0", "obff_ck0", "pipe_ck0"; - - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1a145000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0 0x1a145000 0 0x1000>; - reg-names = "port1"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - /* designer has connect RC1 with p0_ahb clock */ - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", - "axi_ck1", "obff_ck1", "pipe_ck1"; - - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml new file mode 100644 index 000000000000..e3afedb77a01 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -0,0 +1,404 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2712-pcie + - mediatek,mt7622-pcie + - mediatek,mt7629-pcie + - items: + - const: airoha,en7523-pcie + - const: mediatek,mt7622-pcie + + reg: + minItems: 1 + maxItems: 4 + + reg-names: + minItems: 1 + maxItems: 4 + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + interrupts: + maxItems: 1 + + interrupt-names: + const: pcie_irq + + resets: + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 + + phys: + minItems: 1 + maxItems: 3 + + phy-names: + minItems: 1 + maxItems: 3 + + power-domains: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupts + - interrupt-names + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + + - if: + properties: + compatible: + const: mediatek,mt2712-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + + reset: false + + reset-names: false + + phys: + maxItems: 1 + + phy-names: + items: + - enum: [ pcie-phy0, pcie-phy1 ] + + power-domains: false + + required: + - phys + - phy-names + + - if: + properties: + compatible: + const: mediatek,mt7622-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + - enum: [ aux_ck0, aux_ck1 ] + - enum: [ axi_ck0, axi_ck1 ] + - enum: [ obff_ck0, obff_ck1 ] + - enum: [ pipe_ck0, pipe_ck1 ] + + reset: false + + reset-names: false + + phys: false + + phy-names: false + + required: + - power-domains + + - if: + properties: + compatible: + const: mediatek,mt7629-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + - enum: [ aux_ck0, aux_ck1 ] + - enum: [ axi_ck0, axi_ck1 ] + - enum: [ obff_ck0, obff_ck1 ] + - enum: [ pipe_ck0, pipe_ck1 ] + + reset: false + + reset-names: false + + phys: + maxItems: 1 + + phy-names: + items: + - enum: [ pcie-phy0, pcie-phy1 ] + + required: + - power-domains + + - if: + properties: + compatible: + contains: + const: airoha,en7523-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + maxItems: 1 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + + reset: false + + reset-names: false + + phys: false + + phy-names: false + + power-domain: false + +unevaluatedProperties: false + +examples: + # MT2712 + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/phy/phy.h> + + soc_1 { + #address-cells = <2>; + #size-cells = <2>; + + pcie@112ff000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x112ff000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ + <&pericfg>; /* CLK_PERI_PCIE1 */ + clock-names = "sys_ck1", "ahb_ck1"; + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie@11700000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x11700000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ + <&pericfg>; /* CLK_PERI_PCIE0 */ + clock-names = "sys_ck0", "ahb_ck0"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + # MT7622 + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt7622-power.h> + + soc_2 { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1a143000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0 0x1a143000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "pcie_irq"; + clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", + "axi_ck0", "obff_ck0", "pipe_ck0"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0_1 0>, + <0 0 0 2 &pcie_intc0_1 1>, + <0 0 0 3 &pcie_intc0_1 2>, + <0 0 0 4 &pcie_intc0_1 3>; + pcie_intc0_1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie@1a145000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0 0x1a145000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "pcie_irq"; + clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ + /* designer has connect RC1 with p0_ahb clock */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", + "axi_ck1", "obff_ck1", "pipe_ck1"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1_1 0>, + <0 0 0 2 &pcie_intc1_1 1>, + <0 0 0 3 &pcie_intc1_1 2>, + <0 0 0 4 &pcie_intc1_1 3>; + pcie_intc1_1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema 2025-09-25 16:23 ` [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema Christian Marangi @ 2025-09-26 13:09 ` Rob Herring (Arm) 2025-09-26 21:26 ` Rob Herring 1 sibling, 0 replies; 12+ messages in thread From: Rob Herring (Arm) @ 2025-09-26 13:09 UTC (permalink / raw) To: Christian Marangi Cc: Ryder Lee, Lorenzo Pieralisi, Krzysztof Wilczyński, Matthias Brugger, Conor Dooley, Manivannan Sadhasivam, Bjorn Helgaas, AngeloGioacchino Del Regno, devicetree, linux-kernel, Krzysztof Kozlowski, linux-pci, linux-mediatek, linux-arm-kernel, upstream, Jianjun Wang On Thu, 25 Sep 2025 18:23:16 +0200, Christian Marangi wrote: > Convert the PCI mediatek Documentation to YAML schema to enable > validation of the supported GEN1/2 Mediatek PCIe controller. > > While converting, lots of cleanup were done from the .txt with better > specifying what is supported by the various PCIe controller variant and > drop of redundant info that are part of the standard PCIe Host Bridge > schema. > > To reduce schema complexity the .txt is split in 2 YAML, one for > mt7623/mt2701 and the other for every other compatible. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > .../bindings/pci/mediatek-pcie-mt7623.yaml | 173 ++++++++ > .../devicetree/bindings/pci/mediatek-pcie.txt | 289 ------------- > .../bindings/pci/mediatek-pcie.yaml | 404 ++++++++++++++++++ > 3 files changed, 577 insertions(+), 289 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml > delete mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.example.dtb: syscon@1a000000 (mediatek,mt7623-hifsys): compatible: 'oneOf' conditional failed, one must be fixed: ['mediatek,mt7623-hifsys', 'mediatek,mt2701-hifsys', 'syscon'] is too long 'mediatek,mt7623-hifsys' is not one of ['mediatek,mt2701-hifsys', 'mediatek,mt7622-hifsys'] from schema $id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250925162332.9794-3-ansuelsmth@gmail.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema 2025-09-25 16:23 ` [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema Christian Marangi 2025-09-26 13:09 ` Rob Herring (Arm) @ 2025-09-26 21:26 ` Rob Herring 1 sibling, 0 replies; 12+ messages in thread From: Rob Herring @ 2025-09-26 21:26 UTC (permalink / raw) To: Christian Marangi Cc: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream On Thu, Sep 25, 2025 at 06:23:16PM +0200, Christian Marangi wrote: > Convert the PCI mediatek Documentation to YAML schema to enable > validation of the supported GEN1/2 Mediatek PCIe controller. > > While converting, lots of cleanup were done from the .txt with better > specifying what is supported by the various PCIe controller variant and > drop of redundant info that are part of the standard PCIe Host Bridge > schema. > > To reduce schema complexity the .txt is split in 2 YAML, one for > mt7623/mt2701 and the other for every other compatible. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > .../bindings/pci/mediatek-pcie-mt7623.yaml | 173 ++++++++ > .../devicetree/bindings/pci/mediatek-pcie.txt | 289 ------------- > .../bindings/pci/mediatek-pcie.yaml | 404 ++++++++++++++++++ > 3 files changed, 577 insertions(+), 289 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml > delete mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml > new file mode 100644 > index 000000000000..2f201c84e29a > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml > @@ -0,0 +1,173 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PCIe controller on MediaTek SoCs > + > +maintainers: > + - Christian Marangi <ansuelsmth@gmail.com> > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-pcie > + - mediatek,mt7623-pcie > + > + reg: > + minItems: 4 > + maxItems: 4 > + > + reg-names: > + items: > + - const: subsys > + - const: port0 > + - const: port1 > + - const: port2 > + > + clocks: > + minItems: 4 > + maxItems: 4 > + > + clock-names: > + items: > + - const: free_ck > + - const: sys_ck0 > + - const: sys_ck1 > + - const: sys_ck2 > + > + resets: > + minItems: 3 > + maxItems: 3 > + > + reset-names: > + items: > + - const: pcie-rst0 > + - const: pcie-rst1 > + - const: pcie-rst2 > + > + phys: > + minItems: 3 > + maxItems: 3 > + > + phy-names: > + items: > + - const: pcie-phy0 > + - const: pcie-phy1 > + - const: pcie-phy2 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - reg-names > + - ranges > + - clocks > + - clock-names > + - '#interrupt-cells' > + - resets > + - reset-names > + - phys > + - phy-names > + - power-domains > + - pcie@0,0 > + - pcie@1,0 > + - pcie@2,0 > + > +allOf: > + - $ref: /schemas/pci/pci-host-bridge.yaml# > + > +unevaluatedProperties: false > + > +examples: > + # MT7623 > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/mt2701-clk.h> > + #include <dt-bindings/reset/mt2701-resets.h> > + #include <dt-bindings/phy/phy.h> > + #include <dt-bindings/power/mt2701-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + hifsys: syscon@1a000000 { > + compatible = "mediatek,mt7623-hifsys", > + "mediatek,mt2701-hifsys", > + "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; Drop this node. It's not part of this schema. > + > + pcie@1a140000 { > + compatible = "mediatek,mt7623-pcie"; > + device_type = "pci"; > + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ > + <0 0x1a142000 0 0x1000>, /* Port0 registers */ > + <0 0x1a143000 0 0x1000>, /* Port1 registers */ > + <0 0x1a144000 0 0x1000>; /* Port2 registers */ > + reg-names = "subsys", "port0", "port1", "port2"; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0xf800 0 0 0>; > + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, > + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, > + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > + <&hifsys CLK_HIFSYS_PCIE0>, > + <&hifsys CLK_HIFSYS_PCIE1>, > + <&hifsys CLK_HIFSYS_PCIE2>; > + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; > + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, > + <&hifsys MT2701_HIFSYS_PCIE1_RST>, > + <&hifsys MT2701_HIFSYS_PCIE2_RST>; > + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; > + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, > + <&pcie2_phy PHY_TYPE_PCIE>; > + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; > + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; > + bus-range = <0x00 0xff>; > + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ > + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ Use <> on each entry. > + > + pcie@0,0 { > + device_type = "pci"; > + reg = <0x0000 0 0 0 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; > + ranges; > + }; > + > + pcie@1,0 { > + device_type = "pci"; > + reg = <0x0800 0 0 0 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; > + ranges; > + }; > + > + pcie@2,0 { > + device_type = "pci"; > + reg = <0x1000 0 0 0 0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; > + ranges; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > deleted file mode 100644 > index 684227522267..000000000000 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt > +++ /dev/null > @@ -1,289 +0,0 @@ > -MediaTek Gen2 PCIe controller > - > -Required properties: > -- compatible: Should contain one of the following strings: > - "mediatek,mt2701-pcie" > - "mediatek,mt2712-pcie" > - "mediatek,mt7622-pcie" > - "mediatek,mt7623-pcie" > - "mediatek,mt7629-pcie" > - "airoha,en7523-pcie" > -- device_type: Must be "pci" > -- reg: Base addresses and lengths of the root ports. > -- reg-names: Names of the above areas to use during resource lookup. > -- #address-cells: Address representation for root ports (must be 3) > -- #size-cells: Size representation for root ports (must be 2) > -- clocks: Must contain an entry for each entry in clock-names. > - See ../clocks/clock-bindings.txt for details. > -- clock-names: > - Mandatory entries: > - - sys_ckN :transaction layer and data link layer clock > - Required entries for MT2701/MT7623: > - - free_ck :for reference clock of PCIe subsys > - Required entries for MT2712/MT7622: > - - ahb_ckN :AHB slave interface operating clock for CSR access and RC > - initiated MMIO access > - Required entries for MT7622: > - - axi_ckN :application layer MMIO channel operating clock > - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when > - pcie_mac_ck/pcie_pipe_ck is turned off > - - obff_ckN :OBFF functional block operating clock > - - pipe_ckN :LTSSM and PHY/MAC layer operating clock > - where N starting from 0 to one less than the number of root ports. > -- phys: List of PHY specifiers (used by generic PHY framework). > -- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the > - number of PHYs as specified in *phys* property. > -- power-domains: A phandle and power domain specifier pair to the power domain > - which is responsible for collapsing and restoring power to the peripheral. > -- bus-range: Range of bus numbers associated with this controller. > -- ranges: Ranges for the PCI memory and I/O regions. > - > -Required properties for MT7623/MT2701: > -- #interrupt-cells: Size representation for interrupts (must be 1) > -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties > - Please refer to the standard PCI bus binding document for a more detailed > - explanation. > -- resets: Must contain an entry for each entry in reset-names. > - See ../reset/reset.txt for details. > -- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the > - number of root ports. > - > -Required properties for MT2712/MT7622/MT7629: > --interrupts: A list of interrupt outputs of the controller, must have one > - entry for each PCIe port > -- interrupt-names: Must include the following entries: > - - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received > -- linux,pci-domain: PCI domain ID. Should be unique for each host controller > - > -In addition, the device tree node must have sub-nodes describing each > -PCIe port interface, having the following mandatory properties: > - > -Required properties: > -- device_type: Must be "pci" > -- reg: Only the first four bytes are used to refer to the correct bus number > - and device number. > -- #address-cells: Must be 3 > -- #size-cells: Must be 2 > -- #interrupt-cells: Must be 1 > -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties > - Please refer to the standard PCI bus binding document for a more detailed > - explanation. > -- ranges: Sub-ranges distributed from the PCIe controller node. An empty > - property is sufficient. > - > -Examples for MT7623: > - > - hifsys: syscon@1a000000 { > - compatible = "mediatek,mt7623-hifsys", > - "mediatek,mt2701-hifsys", > - "syscon"; > - reg = <0 0x1a000000 0 0x1000>; > - #clock-cells = <1>; > - #reset-cells = <1>; > - }; > - > - pcie: pcie@1a140000 { > - compatible = "mediatek,mt7623-pcie"; > - device_type = "pci"; > - reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ > - <0 0x1a142000 0 0x1000>, /* Port0 registers */ > - <0 0x1a143000 0 0x1000>, /* Port1 registers */ > - <0 0x1a144000 0 0x1000>; /* Port2 registers */ > - reg-names = "subsys", "port0", "port1", "port2"; > - #address-cells = <3>; > - #size-cells = <2>; > - #interrupt-cells = <1>; > - interrupt-map-mask = <0xf800 0 0 0>; > - interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, > - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, > - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > - <&hifsys CLK_HIFSYS_PCIE0>, > - <&hifsys CLK_HIFSYS_PCIE1>, > - <&hifsys CLK_HIFSYS_PCIE2>; > - clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; > - resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, > - <&hifsys MT2701_HIFSYS_PCIE1_RST>, > - <&hifsys MT2701_HIFSYS_PCIE2_RST>; > - reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; > - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, > - <&pcie2_phy PHY_TYPE_PCIE>; > - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; > - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; > - bus-range = <0x00 0xff>; > - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ > - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ > - > - pcie@0,0 { > - reg = <0x0000 0 0 0 0>; > - #address-cells = <3>; > - #size-cells = <2>; > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; > - ranges; > - }; > - > - pcie@1,0 { > - reg = <0x0800 0 0 0 0>; > - #address-cells = <3>; > - #size-cells = <2>; > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; > - ranges; > - }; > - > - pcie@2,0 { > - reg = <0x1000 0 0 0 0>; > - #address-cells = <3>; > - #size-cells = <2>; > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; > - ranges; > - }; > - }; > - > -Examples for MT2712: > - > - pcie1: pcie@112ff000 { > - compatible = "mediatek,mt2712-pcie"; > - device_type = "pci"; > - reg = <0 0x112ff000 0 0x1000>; > - reg-names = "port1"; > - linux,pci-domain = <1>; > - #address-cells = <3>; > - #size-cells = <2>; > - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "pcie_irq"; > - clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, > - <&pericfg CLK_PERI_PCIE1>; > - clock-names = "sys_ck1", "ahb_ck1"; > - phys = <&u3port1 PHY_TYPE_PCIE>; > - phy-names = "pcie-phy1"; > - bus-range = <0x00 0xff>; > - ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; > - status = "disabled"; > - > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc1 0>, > - <0 0 0 2 &pcie_intc1 1>, > - <0 0 0 3 &pcie_intc1 2>, > - <0 0 0 4 &pcie_intc1 3>; > - pcie_intc1: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > - > - pcie0: pcie@11700000 { > - compatible = "mediatek,mt2712-pcie"; > - device_type = "pci"; > - reg = <0 0x11700000 0 0x1000>; > - reg-names = "port0"; > - linux,pci-domain = <0>; > - #address-cells = <3>; > - #size-cells = <2>; > - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "pcie_irq"; > - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, > - <&pericfg CLK_PERI_PCIE0>; > - clock-names = "sys_ck0", "ahb_ck0"; > - phys = <&u3port0 PHY_TYPE_PCIE>; > - phy-names = "pcie-phy0"; > - bus-range = <0x00 0xff>; > - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; > - status = "disabled"; > - > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc0 0>, > - <0 0 0 2 &pcie_intc0 1>, > - <0 0 0 3 &pcie_intc0 2>, > - <0 0 0 4 &pcie_intc0 3>; > - pcie_intc0: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > - > -Examples for MT7622: > - > - pcie0: pcie@1a143000 { > - compatible = "mediatek,mt7622-pcie"; > - device_type = "pci"; > - reg = <0 0x1a143000 0 0x1000>; > - reg-names = "port0"; > - linux,pci-domain = <0>; > - #address-cells = <3>; > - #size-cells = <2>; > - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; > - interrupt-names = "pcie_irq"; > - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, > - <&pciesys CLK_PCIE_P0_AHB_EN>, > - <&pciesys CLK_PCIE_P0_AUX_EN>, > - <&pciesys CLK_PCIE_P0_AXI_EN>, > - <&pciesys CLK_PCIE_P0_OBFF_EN>, > - <&pciesys CLK_PCIE_P0_PIPE_EN>; > - clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", > - "axi_ck0", "obff_ck0", "pipe_ck0"; > - > - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; > - bus-range = <0x00 0xff>; > - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; > - status = "disabled"; > - > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc0 0>, > - <0 0 0 2 &pcie_intc0 1>, > - <0 0 0 3 &pcie_intc0 2>, > - <0 0 0 4 &pcie_intc0 3>; > - pcie_intc0: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > - > - pcie1: pcie@1a145000 { > - compatible = "mediatek,mt7622-pcie"; > - device_type = "pci"; > - reg = <0 0x1a145000 0 0x1000>; > - reg-names = "port1"; > - linux,pci-domain = <1>; > - #address-cells = <3>; > - #size-cells = <2>; > - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > - interrupt-names = "pcie_irq"; > - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, > - /* designer has connect RC1 with p0_ahb clock */ > - <&pciesys CLK_PCIE_P0_AHB_EN>, > - <&pciesys CLK_PCIE_P1_AUX_EN>, > - <&pciesys CLK_PCIE_P1_AXI_EN>, > - <&pciesys CLK_PCIE_P1_OBFF_EN>, > - <&pciesys CLK_PCIE_P1_PIPE_EN>; > - clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", > - "axi_ck1", "obff_ck1", "pipe_ck1"; > - > - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; > - bus-range = <0x00 0xff>; > - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; > - status = "disabled"; > - > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = <0 0 0 1 &pcie_intc1 0>, > - <0 0 0 2 &pcie_intc1 1>, > - <0 0 0 3 &pcie_intc1 2>, > - <0 0 0 4 &pcie_intc1 3>; > - pcie_intc1: interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml > new file mode 100644 > index 000000000000..e3afedb77a01 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml > @@ -0,0 +1,404 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PCIe controller on MediaTek SoCs > + > +maintainers: > + - Christian Marangi <ansuelsmth@gmail.com> > + > +properties: > + compatible: > + oneOf: > + - enum: > + - mediatek,mt2712-pcie > + - mediatek,mt7622-pcie > + - mediatek,mt7629-pcie > + - items: > + - const: airoha,en7523-pcie > + - const: mediatek,mt7622-pcie > + > + reg: > + minItems: 1 > + maxItems: 4 > + > + reg-names: > + minItems: 1 > + maxItems: 4 Looks to me like max is 1 entry which is either port0 or port1. > + > + clocks: > + minItems: 1 > + maxItems: 6 > + > + clock-names: > + minItems: 1 > + maxItems: 6 > + > + interrupts: > + maxItems: 1 > + > + interrupt-names: > + const: pcie_irq > + > + resets: > + minItems: 1 > + maxItems: 3 > + > + reset-names: > + minItems: 1 > + maxItems: 3 > + > + phys: > + minItems: 1 > + maxItems: 3 > + > + phy-names: > + minItems: 1 > + maxItems: 3 Isn't the max 1? > + > + power-domains: > + maxItems: 1 > + > + '#interrupt-cells': > + const: 1 > + > + interrupt-controller: > + description: Interrupt controller node for handling legacy PCI interrupts. > + type: object > + properties: > + '#address-cells': > + const: 0 > + '#interrupt-cells': > + const: 1 > + interrupt-controller: true > + > + required: > + - '#address-cells' > + - '#interrupt-cells' > + - interrupt-controller > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - reg-names > + - ranges > + - clocks > + - clock-names > + - '#interrupt-cells' > + - interrupts > + - interrupt-names > + - interrupt-controller > + > +allOf: > + - $ref: /schemas/pci/pci-host-bridge.yaml# > + > + - if: > + properties: > + compatible: > + const: mediatek,mt2712-pcie > + then: > + properties: > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - enum: [ port0, port1 ] The point of spliting this into 2 schemas was to reduce or get rid of all the if/then schemas. > + > + clocks: > + minItems: 2 > + maxItems: 2 > + > + clock-names: > + items: > + - enum: [ sys_ck0, sys_ck1 ] > + - enum: [ ahb_ck0, ahb_ck1 ] > + > + reset: false > + > + reset-names: false > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - enum: [ pcie-phy0, pcie-phy1 ] This goes in the top-level. > + > + power-domains: false > + > + required: > + - phys > + - phy-names > + > + - if: > + properties: > + compatible: > + const: mediatek,mt7622-pcie > + then: > + properties: > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - enum: [ port0, port1 ] > + > + clocks: > + minItems: 6 > + maxItems: 6 > + > + clock-names: > + items: > + - enum: [ sys_ck0, sys_ck1 ] > + - enum: [ ahb_ck0, ahb_ck1 ] > + - enum: [ aux_ck0, aux_ck1 ] > + - enum: [ axi_ck0, axi_ck1 ] > + - enum: [ obff_ck0, obff_ck1 ] > + - enum: [ pipe_ck0, pipe_ck1 ] Move this list to the top level and this should only be 'minItems: 6' here. > + > + reset: false > + > + reset-names: false > + > + phys: false > + > + phy-names: false > + > + required: > + - power-domains > + > + - if: > + properties: > + compatible: > + const: mediatek,mt7629-pcie > + then: > + properties: > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - enum: [ port0, port1 ] > + > + clocks: > + minItems: 6 > + maxItems: 6 > + > + clock-names: > + items: > + - enum: [ sys_ck0, sys_ck1 ] > + - enum: [ ahb_ck0, ahb_ck1 ] > + - enum: [ aux_ck0, aux_ck1 ] > + - enum: [ axi_ck0, axi_ck1 ] > + - enum: [ obff_ck0, obff_ck1 ] > + - enum: [ pipe_ck0, pipe_ck1 ] > + > + reset: false > + > + reset-names: false > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - enum: [ pcie-phy0, pcie-phy1 ] > + > + required: > + - power-domains > + > + - if: > + properties: > + compatible: > + contains: > + const: airoha,en7523-pcie > + then: > + properties: > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - enum: [ port0, port1 ] > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - enum: [ sys_ck0, sys_ck1 ] > + > + reset: false > + > + reset-names: false > + > + phys: false > + > + phy-names: false > + > + power-domain: false > + > +unevaluatedProperties: false > + > +examples: > + # MT2712 > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/phy/phy.h> > + > + soc_1 { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie@112ff000 { > + compatible = "mediatek,mt2712-pcie"; > + device_type = "pci"; > + reg = <0 0x112ff000 0 0x1000>; > + reg-names = "port1"; > + linux,pci-domain = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pcie_irq"; > + clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ > + <&pericfg>; /* CLK_PERI_PCIE1 */ > + clock-names = "sys_ck1", "ahb_ck1"; > + phys = <&u3port1 PHY_TYPE_PCIE>; > + phy-names = "pcie-phy1"; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc1 0>, > + <0 0 0 2 &pcie_intc1 1>, > + <0 0 0 3 &pcie_intc1 2>, > + <0 0 0 4 &pcie_intc1 3>; > + pcie_intc1: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + > + pcie@11700000 { > + compatible = "mediatek,mt2712-pcie"; > + device_type = "pci"; > + reg = <0 0x11700000 0 0x1000>; > + reg-names = "port0"; > + linux,pci-domain = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "pcie_irq"; > + clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ > + <&pericfg>; /* CLK_PERI_PCIE0 */ > + clock-names = "sys_ck0", "ahb_ck0"; > + phys = <&u3port0 PHY_TYPE_PCIE>; > + phy-names = "pcie-phy0"; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc0 0>, > + <0 0 0 2 &pcie_intc0 1>, > + <0 0 0 3 &pcie_intc0 2>, > + <0 0 0 4 &pcie_intc0 3>; > + pcie_intc0: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + # MT7622 > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mt7622-power.h> > + > + soc_2 { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie@1a143000 { > + compatible = "mediatek,mt7622-pcie"; > + device_type = "pci"; > + reg = <0 0x1a143000 0 0x1000>; > + reg-names = "port0"; > + linux,pci-domain = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; > + interrupt-names = "pcie_irq"; > + clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ > + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ > + <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ > + <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ > + <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ > + <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ > + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", > + "axi_ck0", "obff_ck0", "pipe_ck0"; > + > + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc0_1 0>, > + <0 0 0 2 &pcie_intc0_1 1>, > + <0 0 0 3 &pcie_intc0_1 2>, > + <0 0 0 4 &pcie_intc0_1 3>; > + pcie_intc0_1: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + > + pcie@1a145000 { > + compatible = "mediatek,mt7622-pcie"; > + device_type = "pci"; > + reg = <0 0x1a145000 0 0x1000>; > + reg-names = "port1"; > + linux,pci-domain = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + interrupt-names = "pcie_irq"; > + clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ > + /* designer has connect RC1 with p0_ahb clock */ > + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ > + <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ > + <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ > + <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ > + <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ > + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", > + "axi_ck1", "obff_ck1", "pipe_ck1"; > + > + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc1_1 0>, > + <0 0 0 2 &pcie_intc1_1 1>, > + <0 0 0 3 &pcie_intc1_1 2>, > + <0 0 0 4 &pcie_intc1_1 3>; > + pcie_intc1_1: interrupt-controller { > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > -- > 2.51.0 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 3/4] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 2025-09-25 16:23 [PATCH v3 0/4] PCI: mediatek: add support AN7583 + YAML rework Christian Marangi 2025-09-25 16:23 ` [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 Christian Marangi 2025-09-25 16:23 ` [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema Christian Marangi @ 2025-09-25 16:23 ` Christian Marangi 2025-09-25 16:23 ` [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Christian Marangi 3 siblings, 0 replies; 12+ messages in thread From: Christian Marangi @ 2025-09-25 16:23 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Christian Marangi, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- .../bindings/pci/mediatek-pcie.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml index e3afedb77a01..46000049a6c5 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - airoha,an7583-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -61,6 +62,17 @@ properties: power-domains: maxItems: 1 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 @@ -96,6 +108,45 @@ required: allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + compatible: + const: airoha,an7583-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + const: port1 + + clocks: + maxItems: 1 + + clock-names: + const: sys_ck1 + + reset: + maxItems: 1 + + reset-names: + const: pcie-rst1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy1 + + power-domain: false + + required: + - resets + - reset-names + - phys + - phy-names + - mediatek,pbus-csr + - if: properties: compatible: @@ -131,6 +182,8 @@ allOf: power-domains: false + mediatek,pbus-csr: false + required: - phys - phy-names @@ -169,6 +222,8 @@ allOf: phy-names: false + mediatek,pbus-csr: false + required: - power-domains @@ -209,6 +264,8 @@ allOf: items: - enum: [ pcie-phy0, pcie-phy1 ] + mediatek,pbus-csr: false + required: - power-domains @@ -243,6 +300,8 @@ allOf: power-domain: false + mediatek,pbus-csr: false + unevaluatedProperties: false examples: @@ -402,3 +461,54 @@ examples: }; }; }; + + # AN7583 + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/en7523-clk.h> + + soc_3 { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1fa92000 { + compatible = "airoha,an7583-pcie"; + device_type = "pci"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + + reg = <0x0 0x1fa92000 0x0 0x1670>; + reg-names = "port1"; + + clocks = <&scuclk EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + + phys = <&pciephy>; + phy-names = "pcie-phy1"; + + ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>; + + resets = <&scuclk>; /* AN7583_PCIE1_RST */ + reset-names = "pcie-rst1"; + + mediatek,pbus-csr = <&pbus_csr 0x8 0xc>; + + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1_4: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC 2025-09-25 16:23 [PATCH v3 0/4] PCI: mediatek: add support AN7583 + YAML rework Christian Marangi ` (2 preceding siblings ...) 2025-09-25 16:23 ` [PATCH v3 3/4] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Christian Marangi @ 2025-09-25 16:23 ` Christian Marangi 2025-09-26 20:53 ` Bjorn Helgaas ` (2 more replies) 3 siblings, 3 replies; 12+ messages in thread From: Christian Marangi @ 2025-09-25 16:23 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Christian Marangi, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream Add support for the second PCIe line present on Airoha AN7583 SoC. This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 also require workaround for the reset signals. Introduce a new bool to skip having to reset signals and also introduce some additional logic to configure the PBUS registers required for Airoha SoC. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- drivers/pci/controller/pcie-mediatek.c | 85 +++++++++++++++++++------- 1 file changed, 63 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 24cc30a2ab6c..640d1f1a6478 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -147,6 +147,7 @@ struct mtk_pcie_port; * @need_fix_class_id: whether this host's class ID needed to be fixed or not * @need_fix_device_id: whether this host's device ID needed to be fixed or not * @no_msi: Bridge has no MSI support, and relies on an external block + * @skip_pcie_rstb: Skip calling RSTB bits on PCIe probe * @device_id: device ID which this host need to be fixed * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions @@ -156,6 +157,7 @@ struct mtk_pcie_soc { bool need_fix_class_id; bool need_fix_device_id; bool no_msi; + bool skip_pcie_rstb; unsigned int device_id; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); @@ -679,28 +681,30 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); } - /* Assert all reset signals */ - writel(0, port->base + PCIE_RST_CTRL); - - /* - * Enable PCIe link down reset, if link status changed from link up to - * link down, this will reset MAC control registers and configuration - * space. - */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); - - /* - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should - * be delayed 100ms (TPVPERL) for the power and clock to become stable. - */ - msleep(100); - - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val = readl(port->base + PCIE_RST_CTRL); - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | - PCIE_MAC_SRSTB | PCIE_CRSTB; - writel(val, port->base + PCIE_RST_CTRL); + if (!soc->skip_pcie_rstb) { + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from link up to + * link down, this will reset MAC control registers and configuration + * space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should + * be delayed 100ms (TPVPERL) for the power and clock to become stable. + */ + msleep(100); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val = readl(port->base + PCIE_RST_CTRL); + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + } /* Set up vendor ID and class code */ if (soc->need_fix_class_id) { @@ -1105,6 +1109,33 @@ static int mtk_pcie_probe(struct platform_device *pdev) if (err) goto put_resources; + if (device_is_compatible(dev, "airoha,an7583-pcie")) { + struct resource_entry *entry; + struct regmap *pbus_regmap; + resource_size_t addr; + u32 args[2], size; + + /* + * Configure PBus base address and base address mask to allow the + * hw to detect if a given address is accessible on PCIe controller. + */ + pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr = entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size = lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + } + return 0; put_resources: @@ -1205,6 +1236,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { .setup_irq = mtk_pcie_setup_irq, }; +static const struct mtk_pcie_soc mtk_pcie_soc_an7583 = { + .skip_pcie_rstb = true, + .need_fix_class_id = true, + .need_fix_device_id = false, + .ops = &mtk_pcie_ops_v2, + .startup = mtk_pcie_startup_port_v2, + .setup_irq = mtk_pcie_setup_irq, +}; + static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { .need_fix_class_id = true, .need_fix_device_id = true, @@ -1215,6 +1255,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { }; static const struct of_device_id mtk_pcie_ids[] = { + { .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 }, { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, -- 2.51.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC 2025-09-25 16:23 ` [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Christian Marangi @ 2025-09-26 20:53 ` Bjorn Helgaas 2025-09-26 21:32 ` Rob Herring 2025-09-29 10:12 ` AngeloGioacchino Del Regno 2 siblings, 0 replies; 12+ messages in thread From: Bjorn Helgaas @ 2025-09-26 20:53 UTC (permalink / raw) To: Christian Marangi Cc: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream In subject: PCI: mediatek: Add support for Airoha AN7583 SoC On Thu, Sep 25, 2025 at 06:23:18PM +0200, Christian Marangi wrote: > Add support for the second PCIe line present on Airoha AN7583 SoC. What is a "second PCIe line"? Does this mean a second Root Complex? Or a second Root Port in a Root Complex? I guess maybe it just means this adds support for another variant of the Mediatek IP that is used in Airoha AN7583? > This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 > also require workaround for the reset signals. > > Introduce a new bool to skip having to reset signals and also introduce > some additional logic to configure the PBUS registers required for > Airoha SoC. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > drivers/pci/controller/pcie-mediatek.c | 85 +++++++++++++++++++------- > 1 file changed, 63 insertions(+), 22 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index 24cc30a2ab6c..640d1f1a6478 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -147,6 +147,7 @@ struct mtk_pcie_port; > * @need_fix_class_id: whether this host's class ID needed to be fixed or not > * @need_fix_device_id: whether this host's device ID needed to be fixed or not > * @no_msi: Bridge has no MSI support, and relies on an external block > + * @skip_pcie_rstb: Skip calling RSTB bits on PCIe probe > * @device_id: device ID which this host need to be fixed > * @ops: pointer to configuration access functions > * @startup: pointer to controller setting functions > @@ -156,6 +157,7 @@ struct mtk_pcie_soc { > bool need_fix_class_id; > bool need_fix_device_id; > bool no_msi; > + bool skip_pcie_rstb; > unsigned int device_id; > struct pci_ops *ops; > int (*startup)(struct mtk_pcie_port *port); > @@ -679,28 +681,30 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > } > > - /* Assert all reset signals */ > - writel(0, port->base + PCIE_RST_CTRL); > - > - /* > - * Enable PCIe link down reset, if link status changed from link up to > - * link down, this will reset MAC control registers and configuration > - * space. > - */ > - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > - > - /* > - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > - * be delayed 100ms (TPVPERL) for the power and clock to become stable. > - */ > - msleep(100); > - > - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > - val = readl(port->base + PCIE_RST_CTRL); > - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > - PCIE_MAC_SRSTB | PCIE_CRSTB; > - writel(val, port->base + PCIE_RST_CTRL); > + if (!soc->skip_pcie_rstb) { > + /* Assert all reset signals */ > + writel(0, port->base + PCIE_RST_CTRL); > + > + /* > + * Enable PCIe link down reset, if link status changed from link up to > + * link down, this will reset MAC control registers and configuration > + * space. > + */ > + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > + > + /* > + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > + * be delayed 100ms (TPVPERL) for the power and clock to become stable. Wrap these comments to fit in 80 columns like the rest of the file. You only moved the comment, without updating it, but since you're touching it anyway, it's a chance to add the CEM spec revision, e.g., "PCIe CEM r5.0, sec 2.2" > + */ > + msleep(100); Use PCIE_T_PVPERL_MS if that's what this is. > + > + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > + val = readl(port->base + PCIE_RST_CTRL); > + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > + PCIE_MAC_SRSTB | PCIE_CRSTB; > + writel(val, port->base + PCIE_RST_CTRL); > + } > > /* Set up vendor ID and class code */ > if (soc->need_fix_class_id) { > @@ -1105,6 +1109,33 @@ static int mtk_pcie_probe(struct platform_device *pdev) > if (err) > goto put_resources; > > + if (device_is_compatible(dev, "airoha,an7583-pcie")) { > + struct resource_entry *entry; > + struct regmap *pbus_regmap; > + resource_size_t addr; > + u32 args[2], size; > + > + /* > + * Configure PBus base address and base address mask to allow the > + * hw to detect if a given address is accessible on PCIe controller. Wrap to fit in 80 columns. > + */ > + pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, > + "mediatek,pbus-csr", > + ARRAY_SIZE(args), > + args); > + if (IS_ERR(pbus_regmap)) > + return PTR_ERR(pbus_regmap); > + > + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); > + if (!entry) > + return -ENODEV; > + > + addr = entry->res->start - entry->offset; > + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); > + size = lower_32_bits(resource_size(entry->res)); > + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); > + } > + > return 0; > > put_resources: > @@ -1205,6 +1236,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { > .setup_irq = mtk_pcie_setup_irq, > }; > > +static const struct mtk_pcie_soc mtk_pcie_soc_an7583 = { > + .skip_pcie_rstb = true, > + .need_fix_class_id = true, > + .need_fix_device_id = false, No need to specify "false" items; things are false by default since members not explicitly initialized are set to zero. > + .ops = &mtk_pcie_ops_v2, > + .startup = mtk_pcie_startup_port_v2, > + .setup_irq = mtk_pcie_setup_irq, > +}; > + > static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { > .need_fix_class_id = true, > .need_fix_device_id = true, > @@ -1215,6 +1255,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { > }; > > static const struct of_device_id mtk_pcie_ids[] = { > + { .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 }, > { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, > { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, > { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, > -- > 2.51.0 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC 2025-09-25 16:23 ` [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Christian Marangi 2025-09-26 20:53 ` Bjorn Helgaas @ 2025-09-26 21:32 ` Rob Herring 2025-09-29 10:12 ` AngeloGioacchino Del Regno 2 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2025-09-26 21:32 UTC (permalink / raw) To: Christian Marangi Cc: Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream On Thu, Sep 25, 2025 at 06:23:18PM +0200, Christian Marangi wrote: > Add support for the second PCIe line present on Airoha AN7583 SoC. > > This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 > also require workaround for the reset signals. > > Introduce a new bool to skip having to reset signals and also introduce > some additional logic to configure the PBUS registers required for > Airoha SoC. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > drivers/pci/controller/pcie-mediatek.c | 85 +++++++++++++++++++------- > 1 file changed, 63 insertions(+), 22 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index 24cc30a2ab6c..640d1f1a6478 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -147,6 +147,7 @@ struct mtk_pcie_port; > * @need_fix_class_id: whether this host's class ID needed to be fixed or not > * @need_fix_device_id: whether this host's device ID needed to be fixed or not > * @no_msi: Bridge has no MSI support, and relies on an external block > + * @skip_pcie_rstb: Skip calling RSTB bits on PCIe probe > * @device_id: device ID which this host need to be fixed > * @ops: pointer to configuration access functions > * @startup: pointer to controller setting functions > @@ -156,6 +157,7 @@ struct mtk_pcie_soc { > bool need_fix_class_id; > bool need_fix_device_id; > bool no_msi; > + bool skip_pcie_rstb; > unsigned int device_id; > struct pci_ops *ops; > int (*startup)(struct mtk_pcie_port *port); > @@ -679,28 +681,30 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > } > > - /* Assert all reset signals */ > - writel(0, port->base + PCIE_RST_CTRL); > - > - /* > - * Enable PCIe link down reset, if link status changed from link up to > - * link down, this will reset MAC control registers and configuration > - * space. > - */ > - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > - > - /* > - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > - * be delayed 100ms (TPVPERL) for the power and clock to become stable. > - */ > - msleep(100); > - > - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > - val = readl(port->base + PCIE_RST_CTRL); > - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > - PCIE_MAC_SRSTB | PCIE_CRSTB; > - writel(val, port->base + PCIE_RST_CTRL); > + if (!soc->skip_pcie_rstb) { > + /* Assert all reset signals */ > + writel(0, port->base + PCIE_RST_CTRL); > + > + /* > + * Enable PCIe link down reset, if link status changed from link up to > + * link down, this will reset MAC control registers and configuration > + * space. > + */ > + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > + > + /* > + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > + * be delayed 100ms (TPVPERL) for the power and clock to become stable. > + */ > + msleep(100); > + > + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > + val = readl(port->base + PCIE_RST_CTRL); > + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > + PCIE_MAC_SRSTB | PCIE_CRSTB; > + writel(val, port->base + PCIE_RST_CTRL); > + } > > /* Set up vendor ID and class code */ > if (soc->need_fix_class_id) { > @@ -1105,6 +1109,33 @@ static int mtk_pcie_probe(struct platform_device *pdev) > if (err) > goto put_resources; > > + if (device_is_compatible(dev, "airoha,an7583-pcie")) { This should check some match data flag rather than checking compatible again. Otherwise this becomes device_is_compatible() || device_is_compatible() || device_is_compatible()... Rob ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC 2025-09-25 16:23 ` [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Christian Marangi 2025-09-26 20:53 ` Bjorn Helgaas 2025-09-26 21:32 ` Rob Herring @ 2025-09-29 10:12 ` AngeloGioacchino Del Regno 2 siblings, 0 replies; 12+ messages in thread From: AngeloGioacchino Del Regno @ 2025-09-29 10:12 UTC (permalink / raw) To: Christian Marangi, Ryder Lee, Jianjun Wang, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, upstream Il 25/09/25 18:23, Christian Marangi ha scritto: > Add support for the second PCIe line present on Airoha AN7583 SoC. > > This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 > also require workaround for the reset signals. > > Introduce a new bool to skip having to reset signals and also introduce > some additional logic to configure the PBUS registers required for > Airoha SoC. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-09-29 10:12 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-09-25 16:23 [PATCH v3 0/4] PCI: mediatek: add support AN7583 + YAML rework Christian Marangi 2025-09-25 16:23 ` [PATCH v3 1/4] ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623 Christian Marangi 2025-09-26 20:53 ` Bjorn Helgaas 2025-09-29 10:10 ` AngeloGioacchino Del Regno 2025-09-25 16:23 ` [PATCH v3 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema Christian Marangi 2025-09-26 13:09 ` Rob Herring (Arm) 2025-09-26 21:26 ` Rob Herring 2025-09-25 16:23 ` [PATCH v3 3/4] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Christian Marangi 2025-09-25 16:23 ` [PATCH v3 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Christian Marangi 2025-09-26 20:53 ` Bjorn Helgaas 2025-09-26 21:32 ` Rob Herring 2025-09-29 10:12 ` AngeloGioacchino Del Regno
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).