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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1758832799; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=K8koV1fvjKiqOdvzKlp9HUEyXpsh/bOt/eJh59SuqN0=; b=EhWJg2Q34oGjQWLISNkHlAjeZKU8ZoZbnGKu831ie/uwq2BLWG0FiL6AqpqQhsBcDBTky9 RKbULQY35QcMpFTFyQ8vQzLd1Tx5PeYkKub+sk5w4MTUDLUpcn7dgueKyNcmDWeO72h9Fa 112GLO0OhbLaOZYC8fOY4f9MSLI9YNIzLZpR+h8iiTBnjdxFtfiZIzVeLiifIE4YvuBsjf nG9vyX8QcFikPDUKneE7Hzkrv8QcSo0mQ8mCXvDmosXZK7NPLkEVCwLV8FlK6fkIP1pLWL NeSc0mOg3Z27TzUCgPJB2mPYNcN9yhyhiSvSWQETPCxbo0ZJnSPcL037Tl9lqw== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Boris Brezillon , Conor Dooley , David Airlie , Fabio Estevam , "Jiyu Yang (OSS)" , Krzysztof Kozlowski , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Pengutronix Kernel Team , Philipp Zabel , Rob Herring , Sascha Hauer , Sebastian Reichel , Shawn Guo , Simona Vetter , Steven Price , Thomas Zimmermann , Xianzhong Li , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev Subject: [PATCH v3 2/2] arm64: dts: imx95: Describe Mali G310 GPU Date: Thu, 25 Sep 2025 22:38:31 +0200 Message-ID: <20250925203938.169880-2-marek.vasut@mailbox.org> In-Reply-To: <20250925203938.169880-1-marek.vasut@mailbox.org> References: <20250925203938.169880-1-marek.vasut@mailbox.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-MBO-RS-META: eyft1zef34in9duhjg43mr6n19w4thpg X-MBO-RS-ID: 383f404b87e193c4b86 X-Rspamd-Queue-Id: 4cXlvh5t9Yz9tlt The instance of the GPU populated in i.MX95 is the G310, describe this GPU in the DT. Include dummy GPU voltage regulator and OPP tables. Signed-off-by: Marek Vasut --- Cc: Boris Brezillon Cc: Conor Dooley Cc: David Airlie Cc: Fabio Estevam Cc: Jiyu Yang (OSS) Cc: Krzysztof Kozlowski Cc: Liviu Dudau Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Pengutronix Kernel Team Cc: Philipp Zabel Cc: Rob Herring Cc: Sascha Hauer Cc: Sebastian Reichel Cc: Shawn Guo Cc: Simona Vetter Cc: Steven Price Cc: Thomas Zimmermann Cc: Xianzhong Li Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- V2: - Drop regulator-{always,boot}-on from fixed-gpu-reg regulator - Keep the GPU and GPUMIX always enabled - Switch from fsl, to nxp, vendor prefix - Fix opp_table to opp-table - Describe IMX95_CLK_GPUAPB as coregroup clock - Sort interrupts by their names to match bindings V3: - Drop perf power domain - Drop reset block controller --- arch/arm64/boot/dts/freescale/imx95.dtsi | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 1292677cbe4eb..ad47b7f0d173a 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -250,6 +250,35 @@ dummy: clock-dummy { clock-output-names = "dummy"; }; + gpu_fixed_reg: fixed-gpu-reg { + compatible = "regulator-fixed"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd_gpu"; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-hz-real = /bits/ 64 <500000000>; + opp-microvolt = <920000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-hz-real = /bits/ 64 <800000000>; + opp-microvolt = <920000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-hz-real = /bits/ 64 <1000000000>; + opp-microvolt = <920000>; + }; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -2138,6 +2167,22 @@ netc_emdio: mdio@0,0 { }; }; + gpu: gpu@4d900000 { + compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; + reg = <0 0x4d900000 0 0x480000>; + clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; + clock-names = "core", "coregroup"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + mali-supply = <&gpu_fixed_reg>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&scmi_devpd IMX95_PD_GPU>; + #cooling-cells = <2>; + dynamic-power-coefficient = <1013>; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>; -- 2.51.0