* [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
@ 2025-09-19 14:23 Pankaj Patil
2025-09-22 19:56 ` Rob Herring (Arm)
2025-09-26 21:15 ` Bjorn Helgaas
0 siblings, 2 replies; 3+ messages in thread
From: Pankaj Patil @ 2025-09-19 14:23 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
andersson
Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel
From: Qiang Yu <qiang.yu@oss.qualcomm.com>
On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
the DWC controller present on the X1E80100 platform, but does not have
cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
index 257068a18264..61581ffbfb24 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
@@ -32,10 +32,11 @@ properties:
- const: mhi # MHI registers
clocks:
- minItems: 7
+ minItems: 6
maxItems: 7
clock-names:
+ minItems: 6
items:
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
2025-09-19 14:23 [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller Pankaj Patil
@ 2025-09-22 19:56 ` Rob Herring (Arm)
2025-09-26 21:15 ` Bjorn Helgaas
1 sibling, 0 replies; 3+ messages in thread
From: Rob Herring (Arm) @ 2025-09-22 19:56 UTC (permalink / raw)
To: Pankaj Patil
Cc: lpieralisi, linux-kernel, devicetree, kwilczynski, bhelgaas,
conor+dt, andersson, linux-arm-msm, linux-pci, mani, krzk+dt
On Fri, 19 Sep 2025 19:53:25 +0530, Pankaj Patil wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
> the DWC controller present on the X1E80100 platform, but does not have
> cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
2025-09-19 14:23 [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller Pankaj Patil
2025-09-22 19:56 ` Rob Herring (Arm)
@ 2025-09-26 21:15 ` Bjorn Helgaas
1 sibling, 0 replies; 3+ messages in thread
From: Bjorn Helgaas @ 2025-09-26 21:15 UTC (permalink / raw)
To: Pankaj Patil
Cc: bhelgaas, lpieralisi, kwilczynski, mani, robh, krzk+dt, conor+dt,
andersson, linux-arm-msm, linux-pci, devicetree, linux-kernel
On Fri, Sep 19, 2025 at 07:53:25PM +0530, Pankaj Patil wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
> the DWC controller present on the X1E80100 platform, but does not have
> cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Applied with Rob's ack to pci/dt-binding for v6.18, thanks!
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
> index 257068a18264..61581ffbfb24 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
> @@ -32,10 +32,11 @@ properties:
> - const: mhi # MHI registers
>
> clocks:
> - minItems: 7
> + minItems: 6
> maxItems: 7
>
> clock-names:
> + minItems: 6
> items:
> - const: aux # Auxiliary clock
> - const: cfg # Configuration clock
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-09-19 14:23 [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller Pankaj Patil
2025-09-22 19:56 ` Rob Herring (Arm)
2025-09-26 21:15 ` Bjorn Helgaas
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