From: Qingfang Deng <dqfext@gmail.com>
To: Junhui Liu <junhui.liu@pigmoral.tech>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org
Subject: Re: [PATCH v2 04/11] dt-bindings: timer: Add Anlogic DR1V90 CLINT
Date: Sat, 27 Sep 2025 21:59:12 +0800 [thread overview]
Message-ID: <20250927135912.3327-1-dqfext@gmail.com> (raw)
In-Reply-To: <20250922-dr1v90-basic-dt-v2-4-64d28500cb37@pigmoral.tech>
Hi, Junhui,
On Mon, 22 Sep 2025 20:46:34 +0800, Junhui Liu <junhui.liu@pigmoral.tech> wrote:
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -29,6 +29,7 @@ properties:
> oneOf:
> - items:
> - enum:
> + - anlogic,dr1v90-clint # Anlogic DR1V90
UX900 uses the ACLINT with SSWI. Please use the new ACLINT binding.
Link: https://www.nucleisys.com/upload/files/doc/Nuclei_RISC-V_ISA_Spec.pdf
> - canaan,k210-clint # Canaan Kendryte K210
> - eswin,eic7700-clint # ESWIN EIC7700
> - sifive,fu540-c000-clint # SiFive FU540
>
> --
> 2.51.0
Regards,
Qingfang
next prev parent reply other threads:[~2025-09-27 13:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-22 12:46 [PATCH v2 00/11] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-09-22 12:46 ` [PATCH v2 01/11] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-09-22 12:46 ` [PATCH v2 02/11] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
2025-09-23 19:03 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 03/11] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
2025-09-22 12:46 ` [PATCH v2 04/11] dt-bindings: timer: Add Anlogic DR1V90 CLINT Junhui Liu
2025-09-27 13:59 ` Qingfang Deng [this message]
2025-09-28 3:54 ` Junhui Liu
2025-09-22 12:46 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
2025-09-23 19:06 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 06/11] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
2025-09-22 12:46 ` [PATCH v2 07/11] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
2025-09-23 19:06 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 08/11] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
2025-09-23 19:08 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 09/11] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
2025-09-23 19:08 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 10/11] riscv: defconfig: Enable Anlogic SoC Junhui Liu
2025-09-23 19:08 ` Conor Dooley
2025-09-22 12:46 ` [PATCH v2 11/11] MAINTAINERS: Setup support for Anlogic DR1V90 SoC tree Junhui Liu
2025-09-23 19:09 ` Conor Dooley
2025-09-25 3:06 ` [PATCH v2 00/11] riscv: Add initial support for Anlogic DR1V90 fushan.zeng
2025-09-25 3:49 ` Troy Mitchell
2025-09-25 3:49 ` Krzysztof Kozlowski
2025-09-25 17:09 ` Conor Dooley
2025-09-26 14:38 ` fushan.zeng
2025-09-25 17:22 ` Conor Dooley
2025-09-29 18:46 ` Conor Dooley
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