From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Xianwei Zhao <xianwei.zhao@amlogic.com>,
Chuan Liu <chuan.liu@amlogic.com>
Subject: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
Date: Tue, 30 Sep 2025 17:37:13 +0800 [thread overview]
Message-ID: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> (raw)
This patch series includes changes related to the PLL and peripheral
clocks for both the A4 and A5 SoCs.
The patches for A5 were previously submitted up to V3 by Xianwei.
https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
After friendly coordination, I’ve taken over and continued the
submission as part of this series. The dt-bindings patch retains Rob's
original "Reviewed-by" tag, and I hope this hasn’t caused any
additional confusion.
Both A4 and A5 belong to the Audio series. Judging by their names, one
might assume that A5 is an upgrade to A4, but in fact, A5 was released
a year earlier than A4.
Since there are differences in the PLLs and peripheral clocks between
the A4 and A5 SoCs (especially the PLL), and taking into account factors
such as memory footprint and maintainability, this series does not
attempt to merge the two into a shared driver as was done for
G12A/G12B/SM1.
This patch series includes all related dt-bindings, driver, and dts
changes for the PLLs and peripheral clocks. Following our past convention
for clock-related submissions, the dts changes are placed at the end
and submitted separately. If this ordering makes it harder for
maintainers to review or pick patches, please feel free to point it out.
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
Chuan Liu (19):
dt-bindings: clock: Add Amlogic A4 SCMI clock controller
dt-bindings: clock: Add Amlogic A4 PLL clock controller
dt-bindings: clock: Add Amlogic A4 peripherals clock controller
clk: amlogic: Optimize PLL enable timing
clk: amlogic: Correct l_detect bit control
clk: amlogic: Fix out-of-range PLL frequency setting
clk: amlogic: Add A4 PLL clock controller driver
clk: amlogic: Add A4 clock peripherals controller driver
arm64: dts: amlogic: A4: Add scmi-clk node
arm64: dts: amlogic: A4: Add PLL controller node
arm64: dts: amlogic: A4: Add peripherals clock controller node
dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
dt-bindings: clock: Add Amlogic A5 PLL clock controller
dt-bindings: clock: Add Amlogic A5 peripherals clock controller
clk: amlogic: Add A5 PLL clock controller driver
clk: amlogic: Add A5 clock peripherals controller driver
arm64: dts: amlogic: A5: Add scmi-clk node
arm64: dts: amlogic: A5: Add PLL controller node
arm64: dts: amlogic: A5: Add peripheral clock controller node
.../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
.../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
.../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
.../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
drivers/clk/meson/Kconfig | 53 ++
drivers/clk/meson/Makefile | 4 +
drivers/clk/meson/a1-pll.c | 1 +
drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
drivers/clk/meson/a4-pll.c | 242 ++++++
drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
drivers/clk/meson/a5-pll.c | 476 +++++++++++
drivers/clk/meson/clk-pll.c | 76 +-
drivers/clk/meson/clk-pll.h | 2 +
.../clock/amlogic,a4-peripherals-clkc.h | 129 +++
include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
.../clock/amlogic,a5-peripherals-clkc.h | 132 +++
include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
21 files changed, 3406 insertions(+), 28 deletions(-)
---
base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
Best regards,
--
Chuan Liu <chuan.liu@amlogic.com>
next reply other threads:[~2025-09-30 9:37 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-30 9:37 Chuan Liu via B4 Relay [this message]
2025-09-30 9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
2025-10-09 18:07 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL " Chuan Liu via B4 Relay
2025-10-09 18:04 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals " Chuan Liu via B4 Relay
2025-10-09 18:04 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 04/19] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 05/19] clk: amlogic: Correct l_detect bit control Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 08/19] clk: amlogic: Add A4 clock peripherals " Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
2025-10-07 19:33 ` kernel test robot
2025-10-10 4:21 ` kernel test robot
2025-09-30 9:37 ` [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2025-09-30 9:46 ` Chuan Liu
2025-09-30 9:37 ` [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 16/19] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
2025-09-30 14:39 ` [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Rob Herring (Arm)
2025-10-01 7:45 ` Jerome Brunet
2025-10-09 3:09 ` Chuan Liu
2025-10-09 7:59 ` Jerome Brunet
2025-10-10 2:38 ` Chuan Liu
2025-10-10 2:42 ` Krzysztof Kozlowski
2025-10-10 6:15 ` Chuan Liu
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