From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 674802F7462; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=ReITe6uiwIggL2wR3/h6S9WcX7RI3fTKon+z/2oDFsVwD1dR8m4ieanLCOnLSD+v1qeke0JCrI1lAwuTJJAvoIi36pMoc47vNmZQFS6/+RiwbZwp256IxiXM2UIz1rhhp5AwRkNxfFex0T7NmuwT33+u1AsIOuHYho6vJrxp1lM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=pJfB4TXNmkLx5PsgtIGHnwAF+cA8RL+QoqrxgmDx/EI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZQfq2l86fgTn2/WAgaw3V4+yz5aLijD+XrUA6osI6QlNYJq6VEfxlgWU+NGIFIIMtNgl+T3ABrGT0qfiwh6o/ULCEE4U+Vob3tR5gWcYJNl+gA2cDCgIo/VBuQBNrGLG2vetoGxgY9syOddM09gfQvkVD17tYNYPezfi2jGv5fo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a2r9NKlh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a2r9NKlh" Received: by smtp.kernel.org (Postfix) with ESMTPS id F29BEC113D0; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=pJfB4TXNmkLx5PsgtIGHnwAF+cA8RL+QoqrxgmDx/EI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=a2r9NKlhfwzKXpHhNPH9alTLDX8P8mf1mJxLYbCErn1uedIGo6QkaerYwlJM2TPlL Wuz58pzdiu/Yr5R6d3DDMrprR7qcGGT12h+EOWu9gGsGGYgR71XbEvkWQFLyMm1rOS i0+0fMA2Hen5Hx3uSc0j9oKNm4eKkAQAGN9d+HeKHZh3oBNB9CJ0D8ihiMb3zJlxlT AVEvDs9ywpq60qqZmmqzc2E1kcYpEAxkt6zn2ivivSCJBOB4m7emARuXX0EBMiKjvG NjMfr3ZkTDvD+AH7icDnbXj2FAubaeLJF88Qj+YtTX5RbPn6abuVXPxyYdhEl6nEjf YG6hE49VmNS9A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA9A3CAC5B8; Tue, 30 Sep 2025 09:37:31 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:24 +0800 Subject: [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250930-a4_a5_add_clock_driver-v1-11-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=1947; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=WkZjCGYH9SRZ1p+CbboLb8KN0Yvea30tPFS+Yn032E8=; b=24BHjpOH4gCCvBgh+DjCK5+2l9sJd9v4b8UIh947+UdrksdwZhUuw12uWaJw/27TRTxRo5Ddb KHdpac5OKj9DyJkBJV814kMWQ5dG6ngI/Z2tXLhRKgltH8WEvNX+vCD X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the peripherals clock controller node for A4 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi index aca81e658654..3404358aff58 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { cpus { @@ -83,6 +84,44 @@ scmi_clk: protocol@14 { }; &apb { + clkc_periphs: clock-controller@0 { + compatible = "amlogic,a4-peripherals-clkc"; + reg = <0x0 0x0 0x0 0x20c>; + #clock-cells = <1>; + clocks = <&xtal>, + <&scmi_clk CLKID_OSC>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_GP0_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HIFI_PLL>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_AXI_CLK>, + <&scmi_clk CLKID_SYS_PLL_DIV16>, + <&scmi_clk CLKID_CPU_CLK_DIV16>; + clock-names = "xtal", + "oscin", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "gp0", + "gp1", + "hifi", + "sysclk",s + "axiclk", + "sysplldiv16", + "cpudiv16"; + }; + reset: reset-controller@2000 { compatible = "amlogic,a4-reset", "amlogic,meson-s4-reset"; -- 2.42.0