[PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support

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From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Neil Armstrong <neil.armstrong@linaro.org>,
	 Jerome Brunet <jbrunet@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	 devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
	 linux-arm-kernel@lists.infradead.org,
	 Xianwei Zhao <xianwei.zhao@amlogic.com>,
	Chuan Liu <chuan.liu@amlogic.com>
Subject: [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
Date: Tue, 30 Sep 2025 17:37:25 +0800	[thread overview]
Message-ID: <20250930-a4_a5_add_clock_driver-v1-12-a9acf7951589@amlogic.com> (raw)
In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com>

From: Chuan Liu <chuan.liu@amlogic.com>

Add the SCMI clock controller dt-bindings for the Amlogic A5 SoC family.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
new file mode 100644
index 000000000000..1bf027d0110a
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef __AMLOGIC_A5_SCMI_CLKC_H
+#define __AMLOGIC_A5_SCMI_CLKC_H
+
+#define CLKID_OSC				0
+#define CLKID_SYS_CLK				1
+#define CLKID_AXI_CLK				2
+#define CLKID_CPU_CLK				3
+#define CLKID_DSU_CLK				4
+#define CLKID_GP1_PLL				5
+#define CLKID_FIXED_PLL_DCO			6
+#define CLKID_FIXED_PLL				7
+#define CLKID_ACLKM				8
+#define CLKID_SYS_PLL_DIV16			9
+#define CLKID_CPU_CLK_DIV16			10
+#define CLKID_FCLK_50M_PREDIV			11
+#define CLKID_FCLK_50M_DIV			12
+#define CLKID_FCLK_50M				13
+#define CLKID_FCLK_DIV2_DIV			14
+#define CLKID_FCLK_DIV2				15
+#define CLKID_FCLK_DIV2P5_DIV			16
+#define CLKID_FCLK_DIV2P5			17
+#define CLKID_FCLK_DIV3_DIV			18
+#define CLKID_FCLK_DIV3				19
+#define CLKID_FCLK_DIV4_DIV			20
+#define CLKID_FCLK_DIV4				21
+#define CLKID_FCLK_DIV5_DIV			22
+#define CLKID_FCLK_DIV5				23
+#define CLKID_FCLK_DIV7_DIV			24
+#define CLKID_FCLK_DIV7				25
+#define CLKID_SYS_MMC_PCLK			26
+#define CLKID_SYS_CPU_CTRL			27
+#define CLKID_SYS_IRQ_CTRL			28
+#define CLKID_SYS_GIC				29
+#define CLKID_SYS_BIG_NIC			30
+#define CLKID_AXI_SYS_NIC			31
+#define CLKID_AXI_CPU_DMC			32
+
+#endif /* __AMLOGIC_A5_SCMI_CLKC_H */

-- 
2.42.0

next prev parent reply	other threads:[~2025-09-30  9:37 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-30  9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
2025-10-09 18:07   ` Rob Herring (Arm)
2025-09-30  9:37 ` [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL " Chuan Liu via B4 Relay
2025-10-09 18:04   ` Rob Herring (Arm)
2025-09-30  9:37 ` [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals " Chuan Liu via B4 Relay
2025-10-09 18:04   ` Rob Herring (Arm)
2025-09-30  9:37 ` [PATCH 04/19] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 05/19] clk: amlogic: Correct l_detect bit control Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 08/19] clk: amlogic: Add A4 clock peripherals " Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
2025-10-07 19:33   ` kernel test robot
2025-10-10  4:21   ` kernel test robot
2025-09-30  9:37 ` Chuan Liu via B4 Relay [this message]
2025-09-30  9:37 ` [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2025-09-30  9:46   ` Chuan Liu
2025-09-30  9:37 ` [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 16/19] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
2025-09-30 14:39 ` [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Rob Herring (Arm)
2025-10-01  7:45 ` Jerome Brunet
2025-10-09  3:09   ` Chuan Liu
2025-10-09  7:59     ` Jerome Brunet
2025-10-10  2:38       ` Chuan Liu
2025-10-10  2:42         ` Krzysztof Kozlowski
2025-10-10  6:15           ` Chuan Liu

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:1bf027d0110 )
 OR (
bs:"[PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support" )
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