From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE4222F83C3; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; cv=none; b=UjY+Dyj3zCwdMOPMjV2dNfoPXhTjW9jk4tJjol5Yo9m4K5Dk6ENok+DrxmS/jZ3RFmPqIpAZ3hC5Kgy0e4xXMOq+hqmIg4Bheg22V7CwmGTZwZZP2W0IbPAvvdl+n3N+ujvnBFlNbOu7hyy7UweIUTK85ORo2ab9gCjifH+rljk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759225052; c=relaxed/simple; bh=GhazWRbsOSZcBLYhB/FQbhXm3/61sthie18NPBjHd0g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RjnNhrcoFqqImH50TmR9zFR0+bmIhlmP0rRHduXKyADif0xKTmvaCEtoTcghORUfUQrc5vh3pnNh6xkKHzH0cEdRidtPtuYqm53MJ5achaEEaJDBkK9BnXisRILpsphXlBBZIkTxOqJ7DGITM6tFrx567QHhgsykWA/VabcSs2Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qCpPidns; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qCpPidns" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8DB8DC2BCB0; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759225052; bh=GhazWRbsOSZcBLYhB/FQbhXm3/61sthie18NPBjHd0g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qCpPidns8gn/ylXUskUqdeKTTDpZdsjVzfg7KuSY9msPWwcCeN+Sh3AW4TrNPv1eq Thr4/au1PgLNQsHbtQyOKfz7fBFdu2DUagoip9SYKa7i9KBuuPIKx51Myf4x0qYQKG k8IgUM2rO+vfaau406VBs2hRUfNHsEzf1AGjrm8P5nh4ukeTbgBZUkuC7NLyTLOtVY qm3yHwzjobe4BJCg9WjJhDqCVW7Sloqr+fpL7DTRZ/QUw5QtOYxrCuH4Tz/cBFHi4X 03XgM5t0Wk+2FtPonQf/8mt8BI48yHRr2ahyP6MlnbcTXIJdd2Y8Hm/XBZMrkOQJt0 DPGLi+dRznQRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75BE4CCA470; Tue, 30 Sep 2025 09:37:32 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 30 Sep 2025 17:37:32 +0800 Subject: [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock controller node Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250930-a4_a5_add_clock_driver-v1-19-a9acf7951589@amlogic.com> References: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao , Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759225047; l=2041; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=819hwcypvLPkK6zGwB1cqKbMQOi/dUvVkIknKgOKBPA=; b=Yxou6e6o7eYaQX7ea8PxyQS46pJ+jtcK7m1onlU0UwXsX3ttMyz3/Ts2jBPl6HRVxH7dcdASr d+p/EnVQbr/DBmqr7SkjrupsjApzN85QilFbyXdufDKtY5IGcEaCJDv X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add peripheral clock controller node for A5 SoC family. Signed-off-by: Chuan Liu --- arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 43 +++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi index 89f7b5ff4ea3..406cd52a6474 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { cpus { @@ -83,6 +84,48 @@ scmi_clk: protocol@14 { }; &apb { + clkc_periphs: clock-controller@0 { + compatible = "amlogic,a5-peripherals-clkc"; + reg = <0x0 0x0 0x0 0x224>; + #clock-cells = <1>; + clocks = <&xtal>, + <&scmi_clk CLKID_OSC>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_GP0_PLL>, + <&scmi_clk CLKID_GP1_PLL>, + <&clkc_pll CLKID_HIFI_PLL>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_AXI_CLK>, + <&scmi_clk CLKID_SYS_PLL_DIV16>, + <&scmi_clk CLKID_CPU_CLK_DIV16>; + clock-names = "xtal", + "oscin", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "mpll2", + "mpll3", + "gp0", + "gp1", + "hifi", + "sysclk", + "axiclk", + "sysplldiv16", + "cpudiv16"; + }; + reset: reset-controller@2000 { compatible = "amlogic,a5-reset", "amlogic,meson-s4-reset"; -- 2.42.0