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From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Neil Armstrong <neil.armstrong@linaro.org>,
	 Jerome Brunet <jbrunet@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	 devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
	 linux-arm-kernel@lists.infradead.org,
	 Xianwei Zhao <xianwei.zhao@amlogic.com>,
	Chuan Liu <chuan.liu@amlogic.com>
Subject: [PATCH 05/19] clk: amlogic: Correct l_detect bit control
Date: Tue, 30 Sep 2025 17:37:18 +0800	[thread overview]
Message-ID: <20250930-a4_a5_add_clock_driver-v1-5-a9acf7951589@amlogic.com> (raw)
In-Reply-To: <20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com>

From: Chuan Liu <chuan.liu@amlogic.com>

l_detect controls the enable/disable of the PLL lock-detect module.

For A1, the l_detect signal is active-low:
0 -> Enable lock-detect module;
1 -> Disable lock-detect module.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/clk/meson/a1-pll.c  |  1 +
 drivers/clk/meson/clk-pll.c | 16 ++++++++++++----
 drivers/clk/meson/clk-pll.h |  2 ++
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index 1f82e9c7c14e..bfe559c71402 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -137,6 +137,7 @@ static struct clk_regmap a1_hifi_pll = {
 		.range = &a1_hifi_pll_range,
 		.init_regs = a1_hifi_pll_init_regs,
 		.init_count = ARRAY_SIZE(a1_hifi_pll_init_regs),
+		.flags = CLK_MESON_PLL_L_DETECT_N
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hifi_pll",
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 8bddd44d4738..c1e4c5710015 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -384,8 +384,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
 		meson_parm_write(clk->map, &pll->rst, 1);
 
 	/* Disable the PLL lock-detect module */
-	if (MESON_PARM_APPLICABLE(&pll->l_detect))
-		meson_parm_write(clk->map, &pll->l_detect, 1);
+	if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
+		if (pll->flags & CLK_MESON_PLL_L_DETECT_N)
+			meson_parm_write(clk->map, &pll->l_detect, 1);
+		else
+			meson_parm_write(clk->map, &pll->l_detect, 0);
+	}
 
 	/* Enable the pll */
 	meson_parm_write(clk->map, &pll->en, 1);
@@ -413,8 +417,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
 	udelay(20);
 
 	/* Enable the lock-detect module */
-	if (MESON_PARM_APPLICABLE(&pll->l_detect))
-		meson_parm_write(clk->map, &pll->l_detect, 0);
+	if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
+		if (pll->flags & CLK_MESON_PLL_L_DETECT_N)
+			meson_parm_write(clk->map, &pll->l_detect, 0);
+		else
+			meson_parm_write(clk->map, &pll->l_detect, 1);
+	}
 
 	if (meson_clk_pll_wait_lock(hw)) {
 		/* disable PLL when PLL lock failed. */
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 949157fb7bf5..83295a24721f 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -29,6 +29,8 @@ struct pll_mult_range {
 
 #define CLK_MESON_PLL_ROUND_CLOSEST	BIT(0)
 #define CLK_MESON_PLL_NOINIT_ENABLED	BIT(1)
+/* l_detect signal is active-low */
+#define CLK_MESON_PLL_L_DETECT_N	BIT(2)
 
 struct meson_clk_pll_data {
 	struct parm en;

-- 
2.42.0



  parent reply	other threads:[~2025-09-30  9:37 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-30  9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
2025-10-09 18:07   ` Rob Herring (Arm)
2025-09-30  9:37 ` [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL " Chuan Liu via B4 Relay
2025-10-09 18:04   ` Rob Herring (Arm)
2025-09-30  9:37 ` [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals " Chuan Liu via B4 Relay
2025-10-09 18:04   ` Rob Herring (Arm)
2025-09-30  9:37 ` [PATCH 04/19] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
2025-09-30  9:37 ` Chuan Liu via B4 Relay [this message]
2025-09-30  9:37 ` [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 08/19] clk: amlogic: Add A4 clock peripherals " Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
2025-10-07 19:33   ` kernel test robot
2025-10-10  4:21   ` kernel test robot
2025-09-30  9:37 ` [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2025-09-30  9:46   ` Chuan Liu
2025-09-30  9:37 ` [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 16/19] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30  9:37 ` [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
2025-09-30 14:39 ` [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Rob Herring (Arm)
2025-10-01  7:45 ` Jerome Brunet
2025-10-09  3:09   ` Chuan Liu
2025-10-09  7:59     ` Jerome Brunet
2025-10-10  2:38       ` Chuan Liu
2025-10-10  2:42         ` Krzysztof Kozlowski
2025-10-10  6:15           ` Chuan Liu

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