[PATCH 0/3] spi-cadence: support transmission with bits_per_word

[Jun Guo <jun.guo@cixtech.com>]

The Cadence SPI IP supports configurable FIFO data widths during
integration. On some SoCs, the FIFO data width is designed to be 16 or
32 bits at the chip design stage. However, the current driver only
supports communication with an 8-bit FIFO data width. Therefore, these
patches are added to enable the driver to support communication with
16-bit and 32-bit FIFO data widths.

This series introduces the following enhancements for Cadence SPI
controller support on arm64 platforms:

Patch 1: Document the 'fifo-width' property as optional in
spi-cadence device tree bindings.
Patch 2: Enhance the SPI Cadence driver to support data transmission
with bits_per_word values of 16 and 32.
Patch 3: Add a new 'fifo-width' configuration property to Cadence
SPI node in the CIX device tree.

The CIX Sky1 SPI supported patch is added:
https://lore.kernel.org/all/20250919013118.853078-1-jun.guo@cixtech.com/

This series:
- Documents the new property usage.
- Enables 16/32 bits per word in the driver for broader hardware
  compatibility.
- Makes fifo-width configurable via DT.

The patches have been tested on CIX SKY1 platform.

Jun Guo (3):
  dt-bindings: spi: spi-cadence: document optional fifo-width DT
    property
  spi: spi-cadence: supports transmission with bits_per_word of 16 and
    32
  arm64: dts: cix: add the fifo-width configuration field for cadence
    SPI

 .../devicetree/bindings/spi/spi-cadence.yaml  |  11 ++
 arch/arm64/boot/dts/cix/sky1.dtsi             |   2 +
 drivers/spi/spi-cadence.c                     | 125 ++++++++++++++++--
 3 files changed, 125 insertions(+), 13 deletions(-)

-- 
2.34.1