[PATCH 3/3] arm64: dts: cix: add the fifo-width configuration field for cadence SPI

[Jun Guo <jun.guo@cixtech.com>]

The fifo-width is the FIFO data width (in bits) for the Cadence IP.
Configure it according to the FIFO data width set during the chip design.
The current design of sky1 has a FIFO data width of 32 bits.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index ea324336bf34..c526b92d62ff 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -271,6 +271,7 @@ spi0: spi@4090000 {
 				 <&scmi_clk CLK_TREE_FCH_SPI0_APB>;
 			clock-names = "ref_clk", "pclk";
 			interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
+			fifo-width = <32>;
 			status = "disabled";
 		};
 
@@ -281,6 +282,7 @@ spi1: spi@40a0000 {
 				 <&scmi_clk CLK_TREE_FCH_SPI1_APB>;
 			clock-names = "ref_clk", "pclk";
 			interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
+			fifo-width = <32>;
 			status = "disabled";
 		};
 
-- 
2.34.1