From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 486FF27B354; Wed, 1 Oct 2025 15:42:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759333354; cv=none; b=n8/JcIRHS+QxKe0+RoStcBJhVZQ403ObyMmf2erebUd1taF2OMwFATAYKlZT4Cmcbrrh5nTZbu38kF4zZ4pQgEcnhniEK2eLvAAePKjyOsq3UBRcQNctBzlkYkXXaTjkDkOIrCp2pUnB9SQBRVxpRHadaG/bvxUOLp4J9nmcIXE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759333354; c=relaxed/simple; bh=IFmXaUEVCdfmu4h7uBdcd60/SgHLRG5fK16lXlhnfi4=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=u7BaxWOllY03V58tR01TplYJo2zFy2yGCKlQNNqN/T6OiIBvqudDPc0DUCxXSArZM1UwWfiFAi1nqEGSOQEh1EjRBlAj6kO9SzUNautmxwtuvFwXrjk83USQ5mNOgyfsYAK+mWtnG0jHdWdvri2BBC32vvojxABzNaShrlqoPnc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=eAoGuViM; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="eAoGuViM" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 787784E40E65; Wed, 1 Oct 2025 15:42:21 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 45EC5606BF; Wed, 1 Oct 2025 15:42:21 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E6375102F1A3E; Wed, 1 Oct 2025 17:42:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1759333340; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=HMmBhCThKM49GDvXBon6ScZQqtxnNu2vGA60ajonRrk=; b=eAoGuViMv3sS/djX+80W2N/Ha4y8f5AGU5UP/SVorMoE++0n7PUkIOEIhAJ3hAUMlMayQ6 IOdTySEdA7fFUHanPA+atTEYIdbylUSKo+TCCmVeoP802o0D0sQ6ZEsUanqPU5oUdUIM83 RJ7WEkk1ls21EfWl3VczG/x7TjlqiqUnTUQ6IL1lt2Ex4ioelt2njhvQfTaeQ8/1hPLRtw YLHBqIRoABDSq86ueI3rRxrc1ghmNYCOKTQeDC14gL46PiObRnjWla5q7noyxMhvS/jg3N jLGGWdTh4gcLW2wLshAmpfSrRqLkDzfjsC6tHMAXNusHQHLrKXvKLXsTnpZ6nA== Date: Wed, 1 Oct 2025 17:42:05 +0200 From: Herve Codina To: Linus Walleij Cc: Thomas Gleixner , Wolfram Sang , Hoan Tran , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: Re: [PATCH v4 7/8] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer Message-ID: <20251001174205.71a08017@bootlin.com> In-Reply-To: References: <20250922152640.154092-1-herve.codina@bootlin.com> <20250922152640.154092-8-herve.codina@bootlin.com> Organization: Bootlin X-Mailer: Claws Mail 4.3.1 (GTK 3.24.43; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 Hi Linus, On Wed, 1 Oct 2025 13:08:57 +0200 Linus Walleij wrote: > Hi Herve, > > thanks for your patch! > > On Mon, Sep 22, 2025 at 5:27 PM Herve Codina (Schneider Electric) > wrote: > > > On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those > > interruption lines are multiplexed by the GPIO Interrupt Multiplexer in > > order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. > > > > The GPIO interrupt multiplexer IP does nothing but select 8 GPIO > > IRQ lines out of the 96 available to wire them to the GIC input lines. > > > > Signed-off-by: Herve Codina (Schneider Electric) > > This looks like some complicated code to reimplement hierarchical > irq domains. > > Can't you just select IRQ_DOMAIN_HIERARCHY and let > the existing infrastructure in GPIOLIB_IRQCHIP handle > this? > > This kind of remapping and handling is exactly what the > .child_to_parent_hwirq() callback in struct gpio_irq_chip > is for. This function can fail if you run out if IRQ lines. > > Inspect drivers/gpio/Kconfig driver that select > IRQ_DOMAIN_HIERARCHY for examples of how to > do this. > > Even if your GPIO driver is not using GPIOLIB_IRQCHIP (in that > case: why not?) I think you still need to use IRQ_DOMAIN_HIERARCHY > for this. > I don't see how IRQ_DOMAIN_HIERARCHY would help. The irq-mux only muxes irq signal without performing any operations usually done by an interrupt controller. That's why I used interrupt-map in the irq-mux. The only information needed by the irq-mux is the interrupt line muxing that needs to be applied. This information is available in the interrupt-map. If we introduce IRQ_DOMAIN_HIERARCHY, either it is done at gpio controller level to route gpio interrupts to GIC interrupts and, in that case, the irq-mux is skipped and cannot apply the muxing. Or it is introduced at irq-mux level and irq-mux need to be an interrupt controller but is component is not an interrupt controller. Maybe I missed some points or I misunderstood the purpose of IRQ_DOMAIN_HIERARCHY. Can you give me some details on how IRQ_DOMAIN_HIERARCHY should be used in my case? Best regards, Hervé