From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4B0D2877E0; Fri, 3 Oct 2025 01:58:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759456738; cv=none; b=M69Xw8z7NcyBuWRPbvWWazgMyNuaNx+DBUEe6I4XSH1O18xWL/qR2CUJuKFUZLBpYluQjhAj3LopWBbmEKGy/QM7BX0fG7zV6TGLzjKtnbD7xTd1xBNUtjnRERYz/vgUOjK1XkWU8/ZqEGs92GMVv8xW1QW4ZZTBfJNJoY3QT/0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759456738; c=relaxed/simple; bh=rxd2tW3cxu9hANKdMas7ibmaedQ1ngBMnrh57Rtat7o=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Tk9VOWKghxGALU/WEMdyLqSqNW9OOv8XsTkFtxl7BtygPkJFUJNlCWIh72AaOKZaRlqvpSUYapqDEXs4A7hnIUAKY1HKXGtd7KHI7A3nDR0pcq30YYpdqnK5EyqikoBq/N1f41dEMHJoJbGza5zYiAMb3cvxZVT7SuHfLHSgxj8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 3 Oct 2025 09:58:45 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 3 Oct 2025 09:58:45 +0800 From: Jammy Huang To: , , , , , , , , , , , Subject: [PATCH v2 0/2] Add video reset to aspeed-clk Date: Fri, 3 Oct 2025 09:58:43 +0800 Message-ID: <20251003015845.2715538-1-jammy_huang@aspeedtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Add missing video reset to aspeed clock controller drivers. v2 changes: - Add patch for drivers/clk/clk-aspeed.c - Update index of ASPEED_RESET_VIDEO Jammy Huang (2): dt-bindings: clock: aspeed: Add VIDEO reset definition clk: aspeed: Add reset for HACE/VIDEO drivers/clk/clk-aspeed.c | 2 ++ include/dt-bindings/clock/aspeed-clock.h | 1 + 2 files changed, 3 insertions(+) base-commit: 7f7072574127c9e971cad83a0274e86f6275c0d5 -- 2.25.1