From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F1FA293B5F; Fri, 3 Oct 2025 01:58:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759456744; cv=none; b=Vhoho0X6U67LbwrTV9TjuyvM7xhGyyJhECOKPpJ1+IJrikX+Gj8pUfaar4qmQelJXvJ87dqp9y3OBNlcpf1A2Qo8dIsUHTdAD6Eb4BV/838YqUQoTkJKWYeRbMm8zpcueb2E1m/7MjEqwHNt2ph7xLcynUixnq98ujGGG+3VW50= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759456744; c=relaxed/simple; bh=gaObcC8/RaGghxraC8wMdNsgeWuSwwVxqyG0kFgPZPQ=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=p4TatxwkfjnBtJRPrjRfIo9Xz3x9VtNVThz+AYMvf6Ucuazo660swKNu5WhwmLEjGSdtEoSVkHaVSo2d7M+NN8nGdt07oTLkRqXcg5QAHZ7E1AmhmNRX3xlADXO85Ff+1kyRCxlQBeOQwLbT0YKmb6RO7yxz1cXs6HadDpq7VLg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 3 Oct 2025 09:58:45 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 3 Oct 2025 09:58:45 +0800 From: Jammy Huang To: , , , , , , , , , , , Subject: [PATCH v2 1/2] dt-bindings: clock: aspeed: Add VIDEO reset definition Date: Fri, 3 Oct 2025 09:58:44 +0800 Message-ID: <20251003015845.2715538-2-jammy_huang@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251003015845.2715538-1-jammy_huang@aspeedtech.com> References: <20251003015845.2715538-1-jammy_huang@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain ASPEED clock controller provides a couple of resets. Add the define of video to allow referring to it. Signed-off-by: Jammy Huang --- v2 changes: - Update index of ASPEED_RESET_VIDEO --- include/dt-bindings/clock/aspeed-clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 06d568382c77..671e5a476eae 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -53,5 +53,6 @@ #define ASPEED_RESET_AHB 8 #define ASPEED_RESET_CRT1 9 #define ASPEED_RESET_HACE 10 +#define ASPEED_RESET_VIDEO 11 #endif -- 2.25.1