* [PATCH 0/2] Add support for Pixel 3 and Pixel 3 XL
@ 2025-10-05 13:16 David Heidelberg via B4 Relay
2025-10-05 13:16 ` [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and " David Heidelberg via B4 Relay
` (2 more replies)
0 siblings, 3 replies; 23+ messages in thread
From: David Heidelberg via B4 Relay @ 2025-10-05 13:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, David Heidelberg,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul, Bjorn Andersson
This adds initial device tree support for the following phones:
- Google Pixel 3 (blueline)
- Google Pixel 3 XL (crosshatch)
Both phone boards use the same identifiers and differ only slightly
in their connected peripherals.
Supported functionality includes:
- Debug UART
- UFS
- Charger
- USB-C (peripheral mode)
- Display (Pixel 3 only)
This is mainly focused to get the base functionality of the board and
being able to use the upstream DTS within Linux and u-boot.
Booting
-------
For older Pixel 3 bootloaders, bootloader-compatible board and MSM IDs are
required for the kernel to boot, so these have been added.
For recent Pixel 3 bootloaders,
a) you want chainloaded proper bootloader (f.e. u-boot),
b) you can also boot kernel when adding back TEXT_OFFSET
(partial revert of 120dc60d).
This series is a beggining of cleaning up and transitioning support from
sdm845 close to mainline tree to the mainline.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
David Heidelberg (2):
Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +-
arch/arm64/boot/dts/qcom/Makefile | 2 +
.../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
.../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
5 files changed, 736 insertions(+), 3 deletions(-)
---
base-commit: e5f0a698b34ed76002dc5cff3804a61c80233a7a
change-id: 20250419-pixel-3-511edc2a4607
Best regards,
--
David Heidelberg <david@ixit.cz>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
2025-10-05 13:16 [PATCH 0/2] Add support for Pixel 3 and Pixel 3 XL David Heidelberg via B4 Relay
@ 2025-10-05 13:16 ` David Heidelberg via B4 Relay
2025-10-05 22:21 ` Dmitry Baryshkov
2025-10-05 13:16 ` [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel " David Heidelberg via B4 Relay
2025-10-05 22:15 ` [PATCH 0/2] " Dmitry Baryshkov
2 siblings, 1 reply; 23+ messages in thread
From: David Heidelberg via B4 Relay @ 2025-10-05 13:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, David Heidelberg
From: David Heidelberg <david@ixit.cz>
Document the bindings for the Pixel 3 and 3 XL.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index ae43b35565808..2190c5b409748 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -976,9 +976,8 @@ properties:
- items:
- enum:
- - google,cheza
- - google,cheza-rev1
- - google,cheza-rev2
+ - google,blueline
+ - google,crosshatch
- lenovo,yoga-c630
- lg,judyln
- lg,judyp
--
2.51.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-05 13:16 [PATCH 0/2] Add support for Pixel 3 and Pixel 3 XL David Heidelberg via B4 Relay
2025-10-05 13:16 ` [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and " David Heidelberg via B4 Relay
@ 2025-10-05 13:16 ` David Heidelberg via B4 Relay
2025-10-05 13:25 ` David Heidelberg
` (2 more replies)
2025-10-05 22:15 ` [PATCH 0/2] " Dmitry Baryshkov
2 siblings, 3 replies; 23+ messages in thread
From: David Heidelberg via B4 Relay @ 2025-10-05 13:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, David Heidelberg,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul, Bjorn Andersson
From: David Heidelberg <david@ixit.cz>
This adds initial device tree support for the following phones:
- Google Pixel 3 (blueline)
- Google Pixel 3 XL (crosshatch)
Both phone boards use the same identifiers and differ only slightly
in their connected peripherals.
Supported functionality includes:
- Debug UART
- UFS
- Charger
- USB-C (peripheral mode)
- Display (Pixel 3 only)
GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
so they are marked as reserved to allow the Pixel 3 to boot.
The rmtfs region is allocated using UIO, making it technically "dynamic."
Its address and size can be read from sysfs:
$ cat /sys/class/uio/uio0/name
/sys/class/uio/uio0/maps/map0/addr
0x00000000f2701000
$ cat /sys/class/uio/uio0/maps/map0/size
0x0000000000200000
Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
side of the rmtfs region to work around an XPU bug that would otherwise
cause erroneous violations when accessing the rmtfs_mem region.
Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Co-developed-by: Casey Connolly <casey@connolly.tech>
Signed-off-by: Casey Connolly <casey@connolly.tech>
Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
Co-developed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
arch/arm64/boot/dts/qcom/Makefile | 2 +
.../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
.../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
4 files changed, 734 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4bfa926b6a085..ba05dc935dc7c 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
new file mode 100644
index 0000000000000..df88982018b9e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "sdm845-google-common.dtsi"
+
+/ {
+ model = "Google Pixel 3";
+ compatible = "google,blueline", "qcom,sdm845";
+
+ battery: battery {
+ compatible = "simple-battery";
+
+ charge-full-design-microamp-hours = <2970000>;
+ voltage-min-design-microvolt = <3600000>;
+ voltage-max-design-microvolt = <4400000>;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* for u-boot */
+ framebuffer: framebuffer@9d400000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
+ width = <1080>;
+ height = <2160>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ reserved-memory {
+ framebuffer_region@9d400000 {
+ no-map;
+ reg = <0 0x9d400000 0 0x02400000>; // FIXME
+ };
+ };
+};
+
+&gmu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ status = "okay";
+ vdda-supply = <&vdda_mipi_dsi0_1p2>;
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+ qcom,te-source = "mdp_vsync_e";
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "lg,sw43408";
+ reg = <0>;
+
+ vddi-supply = <&vreg_l14a_1p88>;
+ vpnl-supply = <&vreg_l28a_3p0>;
+
+ reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+
+ status = "okay";
+};
+
+&pm8998_gpios {
+ panel_pmgpio_pins: panel-pmgpio-active-state {
+ pins = "gpio2", "gpio5";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+};
+
+&tlmm {
+ panel_te_pin: panel-te-state {
+ pins = "gpio12";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ panel_reset_pins: panel-active-state {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ panel_suspend: panel-suspend-state {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
new file mode 100644
index 0000000000000..5015e54aed20c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
@@ -0,0 +1,467 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sdm845.dtsi"
+#include "pm8998.dtsi"
+#include "pmi8998.dtsi"
+
+/delete-node/ &mpss_region;
+/delete-node/ &venus_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &mba_region;
+/delete-node/ &slpi_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &rmtfs_mem;
+
+/ {
+ chassis-type = "handset";
+ qcom,board-id = <0x00021505 0>;
+ qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
+
+ aliases {
+ serial0 = &uart9;
+ serial1 = &uart6;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ mpss_region: memory@8e000000 {
+ reg = <0 0x8e000000 0 0x9800000>;
+ no-map;
+ };
+
+ venus_mem: venus@97800000 {
+ reg = <0 0x97800000 0 0x500000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-mem@97D00000 {
+ reg = <0 0x97D00000 0 0x800000>;
+ no-map;
+ };
+
+ mba_region: mba@98500000 {
+ reg = <0 0x98500000 0 0x200000>;
+ no-map;
+ };
+
+ slpi_mem: slpi@98700000 {
+ reg = <0 0x98700000 0 0x1400000>;
+ no-map;
+ };
+
+ spss_mem: spss@99B00000 {
+ reg = <0 0x99B00000 0 0x100000>;
+ no-map;
+ };
+
+ /* rmtfs lower guard */
+ memory@f2700000 {
+ reg = <0 0xf2700000 0 0x1000>;
+ no-map;
+ };
+
+ rmtfs_mem: memory@f2701000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0 0xf2701000 0 0x200000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
+
+ /* rmtfs upper guard */
+ memory@f2901000 {
+ reg = <0 0xf2901000 0 0x1000>;
+ no-map;
+ };
+ };
+
+ volume-keys {
+ compatible = "gpio-keys";
+ label = "Volume keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&volume_up_gpio>;
+
+ key-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ vreg_s4a_1p8: vreg-s4a-1p8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8998-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-s11-supply = <&vph_pwr>;
+ vdd-s12-supply = <&vph_pwr>;
+ vdd-s13-supply = <&vph_pwr>;
+ vdd-l1-l27-supply = <&vreg_s7a_1p025>;
+ vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
+ vdd-l3-l11-supply = <&vreg_s7a_1p025>;
+ vdd-l4-l5-supply = <&vreg_s7a_1p025>;
+ vdd-l6-supply = <&vph_pwr>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+ vdd-l9-supply = <&vreg_bob>;
+ vdd-l10-l23-l25-supply = <&vreg_bob>;
+ vdd-l13-l19-l21-supply = <&vreg_bob>;
+ vdd-l16-l28-supply = <&vreg_bob>;
+ vdd-l18-l22-supply = <&vreg_bob>;
+ vdd-l20-l24-supply = <&vreg_bob>;
+ vdd-l26-supply = <&vreg_s3a_1p35>;
+ vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s3a_1p35: smps3 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_s5a_2p04: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7a_1p025: smps7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1028000>;
+ };
+
+ vdda_mipi_dsi0_pll:
+ vreg_l1a_0p875: ldo1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-boot-on;
+ };
+
+ vreg_l5a_0p8: ldo5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p95: ldo13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p88: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-boot-on;
+ /*
+ * We can't properly bring the panel back if it gets turned off
+ * so keep it's regulators always on for now.
+ */
+ regulator-always-on;
+ };
+
+ vreg_l17a_1p3: ldo17 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19a_3p3: ldo19 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ /*
+ * The touchscreen needs this to be 3.3v, which is apparently
+ * quite close to the hardware limit for this LDO (3.312v)
+ * It must be kept in high power mode to prevent TS brownouts
+ */
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l20a_2p95: ldo20 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2968000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l21a_2p95: ldo21 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2968000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l24a_3p075: ldo24 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3088000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l25a_3p3: ldo25 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_mipi_dsi0_1p2:
+ vreg_l26a_1p2: ldo26 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-boot-on;
+ };
+
+ vreg_l28a_3p0: ldo28 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ regulator-boot-on;
+ /*
+ * We can't properly bring the panel back if it gets turned off
+ * so keep it's regulators always on for now.
+ */
+ regulator-always-on;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmi8998-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8005-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s3c_0p6: smps3 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&pm8998_gpios {
+ volume_up_gpio: vol-up-active-state {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,drive-strength = <0>;
+ };
+};
+
+&pm8998_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&pmi8998_charger {
+ monitored-battery = <&battery>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qup_uart9_rx {
+ drive-strength = <2>;
+ bias-pull-up;
+};
+
+&qup_uart9_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <81 4>;
+
+ touchscreen_reset: ts-reset-state {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ touchscreen_pins: ts-pins-gpio-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ touchscreen_i2c_pins: qup-i2c2-gpio-state {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart6 {
+ pinctrl-0 = <&qup_uart6_4pin>;
+
+ status = "okay";
+};
+
+&uart9 {
+ label = "LS-UART1";
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+
+ qcom,imp-res-offset-value = <8>;
+ qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
+ qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
+ qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l26a_1p2>;
+ vdda-pll-supply = <&vreg_l1a_0p875>;
+
+ status = "okay";
+};
+
+&usb_2 {
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_2_hsphy {
+ vdd-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+
+ qcom,imp-res-offset-value = <8>;
+ qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
+
+ status = "okay";
+};
+
+&usb_2_qmpphy {
+ vdda-phy-supply = <&vreg_l26a_1p2>;
+ vdda-pll-supply = <&vreg_l1a_0p875>;
+
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l20a_2p95>;
+ vcc-max-microamp = <800000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
new file mode 100644
index 0000000000000..dc9938ffc0ab8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "sdm845-google-common.dtsi"
+
+/ {
+ model = "Google Pixel 3 XL";
+ compatible = "google,crosshatch", "qcom,sdm845";
+
+ battery: battery {
+ compatible = "simple-battery";
+
+ charge-full-design-microamp-hours = <3480000>;
+ voltage-min-design-microvolt = <3600000>;
+ voltage-max-design-microvolt = <4400000>;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* for u-boot */
+ framebuffer: framebuffer@9d400000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
+ width = <1440>;
+ height = <2960>;
+ stride = <(1440 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ reserved-memory {
+ framebuffer_region@9d400000 {
+ no-map;
+ reg = <0 0x9d400000 0 0x02400000>;
+ };
+ };
+};
+
+&gmu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vdda_mipi_dsi0_1p2>;
+
+ status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+ qcom,te-source = "mdp_vsync_e";
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "samsung,s6e3ha8";
+ reg = <0>;
+
+ vci-supply = <&vreg_l28a_3p0>; // downstream
+ vdd3-supply = <&vreg_l28a_3p0>;
+ vddr-supply = <&vreg_l14a_1p88>;
+
+ reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+
+ status = "okay";
+};
+
+&pm8998_gpios {
+ panel_pmgpio_pins: panel-pmgpio-active-state {
+ pins = "gpio2", "gpio5";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+};
+
+&tlmm {
+ se8_spiflash: se8-spiflash-state {
+ pins = "gpio65", "gpio66", "gpio67", "gpio68";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+
+ panel_te_pin: panel-te-state {
+ pins = "gpio12";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ panel_reset_pins: panel-active-state {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ panel_suspend: panel-suspend-state {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-05 13:16 ` [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel " David Heidelberg via B4 Relay
@ 2025-10-05 13:25 ` David Heidelberg
2025-10-05 22:03 ` Dmitry Baryshkov
2025-10-06 12:41 ` Konrad Dybcio
2 siblings, 0 replies; 23+ messages in thread
From: David Heidelberg @ 2025-10-05 13:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Amit Pundir,
Casey Connolly, Joel Selvaraj, Sumit Semwal, Vinod Koul
On 05/10/2025 15:16, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> This adds initial device tree support for the following phones:
>
> - Google Pixel 3 (blueline)
> - Google Pixel 3 XL (crosshatch)
>
> Both phone boards use the same identifiers and differ only slightly
> in their connected peripherals.
>
> Supported functionality includes:
> - Debug UART
> - UFS
> - Charger
> - USB-C (peripheral mode)
> - Display (Pixel 3 only)
>
> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
> so they are marked as reserved to allow the Pixel 3 to boot.
>
> The rmtfs region is allocated using UIO, making it technically "dynamic."
>
> Its address and size can be read from sysfs:
>
> $ cat /sys/class/uio/uio0/name
> /sys/class/uio/uio0/maps/map0/addr
> 0x00000000f2701000
>
> $ cat /sys/class/uio/uio0/maps/map0/size
> 0x0000000000200000
>
> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
> side of the rmtfs region to work around an XPU bug that would otherwise
> cause erroneous violations when accessing the rmtfs_mem region.
>
> Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Co-developed-by: Casey Connolly <casey@connolly.tech>
> Signed-off-by: Casey Connolly <casey@connolly.tech>
> Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
> Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
> Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> Co-developed-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
> .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
> 4 files changed, 734 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 4bfa926b6a085..ba05dc935dc7c 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
>
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> new file mode 100644
> index 0000000000000..df88982018b9e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +#include "sdm845-google-common.dtsi"
> +
> +/ {
> + model = "Google Pixel 3";
> + compatible = "google,blueline", "qcom,sdm845";
> +
> + battery: battery {
> + compatible = "simple-battery";
> +
> + charge-full-design-microamp-hours = <2970000>;
> + voltage-min-design-microvolt = <3600000>;
> + voltage-max-design-microvolt = <4400000>;
> + };
> +
> + chosen {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* for u-boot */
> + framebuffer: framebuffer@9d400000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
> + width = <1080>;
> + height = <2160>;
> + stride = <(1080 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + framebuffer_region@9d400000 {
> + no-map;
> + reg = <0 0x9d400000 0 0x02400000>; // FIXME
> + };
> + };
> +};
> +
> +&gmu {
> + status = "okay";
> +};
> +
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + status = "okay";
> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> + qcom,te-source = "mdp_vsync_e";
> + };
> + };
> + };
> +
> + panel@0 {
> + compatible = "lg,sw43408";
> + reg = <0>;
> +
> + vddi-supply = <&vreg_l14a_1p88>;
> + vpnl-supply = <&vreg_l28a_3p0>;
> +
> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> + vdds-supply = <&vdda_mipi_dsi0_pll>;
> +
> + status = "okay";
> +};
> +
> +&pm8998_gpios {
> + panel_pmgpio_pins: panel-pmgpio-active-state {
> + pins = "gpio2", "gpio5";
> + function = "normal";
> + input-enable;
> + bias-disable;
> + power-source = <0>;
> + };
> +};
> +
> +&tlmm {
> + panel_te_pin: panel-te-state {
> + pins = "gpio12";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + panel_reset_pins: panel-active-state {
> + pins = "gpio6";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + panel_suspend: panel-suspend-state {
> + pins = "gpio6";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
> new file mode 100644
> index 0000000000000..5015e54aed20c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi
> @@ -0,0 +1,467 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/arm/qcom,ids.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +
> +#include "sdm845.dtsi"
> +#include "pm8998.dtsi"
> +#include "pmi8998.dtsi"
> +
> +/delete-node/ &mpss_region;
> +/delete-node/ &venus_mem;
> +/delete-node/ &cdsp_mem;
> +/delete-node/ &mba_region;
> +/delete-node/ &slpi_mem;
> +/delete-node/ &spss_mem;
> +/delete-node/ &rmtfs_mem;
> +
> +/ {
> + chassis-type = "handset";
> + qcom,board-id = <0x00021505 0>;
> + qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
> +
> + aliases {
> + serial0 = &uart9;
> + serial1 = &uart6;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reserved-memory {
> + mpss_region: memory@8e000000 {
> + reg = <0 0x8e000000 0 0x9800000>;
> + no-map;
> + };
> +
> + venus_mem: venus@97800000 {
> + reg = <0 0x97800000 0 0x500000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp-mem@97D00000 {
> + reg = <0 0x97D00000 0 0x800000>;
> + no-map;
> + };
> +
> + mba_region: mba@98500000 {
> + reg = <0 0x98500000 0 0x200000>;
> + no-map;
> + };
> +
> + slpi_mem: slpi@98700000 {
> + reg = <0 0x98700000 0 0x1400000>;
> + no-map;
> + };
> +
> + spss_mem: spss@99B00000 {
> + reg = <0 0x99B00000 0 0x100000>;
> + no-map;
> + };
> +
> + /* rmtfs lower guard */
> + memory@f2700000 {
> + reg = <0 0xf2700000 0 0x1000>;
> + no-map;
> + };
> +
> + rmtfs_mem: memory@f2701000 {
> + compatible = "qcom,rmtfs-mem";
> + reg = <0 0xf2701000 0 0x200000>;
> + no-map;
> +
> + qcom,client-id = <1>;
> + qcom,vmid = <15>;
> + };
> +
> + /* rmtfs upper guard */
> + memory@f2901000 {
> + reg = <0 0xf2901000 0 0x1000>;
> + no-map;
> + };
> + };
> +
> + volume-keys {
> + compatible = "gpio-keys";
> + label = "Volume keys";
> + autorepeat;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&volume_up_gpio>;
> +
> + key-vol-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
> + debounce-interval = <15>;
> + };
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + };
> +
> + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s4a_1p8";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vph_pwr>;
> + };
> +};
> +
> +&apps_rsc {
> + regulators-0 {
> + compatible = "qcom,pm8998-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + vdd-s7-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> + vdd-s9-supply = <&vph_pwr>;
> + vdd-s10-supply = <&vph_pwr>;
> + vdd-s11-supply = <&vph_pwr>;
> + vdd-s12-supply = <&vph_pwr>;
> + vdd-s13-supply = <&vph_pwr>;
> + vdd-l1-l27-supply = <&vreg_s7a_1p025>;
> + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
> + vdd-l3-l11-supply = <&vreg_s7a_1p025>;
> + vdd-l4-l5-supply = <&vreg_s7a_1p025>;
> + vdd-l6-supply = <&vph_pwr>;
> + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
> + vdd-l9-supply = <&vreg_bob>;
> + vdd-l10-l23-l25-supply = <&vreg_bob>;
> + vdd-l13-l19-l21-supply = <&vreg_bob>;
> + vdd-l16-l28-supply = <&vreg_bob>;
> + vdd-l18-l22-supply = <&vreg_bob>;
> + vdd-l20-l24-supply = <&vreg_bob>;
> + vdd-l26-supply = <&vreg_s3a_1p35>;
> + vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
> +
> + vreg_s3a_1p35: smps3 {
> + regulator-min-microvolt = <1352000>;
> + regulator-max-microvolt = <1352000>;
> + };
> +
> + vreg_s5a_2p04: smps5 {
> + regulator-min-microvolt = <1904000>;
> + regulator-max-microvolt = <2040000>;
> + };
> +
> + vreg_s7a_1p025: smps7 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1028000>;
> + };
> +
> + vdda_mipi_dsi0_pll:
> + vreg_l1a_0p875: ldo1 {
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <880000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-boot-on;
> + };
> +
> + vreg_l5a_0p8: ldo5 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l12a_1p8: ldo12 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7a_1p8: ldo7 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l13a_2p95: ldo13 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l14a_1p88: ldo14 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-boot-on;
> + /*
> + * We can't properly bring the panel back if it gets turned off
> + * so keep it's regulators always on for now.
> + */
> + regulator-always-on;
> + };
> +
> + vreg_l17a_1p3: ldo17 {
> + regulator-min-microvolt = <1304000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l19a_3p3: ldo19 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + /*
> + * The touchscreen needs this to be 3.3v, which is apparently
> + * quite close to the hardware limit for this LDO (3.312v)
> + * It must be kept in high power mode to prevent TS brownouts
> + */
> + regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l20a_2p95: ldo20 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2968000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l21a_2p95: ldo21 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2968000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l24a_3p075: ldo24 {
> + regulator-min-microvolt = <3088000>;
> + regulator-max-microvolt = <3088000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l25a_3p3: ldo25 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdda_mipi_dsi0_1p2:
> + vreg_l26a_1p2: ldo26 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-boot-on;
> + };
> +
> + vreg_l28a_3p0: ldo28 {
> + regulator-min-microvolt = <2856000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
> + regulator-boot-on;
> + /*
> + * We can't properly bring the panel back if it gets turned off
> + * so keep it's regulators always on for now.
> + */
> + regulator-always-on;
> + };
> + };
> +
> + regulators-1 {
> + compatible = "qcom,pmi8998-rpmh-regulators";
> + qcom,pmic-id = "b";
> +
> + vdd-bob-supply = <&vph_pwr>;
> +
> + vreg_bob: bob {
> + regulator-min-microvolt = <3312000>;
> + regulator-max-microvolt = <3600000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-bypass;
> + };
> + };
> +
> + regulators-2 {
> + compatible = "qcom,pm8005-rpmh-regulators";
> + qcom,pmic-id = "c";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> +
> + vreg_s3c_0p6: smps3 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <600000>;
> + };
> + };
> +};
> +
> +&gcc {
> + protected-clocks = <GCC_QSPI_CORE_CLK>,
> + <GCC_QSPI_CORE_CLK_SRC>,
> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
> +};
> +
> +&gpi_dma0 {
> + status = "okay";
> +};
> +
> +&pm8998_gpios {
> + volume_up_gpio: vol-up-active-state {
> + pins = "gpio6";
> + function = "normal";
> + input-enable;
> + bias-pull-up;
> + qcom,drive-strength = <0>;
> + };
> +};
> +
> +&pm8998_resin {
> + linux,code = <KEY_VOLUMEDOWN>;
> +
> + status = "okay";
> +};
> +
> +&pmi8998_charger {
> + monitored-battery = <&battery>;
> +
> + status = "okay";
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +&qup_uart9_rx {
> + drive-strength = <2>;
> + bias-pull-up;
> +};
> +
> +&qup_uart9_tx {
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <81 4>;
> +
> + touchscreen_reset: ts-reset-state {
> + pins = "gpio99";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> +
> + touchscreen_pins: ts-pins-gpio-state {
> + pins = "gpio125";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + touchscreen_i2c_pins: qup-i2c2-gpio-state {
> + pins = "gpio27", "gpio28";
> + function = "gpio";
> +
> + drive-strength = <2>;
> + bias-disable;
> + };
> +};
> +
> +&uart6 {
> + pinctrl-0 = <&qup_uart6_4pin>;
> +
> + status = "okay";
> +};
> +
> +&uart9 {
> + label = "LS-UART1";
> +
> + status = "okay";
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "peripheral";
> +};
> +
> +&usb_1_hsphy {
> + vdd-supply = <&vreg_l1a_0p875>;
> + vdda-pll-supply = <&vreg_l12a_1p8>;
> + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
> +
> + qcom,imp-res-offset-value = <8>;
> + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
> + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
> + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
> +
> + status = "okay";
> +};
> +
> +&usb_1_qmpphy {
> + vdda-phy-supply = <&vreg_l26a_1p2>;
> + vdda-pll-supply = <&vreg_l1a_0p875>;
> +
> + status = "okay";
> +};
> +
> +&usb_2 {
> + status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
> +};
> +
> +&usb_2_hsphy {
> + vdd-supply = <&vreg_l1a_0p875>;
> + vdda-pll-supply = <&vreg_l12a_1p8>;
> + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
> +
> + qcom,imp-res-offset-value = <8>;
> + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
> +
> + status = "okay";
> +};
> +
> +&usb_2_qmpphy {
> + vdda-phy-supply = <&vreg_l26a_1p2>;
> + vdda-pll-supply = <&vreg_l1a_0p875>;
> +
> + status = "okay";
> +};
> +
> +&ufs_mem_hc {
> + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
> +
> + vcc-supply = <&vreg_l20a_2p95>;
> + vcc-max-microamp = <800000>;
> +
> + status = "okay";
> +};
> +
> +&ufs_mem_phy {
> + vdda-phy-supply = <&vreg_l1a_0p875>;
> + vdda-pll-supply = <&vreg_l26a_1p2>;
> +
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> new file mode 100644
> index 0000000000000..dc9938ffc0ab8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +#include "sdm845-google-common.dtsi"
> +
> +/ {
> + model = "Google Pixel 3 XL";
> + compatible = "google,crosshatch", "qcom,sdm845";
> +
> + battery: battery {
> + compatible = "simple-battery";
> +
> + charge-full-design-microamp-hours = <3480000>;
> + voltage-min-design-microvolt = <3600000>;
> + voltage-max-design-microvolt = <4400000>;
> + };
> +
> + chosen {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* for u-boot */
> + framebuffer: framebuffer@9d400000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
> + width = <1440>;
> + height = <2960>;
> + stride = <(1440 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + framebuffer_region@9d400000 {
> + no-map;
> + reg = <0 0x9d400000 0 0x02400000>;
> + };
> + };
> +};
> +
> +&gmu {
> + status = "okay";
> +};
> +
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> +
> + status = "okay";
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> + qcom,te-source = "mdp_vsync_e";
> + };
> + };
> + };
> +
> + panel@0 {
> + compatible = "samsung,s6e3ha8";
> + reg = <0>;
> +
> + vci-supply = <&vreg_l28a_3p0>; // downstream
> + vdd3-supply = <&vreg_l28a_3p0>;
> + vddr-supply = <&vreg_l14a_1p88>;
> +
> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
Please, ignore the panel and display related nodes. I accidentally
sneaked the WIP parts somehow into the upstream commit. Only framebuffer
works on the Pixel 3 XL. In next version these nodes will be gone for
the initial inclusion.
David
> +};
> +
> +&mdss_dsi0_out {
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&panel_in>;
> +};
> +
> +&mdss_dsi0_phy {
> + vdds-supply = <&vdda_mipi_dsi0_pll>;
> +
> + status = "okay";
> +};
> +
> +&pm8998_gpios {
> + panel_pmgpio_pins: panel-pmgpio-active-state {
> + pins = "gpio2", "gpio5";
> + function = "normal";
> + input-enable;
> + bias-disable;
> + power-source = <0>;
> + };
> +};
> +
> +&tlmm {
> + se8_spiflash: se8-spiflash-state {
> + pins = "gpio65", "gpio66", "gpio67", "gpio68";
> + function = "gpio";
> + input-enable;
> + bias-disable;
> + };
> +
> + panel_te_pin: panel-te-state {
> + pins = "gpio12";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + panel_reset_pins: panel-active-state {
> + pins = "gpio6";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + panel_suspend: panel-suspend-state {
> + pins = "gpio6";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> +};
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-05 13:16 ` [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel " David Heidelberg via B4 Relay
2025-10-05 13:25 ` David Heidelberg
@ 2025-10-05 22:03 ` Dmitry Baryshkov
2025-10-09 21:20 ` David Heidelberg
` (2 more replies)
2025-10-06 12:41 ` Konrad Dybcio
2 siblings, 3 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-05 22:03 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> This adds initial device tree support for the following phones:
>
> - Google Pixel 3 (blueline)
> - Google Pixel 3 XL (crosshatch)
Great to finally see it being submitted!
>
> Both phone boards use the same identifiers and differ only slightly
> in their connected peripherals.
>
> Supported functionality includes:
> - Debug UART
> - UFS
> - Charger
> - USB-C (peripheral mode)
> - Display (Pixel 3 only)
No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
accessible to download from Google and it can be further repackaged (but
not redistributed). See [1], [2].
The phones share all firmware except for the bdwlan, so hopefully you
can add 'Google/blueline/foo.mbn' to the common file.
[1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
[2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
>
> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
> so they are marked as reserved to allow the Pixel 3 to boot.
>
> The rmtfs region is allocated using UIO, making it technically "dynamic."
>
> Its address and size can be read from sysfs:
>
> $ cat /sys/class/uio/uio0/name
> /sys/class/uio/uio0/maps/map0/addr
> 0x00000000f2701000
>
> $ cat /sys/class/uio/uio0/maps/map0/size
> 0x0000000000200000
>
> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
> side of the rmtfs region to work around an XPU bug that would otherwise
> cause erroneous violations when accessing the rmtfs_mem region.
>
> Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Co-developed-by: Casey Connolly <casey@connolly.tech>
> Signed-off-by: Casey Connolly <casey@connolly.tech>
> Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
> Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
> Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> Co-developed-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
> .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
> 4 files changed, 734 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 4bfa926b6a085..ba05dc935dc7c 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
>
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> new file mode 100644
> index 0000000000000..df88982018b9e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +#include "sdm845-google-common.dtsi"
> +
> +/ {
> + model = "Google Pixel 3";
> + compatible = "google,blueline", "qcom,sdm845";
> +
> + battery: battery {
> + compatible = "simple-battery";
> +
> + charge-full-design-microamp-hours = <2970000>;
> + voltage-min-design-microvolt = <3600000>;
> + voltage-max-design-microvolt = <4400000>;
> + };
> +
> + chosen {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* for u-boot */
> + framebuffer: framebuffer@9d400000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
> + width = <1080>;
> + height = <2160>;
> + stride = <(1080 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + framebuffer_region@9d400000 {
Can't we use cont_splash_mem and let bootloader set it?
> + no-map;
> + reg = <0 0x9d400000 0 0x02400000>; // FIXME
> + };
> + };
> +};
> +
> +&gmu {
> + status = "okay";
> +};
No need to, it's enabled by default.
> +
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + status = "okay";
> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> + qcom,te-source = "mdp_vsync_e";
&mdss_dsi1_out {
remote-endpoint = <&panel_in>;
.....
};
> + };
> + };
> + };
> +
> + panel@0 {
> + compatible = "lg,sw43408";
> + reg = <0>;
> +
> + vddi-supply = <&vreg_l14a_1p88>;
> + vpnl-supply = <&vreg_l28a_3p0>;
> +
> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> + vdds-supply = <&vdda_mipi_dsi0_pll>;
> +
> + status = "okay";
> +};
> +
> +&pm8998_gpios {
> + panel_pmgpio_pins: panel-pmgpio-active-state {
Are these two actually used by the panel? I think they were only used
for sw43402, but not for sw43408.
> + pins = "gpio2", "gpio5";
> + function = "normal";
> + input-enable;
> + bias-disable;
> + power-source = <0>;
> + };
> +};
> +
> +
> + volume-keys {
gpio-keys ?
> + compatible = "gpio-keys";
> + label = "Volume keys";
> + autorepeat;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&volume_up_gpio>;
> +
> + key-vol-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
> + debounce-interval = <15>;
> + };
> + };
> +
> + vph_pwr: vph-pwr-regulator {
Nit: BCP is regulator-foo-bar
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + };
> +
> + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s4a_1p8";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vph_pwr>;
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> new file mode 100644
> index 0000000000000..dc9938ffc0ab8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +#include "sdm845-google-common.dtsi"
> +
> +/ {
> + model = "Google Pixel 3 XL";
> + compatible = "google,crosshatch", "qcom,sdm845";
> +
> + battery: battery {
> + compatible = "simple-battery";
> +
> + charge-full-design-microamp-hours = <3480000>;
> + voltage-min-design-microvolt = <3600000>;
> + voltage-max-design-microvolt = <4400000>;
> + };
> +
> + chosen {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
These are all the same as the -blueline. Please move common options to
the -common.dtsi
> +
> + /* for u-boot */
> + framebuffer: framebuffer@9d400000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
> + width = <1440>;
> + height = <2960>;
> + stride = <(1440 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + framebuffer_region@9d400000 {
> + no-map;
> + reg = <0 0x9d400000 0 0x02400000>;
> + };
> + };
> +};
> +
> +&gmu {
> + status = "okay";
> +};
> +
> +&mdss {
More and more common properties. Please move them to the common file.
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> +
> + status = "okay";
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> + qcom,te-source = "mdp_vsync_e";
> + };
> + };
> + };
> +
> + panel@0 {
> + compatible = "samsung,s6e3ha8";
> + reg = <0>;
> +
> + vci-supply = <&vreg_l28a_3p0>; // downstream
> + vdd3-supply = <&vreg_l28a_3p0>;
> + vddr-supply = <&vreg_l14a_1p88>;
> +
> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
- Why do you need spiflash here?
- I don't think this uses pmgpios too.
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0_out {
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&panel_in>;
> +};
> +
> +&mdss_dsi0_phy {
> + vdds-supply = <&vdda_mipi_dsi0_pll>;
> +
> + status = "okay";
> +};
> +
> +&pm8998_gpios {
> + panel_pmgpio_pins: panel-pmgpio-active-state {
> + pins = "gpio2", "gpio5";
> + function = "normal";
> + input-enable;
> + bias-disable;
> + power-source = <0>;
> + };
> +};
> +
> +&tlmm {
> + se8_spiflash: se8-spiflash-state {
> + pins = "gpio65", "gpio66", "gpio67", "gpio68";
> + function = "gpio";
> + input-enable;
> + bias-disable;
> + };
> +
> + panel_te_pin: panel-te-state {
> + pins = "gpio12";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + panel_reset_pins: panel-active-state {
> + pins = "gpio6";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + panel_suspend: panel-suspend-state {
> + pins = "gpio6";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> +};
>
> --
> 2.51.0
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 0/2] Add support for Pixel 3 and Pixel 3 XL
2025-10-05 13:16 [PATCH 0/2] Add support for Pixel 3 and Pixel 3 XL David Heidelberg via B4 Relay
2025-10-05 13:16 ` [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and " David Heidelberg via B4 Relay
2025-10-05 13:16 ` [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel " David Heidelberg via B4 Relay
@ 2025-10-05 22:15 ` Dmitry Baryshkov
2 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-05 22:15 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On Sun, Oct 05, 2025 at 03:16:27PM +0200, David Heidelberg via B4 Relay wrote:
> This adds initial device tree support for the following phones:
>
> - Google Pixel 3 (blueline)
> - Google Pixel 3 XL (crosshatch)
>
> Both phone boards use the same identifiers and differ only slightly
> in their connected peripherals.
>
> Supported functionality includes:
> - Debug UART
> - UFS
> - Charger
> - USB-C (peripheral mode)
> - Display (Pixel 3 only)
>
> This is mainly focused to get the base functionality of the board and
> being able to use the upstream DTS within Linux and u-boot.
>
> Booting
> -------
> For older Pixel 3 bootloaders, bootloader-compatible board and MSM IDs are
> required for the kernel to boot, so these have been added.
>
> For recent Pixel 3 bootloaders,
> a) you want chainloaded proper bootloader (f.e. u-boot),
> b) you can also boot kernel when adding back TEXT_OFFSET
> (partial revert of 120dc60d).
Maybe I should send a patch fixing the TEXT_OFFSET. Let's see what kind
of reaction will it get.
>
> This series is a beggining of cleaning up and transitioning support from
> sdm845 close to mainline tree to the mainline.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> David Heidelberg (2):
> Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
> arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
>
> Documentation/devicetree/bindings/arm/qcom.yaml | 5 +-
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
> .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
> 5 files changed, 736 insertions(+), 3 deletions(-)
> ---
> base-commit: e5f0a698b34ed76002dc5cff3804a61c80233a7a
> change-id: 20250419-pixel-3-511edc2a4607
>
> Best regards,
> --
> David Heidelberg <david@ixit.cz>
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
2025-10-05 13:16 ` [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and " David Heidelberg via B4 Relay
@ 2025-10-05 22:21 ` Dmitry Baryshkov
2025-10-06 8:09 ` Konrad Dybcio
0 siblings, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-05 22:21 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Sun, Oct 05, 2025 at 03:16:28PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> Document the bindings for the Pixel 3 and 3 XL.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index ae43b35565808..2190c5b409748 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -976,9 +976,8 @@ properties:
>
> - items:
> - enum:
> - - google,cheza
> - - google,cheza-rev1
> - - google,cheza-rev2
Why are you removing those?
> + - google,blueline
> + - google,crosshatch
> - lenovo,yoga-c630
> - lg,judyln
> - lg,judyp
>
> --
> 2.51.0
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
2025-10-05 22:21 ` Dmitry Baryshkov
@ 2025-10-06 8:09 ` Konrad Dybcio
2025-10-06 10:09 ` David Heidelberg
2025-10-06 10:17 ` Dmitry Baryshkov
0 siblings, 2 replies; 23+ messages in thread
From: Konrad Dybcio @ 2025-10-06 8:09 UTC (permalink / raw)
To: Dmitry Baryshkov, david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 10/6/25 12:21 AM, Dmitry Baryshkov wrote:
> On Sun, Oct 05, 2025 at 03:16:28PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> Document the bindings for the Pixel 3 and 3 XL.
>>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 5 ++---
>> 1 file changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index ae43b35565808..2190c5b409748 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -976,9 +976,8 @@ properties:
>>
>> - items:
>> - enum:
>> - - google,cheza
>> - - google,cheza-rev1
>> - - google,cheza-rev2
>
> Why are you removing those?
I removed these a long time ago, the base for this series is 6.17-release
instead of -next :/
Konrad
>
>> + - google,blueline
>> + - google,crosshatch
>> - lenovo,yoga-c630
>> - lg,judyln
>> - lg,judyp
>>
>> --
>> 2.51.0
>>
>>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
2025-10-06 8:09 ` Konrad Dybcio
@ 2025-10-06 10:09 ` David Heidelberg
2025-10-06 10:16 ` Konrad Dybcio
2025-10-06 10:17 ` Dmitry Baryshkov
1 sibling, 1 reply; 23+ messages in thread
From: David Heidelberg @ 2025-10-06 10:09 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 06/10/2025 10:09, Konrad Dybcio wrote:
> On 10/6/25 12:21 AM, Dmitry Baryshkov wrote:
>> On Sun, Oct 05, 2025 at 03:16:28PM +0200, David Heidelberg via B4 Relay wrote:
>>> From: David Heidelberg <david@ixit.cz>
>>>
>>> Document the bindings for the Pixel 3 and 3 XL.
>>>
>>> Signed-off-by: David Heidelberg <david@ixit.cz>
>>> ---
>>> Documentation/devicetree/bindings/arm/qcom.yaml | 5 ++---
>>> 1 file changed, 2 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> index ae43b35565808..2190c5b409748 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> @@ -976,9 +976,8 @@ properties:
>>>
>>> - items:
>>> - enum:
>>> - - google,cheza
>>> - - google,cheza-rev1
>>> - - google,cheza-rev2
>>
>> Why are you removing those?
>
> I removed these a long time ago, the base for this series is 6.17-release
> instead of -next :/
I did purposefully base on 6.17 (and sadly the downgrade from next
brought this mess), because the support for Pixel 3 is a bit fragile and
as I have only Pixel 3 XL at home (not the Pixel 3, which I always
asking someone else to borrow or test for me), I decided to kept 6.17
base so I know it's the state where blueline boots (in case sdm845 or
blueline gets broken in the -next).
If you want me to, I can base the next version on -next.
David
>
> Konrad
>
>>
>>> + - google,blueline
>>> + - google,crosshatch
>>> - lenovo,yoga-c630
>>> - lg,judyln
>>> - lg,judyp
>>>
>>> --
>>> 2.51.0
>>>
>>>
>>
--
David Heidelberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
2025-10-06 10:09 ` David Heidelberg
@ 2025-10-06 10:16 ` Konrad Dybcio
0 siblings, 0 replies; 23+ messages in thread
From: Konrad Dybcio @ 2025-10-06 10:16 UTC (permalink / raw)
To: David Heidelberg, Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 10/6/25 12:09 PM, David Heidelberg wrote:
> On 06/10/2025 10:09, Konrad Dybcio wrote:
>> On 10/6/25 12:21 AM, Dmitry Baryshkov wrote:
>>> On Sun, Oct 05, 2025 at 03:16:28PM +0200, David Heidelberg via B4 Relay wrote:
>>>> From: David Heidelberg <david@ixit.cz>
>>>>
>>>> Document the bindings for the Pixel 3 and 3 XL.
>>>>
>>>> Signed-off-by: David Heidelberg <david@ixit.cz>
>>>> ---
>>>> Documentation/devicetree/bindings/arm/qcom.yaml | 5 ++---
>>>> 1 file changed, 2 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> index ae43b35565808..2190c5b409748 100644
>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> @@ -976,9 +976,8 @@ properties:
>>>> - items:
>>>> - enum:
>>>> - - google,cheza
>>>> - - google,cheza-rev1
>>>> - - google,cheza-rev2
>>>
>>> Why are you removing those?
>>
>> I removed these a long time ago, the base for this series is 6.17-release
>> instead of -next :/
>
> I did purposefully base on 6.17 (and sadly the downgrade from next brought this mess), because the support for Pixel 3 is a bit fragile and as I have only Pixel 3 XL at home (not the Pixel 3, which I always asking someone else to borrow or test for me), I decided to kept 6.17 base so I know it's the state where blueline boots (in case sdm845 or blueline gets broken in the -next).
>
> If you want me to, I can base the next version on -next.
-next currently contains changes from the past ~3 months, which
you're missing out on
You unfortunately have to rebase, or your patches will simply
generate merge conflicts
Konrad
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
2025-10-06 8:09 ` Konrad Dybcio
2025-10-06 10:09 ` David Heidelberg
@ 2025-10-06 10:17 ` Dmitry Baryshkov
1 sibling, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-06 10:17 UTC (permalink / raw)
To: Konrad Dybcio
Cc: david, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On Mon, Oct 06, 2025 at 10:09:58AM +0200, Konrad Dybcio wrote:
> On 10/6/25 12:21 AM, Dmitry Baryshkov wrote:
> > On Sun, Oct 05, 2025 at 03:16:28PM +0200, David Heidelberg via B4 Relay wrote:
> >> From: David Heidelberg <david@ixit.cz>
> >>
> >> Document the bindings for the Pixel 3 and 3 XL.
> >>
> >> Signed-off-by: David Heidelberg <david@ixit.cz>
> >> ---
> >> Documentation/devicetree/bindings/arm/qcom.yaml | 5 ++---
> >> 1 file changed, 2 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> index ae43b35565808..2190c5b409748 100644
> >> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> >> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> >> @@ -976,9 +976,8 @@ properties:
> >>
> >> - items:
> >> - enum:
> >> - - google,cheza
> >> - - google,cheza-rev1
> >> - - google,cheza-rev2
> >
> > Why are you removing those?
>
> I removed these a long time ago, the base for this series is 6.17-release
> instead of -next :/
Anyway, they should not be changed in this patch.
>
> Konrad
>
> >
> >> + - google,blueline
> >> + - google,crosshatch
> >> - lenovo,yoga-c630
> >> - lg,judyln
> >> - lg,judyp
> >>
> >> --
> >> 2.51.0
> >>
> >>
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-05 13:16 ` [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel " David Heidelberg via B4 Relay
2025-10-05 13:25 ` David Heidelberg
2025-10-05 22:03 ` Dmitry Baryshkov
@ 2025-10-06 12:41 ` Konrad Dybcio
2025-10-17 23:32 ` David Heidelberg
2 siblings, 1 reply; 23+ messages in thread
From: Konrad Dybcio @ 2025-10-06 12:41 UTC (permalink / raw)
To: david, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Amit Pundir,
Casey Connolly, Joel Selvaraj, Sumit Semwal, Vinod Koul
On 10/5/25 3:16 PM, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> This adds initial device tree support for the following phones:
>
> - Google Pixel 3 (blueline)
> - Google Pixel 3 XL (crosshatch)
>
> Both phone boards use the same identifiers and differ only slightly
> in their connected peripherals.
>
> Supported functionality includes:
> - Debug UART
> - UFS
> - Charger
> - USB-C (peripheral mode)
> - Display (Pixel 3 only)
>
> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
> so they are marked as reserved to allow the Pixel 3 to boot.
>
> The rmtfs region is allocated using UIO, making it technically "dynamic."
>
> Its address and size can be read from sysfs:
>
> $ cat /sys/class/uio/uio0/name
> /sys/class/uio/uio0/maps/map0/addr
> 0x00000000f2701000
>
> $ cat /sys/class/uio/uio0/maps/map0/size
> 0x0000000000200000
>
> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
> side of the rmtfs region to work around an XPU bug that would otherwise
> cause erroneous violations when accessing the rmtfs_mem region.
[...]
> +&gmu {
> + status = "okay";
> +};
It's already enabled> +
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + status = "okay";
> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
'status' should be last, with a \n before it
> +
> + ports {
> + port@1 {
> + endpoint {
&mdss_dsi0_out {} instead
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> + qcom,te-source = "mdp_vsync_e";
> + };
> + };
> + };
> +
> + panel@0 {
> + compatible = "lg,sw43408";
> + reg = <0>;
> +
> + vddi-supply = <&vreg_l14a_1p88>;
> + vpnl-supply = <&vreg_l28a_3p0>;
> +
> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
property-n
property-names
in this order, please
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> +};
(as mentioned above..)
[...]
> + /* rmtfs lower guard */
> + memory@f2700000 {
> + reg = <0 0xf2700000 0 0x1000>;
> + no-map;
> + };
> +
> + rmtfs_mem: memory@f2701000 {
> + compatible = "qcom,rmtfs-mem";
> + reg = <0 0xf2701000 0 0x200000>;
> + no-map;
> +
> + qcom,client-id = <1>;
> + qcom,vmid = <15>;
> + };
> +
> + /* rmtfs upper guard */
> + memory@f2901000 {
> + reg = <0 0xf2901000 0 0x1000>;
> + no-map;
> + };
qcom,use-guard-pages instead
[...]
> + vreg_l14a_1p88: ldo14 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-boot-on;
> + /*
> + * We can't properly bring the panel back if it gets turned off
> + * so keep it's regulators always on for now.
> + */
> + regulator-always-on;
Sounds like your panel driver is not sequencing things properly
[...]
> +&uart9 {
> + label = "LS-UART1";
This is a 96boards-ism> +
> + status = "okay";
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "peripheral";
Are you sure?
[...]
> +&usb_2 {
> + status = "okay";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
Does the phone actually have something connected to both USB hosts?
Would that be the weasel(?) security chip?
[...]
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> new file mode 100644
> index 0000000000000..dc9938ffc0ab8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/dts-v1/;
> +
> +#include "sdm845-google-common.dtsi"
> +
> +/ {
> + model = "Google Pixel 3 XL";
> + compatible = "google,crosshatch", "qcom,sdm845";
> +
> + battery: battery {
> + compatible = "simple-battery";
> +
> + charge-full-design-microamp-hours = <3480000>;
> + voltage-min-design-microvolt = <3600000>;
> + voltage-max-design-microvolt = <4400000>;
> + };
> +
> + chosen {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* for u-boot */
> + framebuffer: framebuffer@9d400000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
> + width = <1440>;
> + height = <2960>;
> + stride = <(1440 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + framebuffer_region@9d400000 {
> + no-map;
> + reg = <0 0x9d400000 0 0x02400000>;
> + };
> + };
> +};
> +
> +&gmu {
> + status = "okay";
> +};
> +
> +&mdss {
> + status = "okay";
> +};
I'm sure you can push some of this into -common
> +
> +&mdss_dsi0 {
> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> +
> + status = "okay";
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> + qcom,te-source = "mdp_vsync_e";
> + };
> + };
> + };
> +
> + panel@0 {
> + compatible = "samsung,s6e3ha8";
> + reg = <0>;
> +
> + vci-supply = <&vreg_l28a_3p0>; // downstream
which supply should /* upstream */ use then? :(
Konrad
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-05 22:03 ` Dmitry Baryshkov
@ 2025-10-09 21:20 ` David Heidelberg
2025-10-09 21:50 ` Dmitry Baryshkov
2025-10-17 16:59 ` David Heidelberg
2025-10-17 22:23 ` David Heidelberg
2 siblings, 1 reply; 23+ messages in thread
From: David Heidelberg @ 2025-10-09 21:20 UTC (permalink / raw)
To: Dmitry Baryshkov, Konrad Dybcio
Cc: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, Amit Pundir,
Casey Connolly, Joel Selvaraj, Sumit Semwal, Vinod Koul
On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> This adds initial device tree support for the following phones:
>>
>> - Google Pixel 3 (blueline)
>> - Google Pixel 3 XL (crosshatch)
>
> Great to finally see it being submitted!
>
>>
>> Both phone boards use the same identifiers and differ only slightly
>> in their connected peripherals.
>>
>> Supported functionality includes:
>> - Debug UART
>> - UFS
>> - Charger
>> - USB-C (peripheral mode)
>> - Display (Pixel 3 only)
>
> No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> accessible to download from Google and it can be further repackaged (but
> not redistributed). See [1], [2].
Since I didn't have Pixel 3 at hand to test (I sent the series when
attending event where someone had Pixel 3 ;-) ), I was aiming to merge
MVP.. more precisely, Minimal Viable Device-tree (MVD).
Until the end of the month I should have also Pixel 3, so I'll
definitely continue to enable all the mentioned features, but as this
DTB is also needed for u-boot [1], I would prefer to get MVD in ASAP,
mostly because of the fastboot is useless for loading mainline kernel.
[1] https://gitlab.postmarketos.org/tauchgang
Before I'll send the v2, the progress can be tracked in
https://gitlab.com/dhxx/linux/-/commits/b4/pixel-3
Thank you both for the review!
David
>
> The phones share all firmware except for the bdwlan, so hopefully you
> can add 'Google/blueline/foo.mbn' to the common file.
>
> [1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
> [2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
>
>>
>> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
>> so they are marked as reserved to allow the Pixel 3 to boot.
>>
>> The rmtfs region is allocated using UIO, making it technically "dynamic."
>>
>> Its address and size can be read from sysfs:
>>
>> $ cat /sys/class/uio/uio0/name
>> /sys/class/uio/uio0/maps/map0/addr
>> 0x00000000f2701000
>>
>> $ cat /sys/class/uio/uio0/maps/map0/size
>> 0x0000000000200000
>>
>> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
>> side of the rmtfs region to work around an XPU bug that would otherwise
>> cause erroneous violations when accessing the rmtfs_mem region.
>>
>> Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
>> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
>> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Co-developed-by: Casey Connolly <casey@connolly.tech>
>> Signed-off-by: Casey Connolly <casey@connolly.tech>
>> Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
>> Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
>> Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
>> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>> Co-developed-by: Vinod Koul <vkoul@kernel.org>
>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 2 +
>> .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
>> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
>> .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
>> 4 files changed, 734 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 4bfa926b6a085..ba05dc935dc7c 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
>> sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
>>
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> new file mode 100644
>> index 0000000000000..df88982018b9e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> @@ -0,0 +1,128 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> + model = "Google Pixel 3";
>> + compatible = "google,blueline", "qcom,sdm845";
>> +
>> + battery: battery {
>> + compatible = "simple-battery";
>> +
>> + charge-full-design-microamp-hours = <2970000>;
>> + voltage-min-design-microvolt = <3600000>;
>> + voltage-max-design-microvolt = <4400000>;
>> + };
>> +
>> + chosen {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + /* for u-boot */
>> + framebuffer: framebuffer@9d400000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
>> + width = <1080>;
>> + height = <2160>;
>> + stride = <(1080 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + framebuffer_region@9d400000 {
>
> Can't we use cont_splash_mem and let bootloader set it?
>
>> + no-map;
>> + reg = <0 0x9d400000 0 0x02400000>; // FIXME
>> + };
>> + };
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>
> No need to, it's enabled by default.
>
>> +
>> +&mdss {
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + status = "okay";
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>
> &mdss_dsi1_out {
> remote-endpoint = <&panel_in>;
> .....
> };
>
>
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "lg,sw43408";
>> + reg = <0>;
>> +
>> + vddi-supply = <&vreg_l14a_1p88>;
>> + vpnl-supply = <&vreg_l28a_3p0>;
>> +
>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
>> +
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>
> Are these two actually used by the panel? I think they were only used
> for sw43402, but not for sw43408.
>
>> + pins = "gpio2", "gpio5";
>> + function = "normal";
>> + input-enable;
>> + bias-disable;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> +
>> + volume-keys {
>
> gpio-keys ?
>
>> + compatible = "gpio-keys";
>> + label = "Volume keys";
>> + autorepeat;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&volume_up_gpio>;
>> +
>> + key-vol-up {
>> + label = "Volume Up";
>> + linux,code = <KEY_VOLUMEUP>;
>> + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
>> + debounce-interval = <15>;
>> + };
>> + };
>> +
>> + vph_pwr: vph-pwr-regulator {
>
> Nit: BCP is regulator-foo-bar
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> + };
>> +
>> + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg_s4a_1p8";
>> +
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> +
>> + vin-supply = <&vph_pwr>;
>> + };
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> new file mode 100644
>> index 0000000000000..dc9938ffc0ab8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> @@ -0,0 +1,137 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> + model = "Google Pixel 3 XL";
>> + compatible = "google,crosshatch", "qcom,sdm845";
>> +
>> + battery: battery {
>> + compatible = "simple-battery";
>> +
>> + charge-full-design-microamp-hours = <3480000>;
>> + voltage-min-design-microvolt = <3600000>;
>> + voltage-max-design-microvolt = <4400000>;
>> + };
>> +
>> + chosen {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>
> These are all the same as the -blueline. Please move common options to
> the -common.dtsi
>
>> +
>> + /* for u-boot */
>> + framebuffer: framebuffer@9d400000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
>> + width = <1440>;
>> + height = <2960>;
>> + stride = <(1440 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + framebuffer_region@9d400000 {
>> + no-map;
>> + reg = <0 0x9d400000 0 0x02400000>;
>> + };
>> + };
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>> +
>> +&mdss {
>
> More and more common properties. Please move them to the common file.
Sorry about this, the mdss nodes got in by accident, the display driver
for crosshatch is WIP.>
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> + status = "okay";
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "samsung,s6e3ha8";
>> + reg = <0>;
>> +
>> + vci-supply = <&vreg_l28a_3p0>; // downstream
>> + vdd3-supply = <&vreg_l28a_3p0>;
>> + vddr-supply = <&vreg_l14a_1p88>;
>> +
>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
>
> - Why do you need spiflash here?
> - I don't think this uses pmgpios too.
>
>> +
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + data-lanes = <0 1 2 3>;
>> + remote-endpoint = <&panel_in>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>> + pins = "gpio2", "gpio5";
>> + function = "normal";
>> + input-enable;
>> + bias-disable;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> +&tlmm {
>> + se8_spiflash: se8-spiflash-state {
>> + pins = "gpio65", "gpio66", "gpio67", "gpio68";
>> + function = "gpio";
>> + input-enable;
>> + bias-disable;
>> + };
>> +
>> + panel_te_pin: panel-te-state {
>> + pins = "gpio12";
>> + function = "mdp_vsync";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + panel_reset_pins: panel-active-state {
>> + pins = "gpio6";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + panel_suspend: panel-suspend-state {
>> + pins = "gpio6";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> +};
>>
>> --
>> 2.51.0
>>
>>
>
--
David Heidelberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-09 21:20 ` David Heidelberg
@ 2025-10-09 21:50 ` Dmitry Baryshkov
2025-10-10 7:51 ` David Heidelberg
0 siblings, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-09 21:50 UTC (permalink / raw)
To: David Heidelberg
Cc: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On Thu, Oct 09, 2025 at 11:20:49PM +0200, David Heidelberg wrote:
> On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> > On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
> > > From: David Heidelberg <david@ixit.cz>
> > >
> > > This adds initial device tree support for the following phones:
> > >
> > > - Google Pixel 3 (blueline)
> > > - Google Pixel 3 XL (crosshatch)
> >
> > Great to finally see it being submitted!
> >
> > >
> > > Both phone boards use the same identifiers and differ only slightly
> > > in their connected peripherals.
> > >
> > > Supported functionality includes:
> > > - Debug UART
> > > - UFS
> > > - Charger
> > > - USB-C (peripheral mode)
> > > - Display (Pixel 3 only)
> >
> > No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> > accessible to download from Google and it can be further repackaged (but
> > not redistributed). See [1], [2].
>
> Since I didn't have Pixel 3 at hand to test (I sent the series when
> attending event where someone had Pixel 3 ;-) ), I was aiming to merge MVP..
> more precisely, Minimal Viable Device-tree (MVD).
If you have Pix3 XL, you can use it for both. I think the only major
difference is the screen.
> Until the end of the month I should have also Pixel 3, so I'll definitely
> continue to enable all the mentioned features, but as this DTB is also
> needed for u-boot [1], I would prefer to get MVD in ASAP, mostly because of
> the fastboot is useless for loading mainline kernel.
Hmm? I was using onboard ABL and fastboot.
>
> [1] https://gitlab.postmarketos.org/tauchgang
>
> Before I'll send the v2, the progress can be tracked in
> https://gitlab.com/dhxx/linux/-/commits/b4/pixel-3
>
> Thank you both for the review!
> David
>
> >
> > The phones share all firmware except for the bdwlan, so hopefully you
> > can add 'Google/blueline/foo.mbn' to the common file.
> >
> > [1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
> > [2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
> >
> > >
> > > GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
> > > so they are marked as reserved to allow the Pixel 3 to boot.
> > >
> > > The rmtfs region is allocated using UIO, making it technically "dynamic."
> > >
> > > Its address and size can be read from sysfs:
> > >
> > > $ cat /sys/class/uio/uio0/name
> > > /sys/class/uio/uio0/maps/map0/addr
> > > 0x00000000f2701000
> > >
> > > $ cat /sys/class/uio/uio0/maps/map0/size
> > > 0x0000000000200000
> > >
> > > Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
> > > side of the rmtfs region to work around an XPU bug that would otherwise
> > > cause erroneous violations when accessing the rmtfs_mem region.
> > >
> > > Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
> > > Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
> > > Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > Co-developed-by: Casey Connolly <casey@connolly.tech>
> > > Signed-off-by: Casey Connolly <casey@connolly.tech>
> > > Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
> > > Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
> > > Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
> > > Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> > > Co-developed-by: Vinod Koul <vkoul@kernel.org>
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > Signed-off-by: David Heidelberg <david@ixit.cz>
> > > ---
> > > arch/arm64/boot/dts/qcom/Makefile | 2 +
> > > .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
> > > arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
> > > .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
> > > 4 files changed, 734 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> > > index 4bfa926b6a085..ba05dc935dc7c 100644
> > > --- a/arch/arm64/boot/dts/qcom/Makefile
> > > +++ b/arch/arm64/boot/dts/qcom/Makefile
> > > @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> > > sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
> > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
> > > +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
> > > +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
> > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
> > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
> > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> > > new file mode 100644
> > > index 0000000000000..df88982018b9e
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> > > @@ -0,0 +1,128 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "sdm845-google-common.dtsi"
> > > +
> > > +/ {
> > > + model = "Google Pixel 3";
> > > + compatible = "google,blueline", "qcom,sdm845";
> > > +
> > > + battery: battery {
> > > + compatible = "simple-battery";
> > > +
> > > + charge-full-design-microamp-hours = <2970000>;
> > > + voltage-min-design-microvolt = <3600000>;
> > > + voltage-max-design-microvolt = <4400000>;
> > > + };
> > > +
> > > + chosen {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> > > +
> > > + /* for u-boot */
> > > + framebuffer: framebuffer@9d400000 {
> > > + compatible = "simple-framebuffer";
> > > + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
> > > + width = <1080>;
> > > + height = <2160>;
> > > + stride = <(1080 * 4)>;
> > > + format = "a8r8g8b8";
> > > + };
> > > + };
> > > +
> > > + reserved-memory {
> > > + framebuffer_region@9d400000 {
> >
> > Can't we use cont_splash_mem and let bootloader set it?
> >
> > > + no-map;
> > > + reg = <0 0x9d400000 0 0x02400000>; // FIXME
> > > + };
> > > + };
> > > +};
> > > +
> > > +&gmu {
> > > + status = "okay";
> > > +};
> >
> > No need to, it's enabled by default.
> >
> > > +
> > > +&mdss {
> > > + status = "okay";
> > > +};
> > > +
> > > +&mdss_dsi0 {
> > > + status = "okay";
> > > + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> > > +
> > > + ports {
> > > + port@1 {
> > > + endpoint {
> > > + remote-endpoint = <&panel_in>;
> > > + data-lanes = <0 1 2 3>;
> > > + qcom,te-source = "mdp_vsync_e";
> >
> > &mdss_dsi1_out {
> > remote-endpoint = <&panel_in>;
> > .....
> > };
> >
> >
> > > + };
> > > + };
> > > + };
> > > +
> > > + panel@0 {
> > > + compatible = "lg,sw43408";
> > > + reg = <0>;
> > > +
> > > + vddi-supply = <&vreg_l14a_1p88>;
> > > + vpnl-supply = <&vreg_l28a_3p0>;
> > > +
> > > + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> > > +
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
> > > +
> > > + port {
> > > + panel_in: endpoint {
> > > + remote-endpoint = <&mdss_dsi0_out>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&mdss_dsi0_out {
> > > + remote-endpoint = <&panel_in>;
> > > + data-lanes = <0 1 2 3>;
> > > +};
> > > +
> > > +&mdss_dsi0_phy {
> > > + vdds-supply = <&vdda_mipi_dsi0_pll>;
> > > +
> > > + status = "okay";
> > > +};
> > > +
> > > +&pm8998_gpios {
> > > + panel_pmgpio_pins: panel-pmgpio-active-state {
> >
> > Are these two actually used by the panel? I think they were only used
> > for sw43402, but not for sw43408.
> >
> > > + pins = "gpio2", "gpio5";
> > > + function = "normal";
> > > + input-enable;
> > > + bias-disable;
> > > + power-source = <0>;
> > > + };
> > > +};
> > > +
> > > +
> > > + volume-keys {
> >
> > gpio-keys ?
> >
> > > + compatible = "gpio-keys";
> > > + label = "Volume keys";
> > > + autorepeat;
> > > +
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&volume_up_gpio>;
> > > +
> > > + key-vol-up {
> > > + label = "Volume Up";
> > > + linux,code = <KEY_VOLUMEUP>;
> > > + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
> > > + debounce-interval = <15>;
> > > + };
> > > + };
> > > +
> > > + vph_pwr: vph-pwr-regulator {
> >
> > Nit: BCP is regulator-foo-bar
> >
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "vph_pwr";
> > > + regulator-min-microvolt = <3700000>;
> > > + regulator-max-microvolt = <3700000>;
> > > + };
> > > +
> > > + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "vreg_s4a_1p8";
> > > +
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <1800000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > +
> > > + vin-supply = <&vph_pwr>;
> > > + };
> > > +};
> > > +
> > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> > > new file mode 100644
> > > index 0000000000000..dc9938ffc0ab8
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> > > @@ -0,0 +1,137 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "sdm845-google-common.dtsi"
> > > +
> > > +/ {
> > > + model = "Google Pixel 3 XL";
> > > + compatible = "google,crosshatch", "qcom,sdm845";
> > > +
> > > + battery: battery {
> > > + compatible = "simple-battery";
> > > +
> > > + charge-full-design-microamp-hours = <3480000>;
> > > + voltage-min-design-microvolt = <3600000>;
> > > + voltage-max-design-microvolt = <4400000>;
> > > + };
> > > +
> > > + chosen {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> >
> > These are all the same as the -blueline. Please move common options to
> > the -common.dtsi
> >
> > > +
> > > + /* for u-boot */
> > > + framebuffer: framebuffer@9d400000 {
> > > + compatible = "simple-framebuffer";
> > > + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
> > > + width = <1440>;
> > > + height = <2960>;
> > > + stride = <(1440 * 4)>;
> > > + format = "a8r8g8b8";
> > > + };
> > > + };
> > > +
> > > + reserved-memory {
> > > + framebuffer_region@9d400000 {
> > > + no-map;
> > > + reg = <0 0x9d400000 0 0x02400000>;
> > > + };
> > > + };
> > > +};
> > > +
> > > +&gmu {
> > > + status = "okay";
> > > +};
> > > +
> > > +&mdss {
> >
> > More and more common properties. Please move them to the common file.
>
> Sorry about this, the mdss nodes got in by accident, the display driver for
> crosshatch is WIP.>
> > > + status = "okay";
> > > +};
> > > +
> > > +&mdss_dsi0 {
> > > + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> > > +
> > > + status = "okay";
> > > +
> > > + ports {
> > > + port@1 {
> > > + endpoint {
> > > + remote-endpoint = <&panel_in>;
> > > + data-lanes = <0 1 2 3>;
> > > + qcom,te-source = "mdp_vsync_e";
> > > + };
> > > + };
> > > + };
> > > +
> > > + panel@0 {
> > > + compatible = "samsung,s6e3ha8";
> > > + reg = <0>;
> > > +
> > > + vci-supply = <&vreg_l28a_3p0>; // downstream
> > > + vdd3-supply = <&vreg_l28a_3p0>;
> > > + vddr-supply = <&vreg_l14a_1p88>;
> > > +
> > > + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> > > +
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
> >
> > - Why do you need spiflash here?
> > - I don't think this uses pmgpios too.
> >
> > > +
> > > + port {
> > > + panel_in: endpoint {
> > > + remote-endpoint = <&mdss_dsi0_out>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&mdss_dsi0_out {
> > > + data-lanes = <0 1 2 3>;
> > > + remote-endpoint = <&panel_in>;
> > > +};
> > > +
> > > +&mdss_dsi0_phy {
> > > + vdds-supply = <&vdda_mipi_dsi0_pll>;
> > > +
> > > + status = "okay";
> > > +};
> > > +
> > > +&pm8998_gpios {
> > > + panel_pmgpio_pins: panel-pmgpio-active-state {
> > > + pins = "gpio2", "gpio5";
> > > + function = "normal";
> > > + input-enable;
> > > + bias-disable;
> > > + power-source = <0>;
> > > + };
> > > +};
> > > +
> > > +&tlmm {
> > > + se8_spiflash: se8-spiflash-state {
> > > + pins = "gpio65", "gpio66", "gpio67", "gpio68";
> > > + function = "gpio";
> > > + input-enable;
> > > + bias-disable;
> > > + };
> > > +
> > > + panel_te_pin: panel-te-state {
> > > + pins = "gpio12";
> > > + function = "mdp_vsync";
> > > + drive-strength = <2>;
> > > + bias-pull-down;
> > > + };
> > > +
> > > + panel_reset_pins: panel-active-state {
> > > + pins = "gpio6";
> > > + function = "gpio";
> > > + drive-strength = <8>;
> > > + bias-disable;
> > > + };
> > > +
> > > + panel_suspend: panel-suspend-state {
> > > + pins = "gpio6";
> > > + function = "gpio";
> > > + drive-strength = <2>;
> > > + bias-pull-down;
> > > + };
> > > +
> > > +};
> > >
> > > --
> > > 2.51.0
> > >
> > >
> >
>
> --
> David Heidelberg
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-09 21:50 ` Dmitry Baryshkov
@ 2025-10-10 7:51 ` David Heidelberg
2025-10-10 8:17 ` Dmitry Baryshkov
0 siblings, 1 reply; 23+ messages in thread
From: David Heidelberg @ 2025-10-10 7:51 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On 09/10/2025 23:50, Dmitry Baryshkov wrote:
> On Thu, Oct 09, 2025 at 11:20:49PM +0200, David Heidelberg wrote:
>> On 06/10/2025 00:03, Dmitry Baryshkov wrote:
>>> On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
>>>> From: David Heidelberg <david@ixit.cz>
>>>>
>>>> This adds initial device tree support for the following phones:
>>>>
>>>> - Google Pixel 3 (blueline)
>>>> - Google Pixel 3 XL (crosshatch)
>>>
>>> Great to finally see it being submitted!
>>>
>>>>
>>>> Both phone boards use the same identifiers and differ only slightly
>>>> in their connected peripherals.
>>>>
>>>> Supported functionality includes:
>>>> - Debug UART
>>>> - UFS
>>>> - Charger
>>>> - USB-C (peripheral mode)
>>>> - Display (Pixel 3 only)
>>>
>>> No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
>>> accessible to download from Google and it can be further repackaged (but
>>> not redistributed). See [1], [2].
>>
>> Since I didn't have Pixel 3 at hand to test (I sent the series when
>> attending event where someone had Pixel 3 ;-) ), I was aiming to merge MVP..
>> more precisely, Minimal Viable Device-tree (MVD).
>
> If you have Pix3 XL, you can use it for both. I think the only major
> difference is the screen.
Yes, screen and battery.
>
>> Until the end of the month I should have also Pixel 3, so I'll definitely
>> continue to enable all the mentioned features, but as this DTB is also
>> needed for u-boot [1], I would prefer to get MVD in ASAP, mostly because of
>> the fastboot is useless for loading mainline kernel.
>
> Hmm? I was using onboard ABL and fastboot.
Most likely older bootloader, which doesn't insist on TEXT_OFFSET
0x80000 :) I have already new one, so without u-boot that's one extra
revert (which I don't feel that comfortable with on top of mainline).
David>
>>
>> [1] https://gitlab.postmarketos.org/tauchgang
>>
>> Before I'll send the v2, the progress can be tracked in
>> https://gitlab.com/dhxx/linux/-/commits/b4/pixel-3
>>
>> Thank you both for the review!
>> David
>>
>>>
>>> The phones share all firmware except for the bdwlan, so hopefully you
>>> can add 'Google/blueline/foo.mbn' to the common file.
>>>
>>> [1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
>>> [2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
>>>
>>>>
>>>> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
>>>> so they are marked as reserved to allow the Pixel 3 to boot.
>>>>
>>>> The rmtfs region is allocated using UIO, making it technically "dynamic."
>>>>
>>>> Its address and size can be read from sysfs:
>>>>
>>>> $ cat /sys/class/uio/uio0/name
>>>> /sys/class/uio/uio0/maps/map0/addr
>>>> 0x00000000f2701000
>>>>
>>>> $ cat /sys/class/uio/uio0/maps/map0/size
>>>> 0x0000000000200000
>>>>
>>>> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
>>>> side of the rmtfs region to work around an XPU bug that would otherwise
>>>> cause erroneous violations when accessing the rmtfs_mem region.
>>>>
>>>> Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
>>>> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
>>>> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>>>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>>>> Co-developed-by: Casey Connolly <casey@connolly.tech>
>>>> Signed-off-by: Casey Connolly <casey@connolly.tech>
>>>> Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
>>>> Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
>>>> Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
>>>> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>>>> Co-developed-by: Vinod Koul <vkoul@kernel.org>
>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>> Signed-off-by: David Heidelberg <david@ixit.cz>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/Makefile | 2 +
>>>> .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
>>>> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
>>>> .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
>>>> 4 files changed, 734 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>>>> index 4bfa926b6a085..ba05dc935dc7c 100644
>>>> --- a/arch/arm64/boot/dts/qcom/Makefile
>>>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>>>> @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
>>>> sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
>>>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
>>>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
>>>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
>>>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
>>>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
>>>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
>>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>>>> new file mode 100644
>>>> index 0000000000000..df88982018b9e
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>>>> @@ -0,0 +1,128 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +
>>>> +/dts-v1/;
>>>> +
>>>> +#include "sdm845-google-common.dtsi"
>>>> +
>>>> +/ {
>>>> + model = "Google Pixel 3";
>>>> + compatible = "google,blueline", "qcom,sdm845";
>>>> +
>>>> + battery: battery {
>>>> + compatible = "simple-battery";
>>>> +
>>>> + charge-full-design-microamp-hours = <2970000>;
>>>> + voltage-min-design-microvolt = <3600000>;
>>>> + voltage-max-design-microvolt = <4400000>;
>>>> + };
>>>> +
>>>> + chosen {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges;
>>>> +
>>>> + /* for u-boot */
>>>> + framebuffer: framebuffer@9d400000 {
>>>> + compatible = "simple-framebuffer";
>>>> + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
>>>> + width = <1080>;
>>>> + height = <2160>;
>>>> + stride = <(1080 * 4)>;
>>>> + format = "a8r8g8b8";
>>>> + };
>>>> + };
>>>> +
>>>> + reserved-memory {
>>>> + framebuffer_region@9d400000 {
>>>
>>> Can't we use cont_splash_mem and let bootloader set it?
>>>
>>>> + no-map;
>>>> + reg = <0 0x9d400000 0 0x02400000>; // FIXME
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> +&gmu {
>>>> + status = "okay";
>>>> +};
>>>
>>> No need to, it's enabled by default.
>>>
>>>> +
>>>> +&mdss {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&mdss_dsi0 {
>>>> + status = "okay";
>>>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>>>> +
>>>> + ports {
>>>> + port@1 {
>>>> + endpoint {
>>>> + remote-endpoint = <&panel_in>;
>>>> + data-lanes = <0 1 2 3>;
>>>> + qcom,te-source = "mdp_vsync_e";
>>>
>>> &mdss_dsi1_out {
>>> remote-endpoint = <&panel_in>;
>>> .....
>>> };
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + panel@0 {
>>>> + compatible = "lg,sw43408";
>>>> + reg = <0>;
>>>> +
>>>> + vddi-supply = <&vreg_l14a_1p88>;
>>>> + vpnl-supply = <&vreg_l28a_3p0>;
>>>> +
>>>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>>>> +
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
>>>> +
>>>> + port {
>>>> + panel_in: endpoint {
>>>> + remote-endpoint = <&mdss_dsi0_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> +&mdss_dsi0_out {
>>>> + remote-endpoint = <&panel_in>;
>>>> + data-lanes = <0 1 2 3>;
>>>> +};
>>>> +
>>>> +&mdss_dsi0_phy {
>>>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>>>> +
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&pm8998_gpios {
>>>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>>>
>>> Are these two actually used by the panel? I think they were only used
>>> for sw43402, but not for sw43408.
>>>
>>>> + pins = "gpio2", "gpio5";
>>>> + function = "normal";
>>>> + input-enable;
>>>> + bias-disable;
>>>> + power-source = <0>;
>>>> + };
>>>> +};
>>>> +
>>>> +
>>>> + volume-keys {
>>>
>>> gpio-keys ?
>>>
>>>> + compatible = "gpio-keys";
>>>> + label = "Volume keys";
>>>> + autorepeat;
>>>> +
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&volume_up_gpio>;
>>>> +
>>>> + key-vol-up {
>>>> + label = "Volume Up";
>>>> + linux,code = <KEY_VOLUMEUP>;
>>>> + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
>>>> + debounce-interval = <15>;
>>>> + };
>>>> + };
>>>> +
>>>> + vph_pwr: vph-pwr-regulator {
>>>
>>> Nit: BCP is regulator-foo-bar
>>>
>>>> + compatible = "regulator-fixed";
>>>> + regulator-name = "vph_pwr";
>>>> + regulator-min-microvolt = <3700000>;
>>>> + regulator-max-microvolt = <3700000>;
>>>> + };
>>>> +
>>>> + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
>>>> + compatible = "regulator-fixed";
>>>> + regulator-name = "vreg_s4a_1p8";
>>>> +
>>>> + regulator-min-microvolt = <1800000>;
>>>> + regulator-max-microvolt = <1800000>;
>>>> + regulator-always-on;
>>>> + regulator-boot-on;
>>>> +
>>>> + vin-supply = <&vph_pwr>;
>>>> + };
>>>> +};
>>>> +
>>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>>>> new file mode 100644
>>>> index 0000000000000..dc9938ffc0ab8
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>>>> @@ -0,0 +1,137 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +
>>>> +/dts-v1/;
>>>> +
>>>> +#include "sdm845-google-common.dtsi"
>>>> +
>>>> +/ {
>>>> + model = "Google Pixel 3 XL";
>>>> + compatible = "google,crosshatch", "qcom,sdm845";
>>>> +
>>>> + battery: battery {
>>>> + compatible = "simple-battery";
>>>> +
>>>> + charge-full-design-microamp-hours = <3480000>;
>>>> + voltage-min-design-microvolt = <3600000>;
>>>> + voltage-max-design-microvolt = <4400000>;
>>>> + };
>>>> +
>>>> + chosen {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges;
>>>
>>> These are all the same as the -blueline. Please move common options to
>>> the -common.dtsi
>>>
>>>> +
>>>> + /* for u-boot */
>>>> + framebuffer: framebuffer@9d400000 {
>>>> + compatible = "simple-framebuffer";
>>>> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
>>>> + width = <1440>;
>>>> + height = <2960>;
>>>> + stride = <(1440 * 4)>;
>>>> + format = "a8r8g8b8";
>>>> + };
>>>> + };
>>>> +
>>>> + reserved-memory {
>>>> + framebuffer_region@9d400000 {
>>>> + no-map;
>>>> + reg = <0 0x9d400000 0 0x02400000>;
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> +&gmu {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&mdss {
>>>
>>> More and more common properties. Please move them to the common file.
>>
>> Sorry about this, the mdss nodes got in by accident, the display driver for
>> crosshatch is WIP.>
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&mdss_dsi0 {
>>>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>>>> +
>>>> + status = "okay";
>>>> +
>>>> + ports {
>>>> + port@1 {
>>>> + endpoint {
>>>> + remote-endpoint = <&panel_in>;
>>>> + data-lanes = <0 1 2 3>;
>>>> + qcom,te-source = "mdp_vsync_e";
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + panel@0 {
>>>> + compatible = "samsung,s6e3ha8";
>>>> + reg = <0>;
>>>> +
>>>> + vci-supply = <&vreg_l28a_3p0>; // downstream
>>>> + vdd3-supply = <&vreg_l28a_3p0>;
>>>> + vddr-supply = <&vreg_l14a_1p88>;
>>>> +
>>>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>>>> +
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
>>>
>>> - Why do you need spiflash here?
>>> - I don't think this uses pmgpios too.
>>>
>>>> +
>>>> + port {
>>>> + panel_in: endpoint {
>>>> + remote-endpoint = <&mdss_dsi0_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> +&mdss_dsi0_out {
>>>> + data-lanes = <0 1 2 3>;
>>>> + remote-endpoint = <&panel_in>;
>>>> +};
>>>> +
>>>> +&mdss_dsi0_phy {
>>>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>>>> +
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&pm8998_gpios {
>>>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>>>> + pins = "gpio2", "gpio5";
>>>> + function = "normal";
>>>> + input-enable;
>>>> + bias-disable;
>>>> + power-source = <0>;
>>>> + };
>>>> +};
>>>> +
>>>> +&tlmm {
>>>> + se8_spiflash: se8-spiflash-state {
>>>> + pins = "gpio65", "gpio66", "gpio67", "gpio68";
>>>> + function = "gpio";
>>>> + input-enable;
>>>> + bias-disable;
>>>> + };
>>>> +
>>>> + panel_te_pin: panel-te-state {
>>>> + pins = "gpio12";
>>>> + function = "mdp_vsync";
>>>> + drive-strength = <2>;
>>>> + bias-pull-down;
>>>> + };
>>>> +
>>>> + panel_reset_pins: panel-active-state {
>>>> + pins = "gpio6";
>>>> + function = "gpio";
>>>> + drive-strength = <8>;
>>>> + bias-disable;
>>>> + };
>>>> +
>>>> + panel_suspend: panel-suspend-state {
>>>> + pins = "gpio6";
>>>> + function = "gpio";
>>>> + drive-strength = <2>;
>>>> + bias-pull-down;
>>>> + };
>>>> +
>>>> +};
>>>>
>>>> --
>>>> 2.51.0
>>>>
>>>>
>>>
>>
>> --
>> David Heidelberg
>>
>
--
David Heidelberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-10 7:51 ` David Heidelberg
@ 2025-10-10 8:17 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-10 8:17 UTC (permalink / raw)
To: David Heidelberg
Cc: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On Fri, Oct 10, 2025 at 09:51:37AM +0200, David Heidelberg wrote:
>
>
> On 09/10/2025 23:50, Dmitry Baryshkov wrote:
> > On Thu, Oct 09, 2025 at 11:20:49PM +0200, David Heidelberg wrote:
> > > On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> > > > On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
> > > > > From: David Heidelberg <david@ixit.cz>
> > > > >
> > > > > This adds initial device tree support for the following phones:
> > > > >
> > > > > - Google Pixel 3 (blueline)
> > > > > - Google Pixel 3 XL (crosshatch)
> > > >
> > > > Great to finally see it being submitted!
> > > >
> > > > >
> > > > > Both phone boards use the same identifiers and differ only slightly
> > > > > in their connected peripherals.
> > > > >
> > > > > Supported functionality includes:
> > > > > - Debug UART
> > > > > - UFS
> > > > > - Charger
> > > > > - USB-C (peripheral mode)
> > > > > - Display (Pixel 3 only)
> > > >
> > > > No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> > > > accessible to download from Google and it can be further repackaged (but
> > > > not redistributed). See [1], [2].
> > >
> > > Since I didn't have Pixel 3 at hand to test (I sent the series when
> > > attending event where someone had Pixel 3 ;-) ), I was aiming to merge MVP..
> > > more precisely, Minimal Viable Device-tree (MVD).
> >
> > If you have Pix3 XL, you can use it for both. I think the only major
> > difference is the screen.
>
> Yes, screen and battery.
>
> >
> > > Until the end of the month I should have also Pixel 3, so I'll definitely
> > > continue to enable all the mentioned features, but as this DTB is also
> > > needed for u-boot [1], I would prefer to get MVD in ASAP, mostly because of
> > > the fastboot is useless for loading mainline kernel.
> >
> > Hmm? I was using onboard ABL and fastboot.
>
> Most likely older bootloader, which doesn't insist on TEXT_OFFSET 0x80000 :)
> I have already new one, so without u-boot that's one extra revert (which I
> don't feel that comfortable with on top of mainline).
No. A new one + TEXT_OFFSET patch.
>
> David>
> > >
> > > [1] https://gitlab.postmarketos.org/tauchgang
> > >
> > > Before I'll send the v2, the progress can be tracked in
> > > https://gitlab.com/dhxx/linux/-/commits/b4/pixel-3
> > >
> > > Thank you both for the review!
> > > David
> > >
> > > >
> > > > The phones share all firmware except for the bdwlan, so hopefully you
> > > > can add 'Google/blueline/foo.mbn' to the common file.
> > > >
> > > > [1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
> > > > [2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
> > > >
> > > > >
> > > > > GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
> > > > > so they are marked as reserved to allow the Pixel 3 to boot.
> > > > >
> > > > > The rmtfs region is allocated using UIO, making it technically "dynamic."
> > > > >
> > > > > Its address and size can be read from sysfs:
> > > > >
> > > > > $ cat /sys/class/uio/uio0/name
> > > > > /sys/class/uio/uio0/maps/map0/addr
> > > > > 0x00000000f2701000
> > > > >
> > > > > $ cat /sys/class/uio/uio0/maps/map0/size
> > > > > 0x0000000000200000
> > > > >
> > > > > Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
> > > > > side of the rmtfs region to work around an XPU bug that would otherwise
> > > > > cause erroneous violations when accessing the rmtfs_mem region.
> > > > >
> > > > > Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
> > > > > Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
> > > > > Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > > > Co-developed-by: Casey Connolly <casey@connolly.tech>
> > > > > Signed-off-by: Casey Connolly <casey@connolly.tech>
> > > > > Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
> > > > > Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
> > > > > Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
> > > > > Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
> > > > > Co-developed-by: Vinod Koul <vkoul@kernel.org>
> > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > > > Signed-off-by: David Heidelberg <david@ixit.cz>
> > > > > ---
> > > > > arch/arm64/boot/dts/qcom/Makefile | 2 +
> > > > > .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
> > > > > arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
> > > > > .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
> > > > > 4 files changed, 734 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> > > > > index 4bfa926b6a085..ba05dc935dc7c 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/Makefile
> > > > > +++ b/arch/arm64/boot/dts/qcom/Makefile
> > > > > @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> > > > > sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
> > > > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
> > > > > +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
> > > > > +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
> > > > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
> > > > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
> > > > > dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> > > > > new file mode 100644
> > > > > index 0000000000000..df88982018b9e
> > > > > --- /dev/null
> > > > > +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
> > > > > @@ -0,0 +1,128 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > > +
> > > > > +/dts-v1/;
> > > > > +
> > > > > +#include "sdm845-google-common.dtsi"
> > > > > +
> > > > > +/ {
> > > > > + model = "Google Pixel 3";
> > > > > + compatible = "google,blueline", "qcom,sdm845";
> > > > > +
> > > > > + battery: battery {
> > > > > + compatible = "simple-battery";
> > > > > +
> > > > > + charge-full-design-microamp-hours = <2970000>;
> > > > > + voltage-min-design-microvolt = <3600000>;
> > > > > + voltage-max-design-microvolt = <4400000>;
> > > > > + };
> > > > > +
> > > > > + chosen {
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + ranges;
> > > > > +
> > > > > + /* for u-boot */
> > > > > + framebuffer: framebuffer@9d400000 {
> > > > > + compatible = "simple-framebuffer";
> > > > > + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
> > > > > + width = <1080>;
> > > > > + height = <2160>;
> > > > > + stride = <(1080 * 4)>;
> > > > > + format = "a8r8g8b8";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + reserved-memory {
> > > > > + framebuffer_region@9d400000 {
> > > >
> > > > Can't we use cont_splash_mem and let bootloader set it?
> > > >
> > > > > + no-map;
> > > > > + reg = <0 0x9d400000 0 0x02400000>; // FIXME
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&gmu {
> > > > > + status = "okay";
> > > > > +};
> > > >
> > > > No need to, it's enabled by default.
> > > >
> > > > > +
> > > > > +&mdss {
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&mdss_dsi0 {
> > > > > + status = "okay";
> > > > > + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> > > > > +
> > > > > + ports {
> > > > > + port@1 {
> > > > > + endpoint {
> > > > > + remote-endpoint = <&panel_in>;
> > > > > + data-lanes = <0 1 2 3>;
> > > > > + qcom,te-source = "mdp_vsync_e";
> > > >
> > > > &mdss_dsi1_out {
> > > > remote-endpoint = <&panel_in>;
> > > > .....
> > > > };
> > > >
> > > >
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + panel@0 {
> > > > > + compatible = "lg,sw43408";
> > > > > + reg = <0>;
> > > > > +
> > > > > + vddi-supply = <&vreg_l14a_1p88>;
> > > > > + vpnl-supply = <&vreg_l28a_3p0>;
> > > > > +
> > > > > + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> > > > > +
> > > > > + pinctrl-names = "default";
> > > > > + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
> > > > > +
> > > > > + port {
> > > > > + panel_in: endpoint {
> > > > > + remote-endpoint = <&mdss_dsi0_out>;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&mdss_dsi0_out {
> > > > > + remote-endpoint = <&panel_in>;
> > > > > + data-lanes = <0 1 2 3>;
> > > > > +};
> > > > > +
> > > > > +&mdss_dsi0_phy {
> > > > > + vdds-supply = <&vdda_mipi_dsi0_pll>;
> > > > > +
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&pm8998_gpios {
> > > > > + panel_pmgpio_pins: panel-pmgpio-active-state {
> > > >
> > > > Are these two actually used by the panel? I think they were only used
> > > > for sw43402, but not for sw43408.
> > > >
> > > > > + pins = "gpio2", "gpio5";
> > > > > + function = "normal";
> > > > > + input-enable;
> > > > > + bias-disable;
> > > > > + power-source = <0>;
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +
> > > > > + volume-keys {
> > > >
> > > > gpio-keys ?
> > > >
> > > > > + compatible = "gpio-keys";
> > > > > + label = "Volume keys";
> > > > > + autorepeat;
> > > > > +
> > > > > + pinctrl-names = "default";
> > > > > + pinctrl-0 = <&volume_up_gpio>;
> > > > > +
> > > > > + key-vol-up {
> > > > > + label = "Volume Up";
> > > > > + linux,code = <KEY_VOLUMEUP>;
> > > > > + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
> > > > > + debounce-interval = <15>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + vph_pwr: vph-pwr-regulator {
> > > >
> > > > Nit: BCP is regulator-foo-bar
> > > >
> > > > > + compatible = "regulator-fixed";
> > > > > + regulator-name = "vph_pwr";
> > > > > + regulator-min-microvolt = <3700000>;
> > > > > + regulator-max-microvolt = <3700000>;
> > > > > + };
> > > > > +
> > > > > + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
> > > > > + compatible = "regulator-fixed";
> > > > > + regulator-name = "vreg_s4a_1p8";
> > > > > +
> > > > > + regulator-min-microvolt = <1800000>;
> > > > > + regulator-max-microvolt = <1800000>;
> > > > > + regulator-always-on;
> > > > > + regulator-boot-on;
> > > > > +
> > > > > + vin-supply = <&vph_pwr>;
> > > > > + };
> > > > > +};
> > > > > +
> > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> > > > > new file mode 100644
> > > > > index 0000000000000..dc9938ffc0ab8
> > > > > --- /dev/null
> > > > > +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
> > > > > @@ -0,0 +1,137 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > > +
> > > > > +/dts-v1/;
> > > > > +
> > > > > +#include "sdm845-google-common.dtsi"
> > > > > +
> > > > > +/ {
> > > > > + model = "Google Pixel 3 XL";
> > > > > + compatible = "google,crosshatch", "qcom,sdm845";
> > > > > +
> > > > > + battery: battery {
> > > > > + compatible = "simple-battery";
> > > > > +
> > > > > + charge-full-design-microamp-hours = <3480000>;
> > > > > + voltage-min-design-microvolt = <3600000>;
> > > > > + voltage-max-design-microvolt = <4400000>;
> > > > > + };
> > > > > +
> > > > > + chosen {
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + ranges;
> > > >
> > > > These are all the same as the -blueline. Please move common options to
> > > > the -common.dtsi
> > > >
> > > > > +
> > > > > + /* for u-boot */
> > > > > + framebuffer: framebuffer@9d400000 {
> > > > > + compatible = "simple-framebuffer";
> > > > > + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
> > > > > + width = <1440>;
> > > > > + height = <2960>;
> > > > > + stride = <(1440 * 4)>;
> > > > > + format = "a8r8g8b8";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + reserved-memory {
> > > > > + framebuffer_region@9d400000 {
> > > > > + no-map;
> > > > > + reg = <0 0x9d400000 0 0x02400000>;
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&gmu {
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&mdss {
> > > >
> > > > More and more common properties. Please move them to the common file.
> > >
> > > Sorry about this, the mdss nodes got in by accident, the display driver for
> > > crosshatch is WIP.>
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&mdss_dsi0 {
> > > > > + vdda-supply = <&vdda_mipi_dsi0_1p2>;
> > > > > +
> > > > > + status = "okay";
> > > > > +
> > > > > + ports {
> > > > > + port@1 {
> > > > > + endpoint {
> > > > > + remote-endpoint = <&panel_in>;
> > > > > + data-lanes = <0 1 2 3>;
> > > > > + qcom,te-source = "mdp_vsync_e";
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + panel@0 {
> > > > > + compatible = "samsung,s6e3ha8";
> > > > > + reg = <0>;
> > > > > +
> > > > > + vci-supply = <&vreg_l28a_3p0>; // downstream
> > > > > + vdd3-supply = <&vreg_l28a_3p0>;
> > > > > + vddr-supply = <&vreg_l14a_1p88>;
> > > > > +
> > > > > + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> > > > > +
> > > > > + pinctrl-names = "default";
> > > > > + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
> > > >
> > > > - Why do you need spiflash here?
> > > > - I don't think this uses pmgpios too.
> > > >
> > > > > +
> > > > > + port {
> > > > > + panel_in: endpoint {
> > > > > + remote-endpoint = <&mdss_dsi0_out>;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&mdss_dsi0_out {
> > > > > + data-lanes = <0 1 2 3>;
> > > > > + remote-endpoint = <&panel_in>;
> > > > > +};
> > > > > +
> > > > > +&mdss_dsi0_phy {
> > > > > + vdds-supply = <&vdda_mipi_dsi0_pll>;
> > > > > +
> > > > > + status = "okay";
> > > > > +};
> > > > > +
> > > > > +&pm8998_gpios {
> > > > > + panel_pmgpio_pins: panel-pmgpio-active-state {
> > > > > + pins = "gpio2", "gpio5";
> > > > > + function = "normal";
> > > > > + input-enable;
> > > > > + bias-disable;
> > > > > + power-source = <0>;
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&tlmm {
> > > > > + se8_spiflash: se8-spiflash-state {
> > > > > + pins = "gpio65", "gpio66", "gpio67", "gpio68";
> > > > > + function = "gpio";
> > > > > + input-enable;
> > > > > + bias-disable;
> > > > > + };
> > > > > +
> > > > > + panel_te_pin: panel-te-state {
> > > > > + pins = "gpio12";
> > > > > + function = "mdp_vsync";
> > > > > + drive-strength = <2>;
> > > > > + bias-pull-down;
> > > > > + };
> > > > > +
> > > > > + panel_reset_pins: panel-active-state {
> > > > > + pins = "gpio6";
> > > > > + function = "gpio";
> > > > > + drive-strength = <8>;
> > > > > + bias-disable;
> > > > > + };
> > > > > +
> > > > > + panel_suspend: panel-suspend-state {
> > > > > + pins = "gpio6";
> > > > > + function = "gpio";
> > > > > + drive-strength = <2>;
> > > > > + bias-pull-down;
> > > > > + };
> > > > > +
> > > > > +};
> > > > >
> > > > > --
> > > > > 2.51.0
> > > > >
> > > > >
> > > >
> > >
> > > --
> > > David Heidelberg
> > >
> >
>
> --
> David Heidelberg
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-05 22:03 ` Dmitry Baryshkov
2025-10-09 21:20 ` David Heidelberg
@ 2025-10-17 16:59 ` David Heidelberg
2025-10-19 11:51 ` Dmitry Baryshkov
2025-10-17 22:23 ` David Heidelberg
2 siblings, 1 reply; 23+ messages in thread
From: David Heidelberg @ 2025-10-17 16:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> This adds initial device tree support for the following phones:
>>
>> - Google Pixel 3 (blueline)
>> - Google Pixel 3 XL (crosshatch)
>
> Great to finally see it being submitted!
>
>>
>> Both phone boards use the same identifiers and differ only slightly
>> in their connected peripherals.
>>
>> Supported functionality includes:
>> - Debug UART
>> - UFS
>> - Charger
>> - USB-C (peripheral mode)
>> - Display (Pixel 3 only)
>
> No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> accessible to download from Google and it can be further repackaged (but
> not redistributed). See [1], [2].
>
> The phones share all firmware except for the bdwlan, so hopefully you
> can add 'Google/blueline/foo.mbn' to the common file.
Would it be acceptable to use path format qcom/sdm845/$codename/ e.g.
qcom/sdm845/blueline as it's used elsewhere?
As I'm looking at the Google scripts, I assume both blueline/crosshatch
use same firmware (which makes sense, as only the battery and display is
different).
David
>
> [1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
> [2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
>
>>
>> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
>> so they are marked as reserved to allow the Pixel 3 to boot.
>>
>> The rmtfs region is allocated using UIO, making it technically "dynamic."
>>
>> Its address and size can be read from sysfs:
>>
>> $ cat /sys/class/uio/uio0/name
>> /sys/class/uio/uio0/maps/map0/addr
>> 0x00000000f2701000
>>
>> $ cat /sys/class/uio/uio0/maps/map0/size
>> 0x0000000000200000
>>
>> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
>> side of the rmtfs region to work around an XPU bug that would otherwise
>> cause erroneous violations when accessing the rmtfs_mem region.
>>
>> Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
>> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
>> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Co-developed-by: Casey Connolly <casey@connolly.tech>
>> Signed-off-by: Casey Connolly <casey@connolly.tech>
>> Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
>> Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
>> Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
>> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>> Co-developed-by: Vinod Koul <vkoul@kernel.org>
>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 2 +
>> .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
>> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
>> .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
>> 4 files changed, 734 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 4bfa926b6a085..ba05dc935dc7c 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
>> sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
>>
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> new file mode 100644
>> index 0000000000000..df88982018b9e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> @@ -0,0 +1,128 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> + model = "Google Pixel 3";
>> + compatible = "google,blueline", "qcom,sdm845";
>> +
>> + battery: battery {
>> + compatible = "simple-battery";
>> +
>> + charge-full-design-microamp-hours = <2970000>;
>> + voltage-min-design-microvolt = <3600000>;
>> + voltage-max-design-microvolt = <4400000>;
>> + };
>> +
>> + chosen {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + /* for u-boot */
>> + framebuffer: framebuffer@9d400000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
>> + width = <1080>;
>> + height = <2160>;
>> + stride = <(1080 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + framebuffer_region@9d400000 {
>
> Can't we use cont_splash_mem and let bootloader set it?
>
>> + no-map;
>> + reg = <0 0x9d400000 0 0x02400000>; // FIXME
>> + };
>> + };
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>
> No need to, it's enabled by default.
>
>> +
>> +&mdss {
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + status = "okay";
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>
> &mdss_dsi1_out {
> remote-endpoint = <&panel_in>;
> .....
> };
>
>
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "lg,sw43408";
>> + reg = <0>;
>> +
>> + vddi-supply = <&vreg_l14a_1p88>;
>> + vpnl-supply = <&vreg_l28a_3p0>;
>> +
>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
>> +
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>
> Are these two actually used by the panel? I think they were only used
> for sw43402, but not for sw43408.
>
>> + pins = "gpio2", "gpio5";
>> + function = "normal";
>> + input-enable;
>> + bias-disable;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> +
>> + volume-keys {
>
> gpio-keys ?
>
>> + compatible = "gpio-keys";
>> + label = "Volume keys";
>> + autorepeat;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&volume_up_gpio>;
>> +
>> + key-vol-up {
>> + label = "Volume Up";
>> + linux,code = <KEY_VOLUMEUP>;
>> + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
>> + debounce-interval = <15>;
>> + };
>> + };
>> +
>> + vph_pwr: vph-pwr-regulator {
>
> Nit: BCP is regulator-foo-bar
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> + };
>> +
>> + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg_s4a_1p8";
>> +
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> +
>> + vin-supply = <&vph_pwr>;
>> + };
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> new file mode 100644
>> index 0000000000000..dc9938ffc0ab8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> @@ -0,0 +1,137 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> + model = "Google Pixel 3 XL";
>> + compatible = "google,crosshatch", "qcom,sdm845";
>> +
>> + battery: battery {
>> + compatible = "simple-battery";
>> +
>> + charge-full-design-microamp-hours = <3480000>;
>> + voltage-min-design-microvolt = <3600000>;
>> + voltage-max-design-microvolt = <4400000>;
>> + };
>> +
>> + chosen {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>
> These are all the same as the -blueline. Please move common options to
> the -common.dtsi
>
>> +
>> + /* for u-boot */
>> + framebuffer: framebuffer@9d400000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
>> + width = <1440>;
>> + height = <2960>;
>> + stride = <(1440 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + framebuffer_region@9d400000 {
>> + no-map;
>> + reg = <0 0x9d400000 0 0x02400000>;
>> + };
>> + };
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>> +
>> +&mdss {
>
> More and more common properties. Please move them to the common file.
>
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> + status = "okay";
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "samsung,s6e3ha8";
>> + reg = <0>;
>> +
>> + vci-supply = <&vreg_l28a_3p0>; // downstream
>> + vdd3-supply = <&vreg_l28a_3p0>;
>> + vddr-supply = <&vreg_l14a_1p88>;
>> +
>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
>
> - Why do you need spiflash here?
> - I don't think this uses pmgpios too.
>
>> +
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + data-lanes = <0 1 2 3>;
>> + remote-endpoint = <&panel_in>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>> + pins = "gpio2", "gpio5";
>> + function = "normal";
>> + input-enable;
>> + bias-disable;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> +&tlmm {
>> + se8_spiflash: se8-spiflash-state {
>> + pins = "gpio65", "gpio66", "gpio67", "gpio68";
>> + function = "gpio";
>> + input-enable;
>> + bias-disable;
>> + };
>> +
>> + panel_te_pin: panel-te-state {
>> + pins = "gpio12";
>> + function = "mdp_vsync";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + panel_reset_pins: panel-active-state {
>> + pins = "gpio6";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + panel_suspend: panel-suspend-state {
>> + pins = "gpio6";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> +};
>>
>> --
>> 2.51.0
>>
>>
>
--
David Heidelberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-05 22:03 ` Dmitry Baryshkov
2025-10-09 21:20 ` David Heidelberg
2025-10-17 16:59 ` David Heidelberg
@ 2025-10-17 22:23 ` David Heidelberg
2025-10-19 11:51 ` Dmitry Baryshkov
2 siblings, 1 reply; 23+ messages in thread
From: David Heidelberg @ 2025-10-17 22:23 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> This adds initial device tree support for the following phones:
>>
>> - Google Pixel 3 (blueline)
>> - Google Pixel 3 XL (crosshatch)
>
> Great to finally see it being submitted!
>
>>
>> Both phone boards use the same identifiers and differ only slightly
>> in their connected peripherals.
>>
>> Supported functionality includes:
>> - Debug UART
>> - UFS
>> - Charger
>> - USB-C (peripheral mode)
>> - Display (Pixel 3 only)
>
> No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> accessible to download from Google and it can be further repackaged (but
> not redistributed). See [1], [2].
>
> The phones share all firmware except for the bdwlan, so hopefully you
> can add 'Google/blueline/foo.mbn' to the common file.
>
> [1] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel3.bb
> [2] https://github.com/linux-msm/meta-qcom-extras/blob/master/recipes-bsp/firmware-nexus/firmware-qcom-pixel.inc
>
>>
>> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
>> so they are marked as reserved to allow the Pixel 3 to boot.
>>
>> The rmtfs region is allocated using UIO, making it technically "dynamic."
>>
>> Its address and size can be read from sysfs:
>>
>> $ cat /sys/class/uio/uio0/name
>> /sys/class/uio/uio0/maps/map0/addr
>> 0x00000000f2701000
>>
>> $ cat /sys/class/uio/uio0/maps/map0/size
>> 0x0000000000200000
>>
>> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
>> side of the rmtfs region to work around an XPU bug that would otherwise
>> cause erroneous violations when accessing the rmtfs_mem region.
>>
>> Co-developed-by: Amit Pundir <amit.pundir@linaro.org>
>> Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
>> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Co-developed-by: Casey Connolly <casey@connolly.tech>
>> Signed-off-by: Casey Connolly <casey@connolly.tech>
>> Co-developed-by: Joel Selvaraj <foss@joelselvaraj.com>
>> Signed-off-by: Joel Selvaraj <foss@joelselvaraj.com>
>> Co-developed-by: Sumit Semwal <sumit.semwal@linaro.org>
>> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>> Co-developed-by: Vinod Koul <vkoul@kernel.org>
>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 2 +
>> .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++
>> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++++++
>> .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++
>> 4 files changed, 734 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 4bfa926b6a085..ba05dc935dc7c 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
>> sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
>>
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> new file mode 100644
>> index 0000000000000..df88982018b9e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts
>> @@ -0,0 +1,128 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> + model = "Google Pixel 3";
>> + compatible = "google,blueline", "qcom,sdm845";
>> +
>> + battery: battery {
>> + compatible = "simple-battery";
>> +
>> + charge-full-design-microamp-hours = <2970000>;
>> + voltage-min-design-microvolt = <3600000>;
>> + voltage-max-design-microvolt = <4400000>;
>> + };
>> +
>> + chosen {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + /* for u-boot */
>> + framebuffer: framebuffer@9d400000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>;
>> + width = <1080>;
>> + height = <2160>;
>> + stride = <(1080 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + framebuffer_region@9d400000 {
>
> Can't we use cont_splash_mem and let bootloader set it?
>
>> + no-map;
>> + reg = <0 0x9d400000 0 0x02400000>; // FIXME
>> + };
>> + };
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>
> No need to, it's enabled by default.
>
>> +
>> +&mdss {
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + status = "okay";
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>
> &mdss_dsi1_out {
> remote-endpoint = <&panel_in>;
> .....
> };
>
>
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "lg,sw43408";
>> + reg = <0>;
>> +
>> + vddi-supply = <&vreg_l14a_1p88>;
>> + vpnl-supply = <&vreg_l28a_3p0>;
>> +
>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
>> +
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>
> Are these two actually used by the panel? I think they were only used
> for sw43402, but not for sw43408.
Yes, I tested and it seems the display behaves same way.>
>> + pins = "gpio2", "gpio5";
>> + function = "normal";
>> + input-enable;
>> + bias-disable;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> +
>> + volume-keys {
>
> gpio-keys ?
>
>> + compatible = "gpio-keys";
>> + label = "Volume keys";
>> + autorepeat;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&volume_up_gpio>;
>> +
>> + key-vol-up {
>> + label = "Volume Up";
>> + linux,code = <KEY_VOLUMEUP>;
>> + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
>> + debounce-interval = <15>;
>> + };
>> + };
>> +
>> + vph_pwr: vph-pwr-regulator {
>
> Nit: BCP is regulator-foo-bar
Can you clarify, all other device-tree use this format, do you mean
regulator-pwr-vph?
Thank you
David
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> + };
>> +
>> + vreg_s4a_1p8: vreg-s4a-1p8-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg_s4a_1p8";
>> +
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> +
>> + vin-supply = <&vph_pwr>;
>> + };
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> new file mode 100644
>> index 0000000000000..dc9938ffc0ab8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> @@ -0,0 +1,137 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> + model = "Google Pixel 3 XL";
>> + compatible = "google,crosshatch", "qcom,sdm845";
>> +
>> + battery: battery {
>> + compatible = "simple-battery";
>> +
>> + charge-full-design-microamp-hours = <3480000>;
>> + voltage-min-design-microvolt = <3600000>;
>> + voltage-max-design-microvolt = <4400000>;
>> + };
>> +
>> + chosen {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>
> These are all the same as the -blueline. Please move common options to
> the -common.dtsi
>
>> +
>> + /* for u-boot */
>> + framebuffer: framebuffer@9d400000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
>> + width = <1440>;
>> + height = <2960>;
>> + stride = <(1440 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + framebuffer_region@9d400000 {
>> + no-map;
>> + reg = <0 0x9d400000 0 0x02400000>;
>> + };
>> + };
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>> +
>> +&mdss {
>
> More and more common properties. Please move them to the common file.
>
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> + status = "okay";
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "samsung,s6e3ha8";
>> + reg = <0>;
>> +
>> + vci-supply = <&vreg_l28a_3p0>; // downstream
>> + vdd3-supply = <&vreg_l28a_3p0>;
>> + vddr-supply = <&vreg_l14a_1p88>;
>> +
>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgpio_pins>;
>
> - Why do you need spiflash here?
> - I don't think this uses pmgpios too.
>
>> +
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + data-lanes = <0 1 2 3>;
>> + remote-endpoint = <&panel_in>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + vdds-supply = <&vdda_mipi_dsi0_pll>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&pm8998_gpios {
>> + panel_pmgpio_pins: panel-pmgpio-active-state {
>> + pins = "gpio2", "gpio5";
>> + function = "normal";
>> + input-enable;
>> + bias-disable;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> +&tlmm {
>> + se8_spiflash: se8-spiflash-state {
>> + pins = "gpio65", "gpio66", "gpio67", "gpio68";
>> + function = "gpio";
>> + input-enable;
>> + bias-disable;
>> + };
>> +
>> + panel_te_pin: panel-te-state {
>> + pins = "gpio12";
>> + function = "mdp_vsync";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + panel_reset_pins: panel-active-state {
>> + pins = "gpio6";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + panel_suspend: panel-suspend-state {
>> + pins = "gpio6";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> +};
>>
>> --
>> 2.51.0
>>
>>
>
--
David Heidelberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-06 12:41 ` Konrad Dybcio
@ 2025-10-17 23:32 ` David Heidelberg
0 siblings, 0 replies; 23+ messages in thread
From: David Heidelberg @ 2025-10-17 23:32 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Amit Pundir,
Casey Connolly, Joel Selvaraj, Sumit Semwal, Vinod Koul
On 06/10/2025 14:41, Konrad Dybcio wrote:
> On 10/5/25 3:16 PM, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> This adds initial device tree support for the following phones:
>>
>> - Google Pixel 3 (blueline)
>> - Google Pixel 3 XL (crosshatch)
>>
>> Both phone boards use the same identifiers and differ only slightly
>> in their connected peripherals.
>>
>> Supported functionality includes:
>> - Debug UART
>> - UFS
>> - Charger
>> - USB-C (peripheral mode)
>> - Display (Pixel 3 only)
>>
>> GPIOs 0–3 and 81–84 are not accessible from the application CPUs,
>> so they are marked as reserved to allow the Pixel 3 to boot.
>>
>> The rmtfs region is allocated using UIO, making it technically "dynamic."
>>
>> Its address and size can be read from sysfs:
>>
>> $ cat /sys/class/uio/uio0/name
>> /sys/class/uio/uio0/maps/map0/addr
>> 0x00000000f2701000
>>
>> $ cat /sys/class/uio/uio0/maps/map0/size
>> 0x0000000000200000
>>
>> Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either
>> side of the rmtfs region to work around an XPU bug that would otherwise
>> cause erroneous violations when accessing the rmtfs_mem region.
>
> [...]
>
>> +&gmu {
>> + status = "okay";
>> +};
>
> It's already enabled> +
>> +&mdss {
>> + status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> + status = "okay";
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>
> 'status' should be last, with a \n before it
>
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>
> &mdss_dsi0_out {} instead
>
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "lg,sw43408";
>> + reg = <0>;
>> +
>> + vddi-supply = <&vreg_l14a_1p88>;
>> + vpnl-supply = <&vreg_l28a_3p0>;
>> +
>> + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>;
>
> property-n
> property-names
>
> in this order, please
>
>> +
>> + port {
>> + panel_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> +};
>
> (as mentioned above..)
>
> [...]
>
>> + /* rmtfs lower guard */
>> + memory@f2700000 {
>> + reg = <0 0xf2700000 0 0x1000>;
>> + no-map;
>> + };
>> +
>> + rmtfs_mem: memory@f2701000 {
>> + compatible = "qcom,rmtfs-mem";
>> + reg = <0 0xf2701000 0 0x200000>;
>> + no-map;
>> +
>> + qcom,client-id = <1>;
>> + qcom,vmid = <15>;
>> + };
>> +
>> + /* rmtfs upper guard */
>> + memory@f2901000 {
>> + reg = <0 0xf2901000 0 0x1000>;
>> + no-map;
>> + };
>
> qcom,use-guard-pages instead
>
> [...]
>
>> + vreg_l14a_1p88: ldo14 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + regulator-boot-on;
>> + /*
>> + * We can't properly bring the panel back if it gets turned off
>> + * so keep it's regulators always on for now.
>> + */
>> + regulator-always-on;
>
> Sounds like your panel driver is not sequencing things properly
>
> [...]
>
>> +&uart9 {
>> + label = "LS-UART1";
>
> This is a 96boards-ism> +
>> + status = "okay";
>> +};
>> +
>> +&usb_1 {
>> + status = "okay";
>> +};
>> +
>> +&usb_1_dwc3 {
>> + dr_mode = "peripheral";
>
> Are you sure?
For now, the peripheral usb works, haven't tried to switch to host mode yet.
>
> [...]
>
>> +&usb_2 {
>> + status = "okay";
>> +};
>> +
>> +&usb_2_dwc3 {
>> + dr_mode = "host";
>
> Does the phone actually have something connected to both USB hosts?
I assume not,
Bus 001 Device 001: ID 1d6b:0002 Linux 6.16.7-sdm845 xhci-hcd xHCI Host
Controller
Bus 002 Device 001: ID 1d6b:0003 Linux 6.16.7-sdm845 xhci-hcd xHCI Host
Controller
I looked at the downstream description and it seems usb_2 was used only
on sda845 devkit.
David
>
> Would that be the weasel(?) security chip?
>
> [...]
>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> new file mode 100644
>> index 0000000000000..dc9938ffc0ab8
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts
>> @@ -0,0 +1,137 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm845-google-common.dtsi"
>> +
>> +/ {
>> + model = "Google Pixel 3 XL";
>> + compatible = "google,crosshatch", "qcom,sdm845";
>> +
>> + battery: battery {
>> + compatible = "simple-battery";
>> +
>> + charge-full-design-microamp-hours = <3480000>;
>> + voltage-min-design-microvolt = <3600000>;
>> + voltage-max-design-microvolt = <4400000>;
>> + };
>> +
>> + chosen {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + /* for u-boot */
>> + framebuffer: framebuffer@9d400000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;
>> + width = <1440>;
>> + height = <2960>;
>> + stride = <(1440 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + framebuffer_region@9d400000 {
>> + no-map;
>> + reg = <0 0x9d400000 0 0x02400000>;
>> + };
>> + };
>> +};
>> +
>> +&gmu {
>> + status = "okay";
>> +};
>> +
>> +&mdss {
>> + status = "okay";
>> +};
>
> I'm sure you can push some of this into -common
>
>> +
>> +&mdss_dsi0 {
>> + vdda-supply = <&vdda_mipi_dsi0_1p2>;
>> +
>> + status = "okay";
>> +
>> + ports {
>> + port@1 {
>> + endpoint {
>> + remote-endpoint = <&panel_in>;
>> + data-lanes = <0 1 2 3>;
>> + qcom,te-source = "mdp_vsync_e";
>> + };
>> + };
>> + };
>> +
>> + panel@0 {
>> + compatible = "samsung,s6e3ha8";
>> + reg = <0>;
>> +
>> + vci-supply = <&vreg_l28a_3p0>; // downstream
>
> which supply should /* upstream */ use then? :(
>
> Konrad
--
David Heidelberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-17 16:59 ` David Heidelberg
@ 2025-10-19 11:51 ` Dmitry Baryshkov
2025-10-19 13:02 ` David Heidelberg
0 siblings, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-19 11:51 UTC (permalink / raw)
To: David Heidelberg
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On Fri, Oct 17, 2025 at 06:59:14PM +0200, David Heidelberg wrote:
> On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> > On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
> > > From: David Heidelberg <david@ixit.cz>
> > >
> > > This adds initial device tree support for the following phones:
> > >
> > > - Google Pixel 3 (blueline)
> > > - Google Pixel 3 XL (crosshatch)
> >
> > Great to finally see it being submitted!
> >
> > >
> > > Both phone boards use the same identifiers and differ only slightly
> > > in their connected peripherals.
> > >
> > > Supported functionality includes:
> > > - Debug UART
> > > - UFS
> > > - Charger
> > > - USB-C (peripheral mode)
> > > - Display (Pixel 3 only)
> >
> > No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> > accessible to download from Google and it can be further repackaged (but
> > not redistributed). See [1], [2].
> >
> > The phones share all firmware except for the bdwlan, so hopefully you
> > can add 'Google/blueline/foo.mbn' to the common file.
>
> Would it be acceptable to use path format qcom/sdm845/$codename/ e.g.
> qcom/sdm845/blueline as it's used elsewhere?
We have settled on qcom/SoC/Vendor/device/ long ago. Could you please
follow? All upstream Qualcomm devices follow this approach.
bdwlan should be sent to ath10k ML:
https://wireless.docs.kernel.org/en/latest/en/users/drivers/ath10k/boardfiles.html
> As I'm looking at the Google scripts, I assume both blueline/crosshatch use
> same firmware (which makes sense, as only the battery and display is
> different).
>
> David
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-17 22:23 ` David Heidelberg
@ 2025-10-19 11:51 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-19 11:51 UTC (permalink / raw)
To: David Heidelberg
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On Sat, Oct 18, 2025 at 12:23:50AM +0200, David Heidelberg wrote:
>
>
> On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> > On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
> > > From: David Heidelberg <david@ixit.cz>
> > > + compatible = "gpio-keys";
> > > + label = "Volume keys";
> > > + autorepeat;
> > > +
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&volume_up_gpio>;
> > > +
> > > + key-vol-up {
> > > + label = "Volume Up";
> > > + linux,code = <KEY_VOLUMEUP>;
> > > + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
> > > + debounce-interval = <15>;
> > > + };
> > > + };
> > > +
> > > + vph_pwr: vph-pwr-regulator {
> >
> > Nit: BCP is regulator-foo-bar
>
> Can you clarify, all other device-tree use this format, do you mean
> regulator-pwr-vph?
regulator-vph-pwr
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-19 11:51 ` Dmitry Baryshkov
@ 2025-10-19 13:02 ` David Heidelberg
2025-10-19 14:53 ` Dmitry Baryshkov
0 siblings, 1 reply; 23+ messages in thread
From: David Heidelberg @ 2025-10-19 13:02 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On 19/10/2025 13:51, Dmitry Baryshkov wrote:
> On Fri, Oct 17, 2025 at 06:59:14PM +0200, David Heidelberg wrote:
>> On 06/10/2025 00:03, Dmitry Baryshkov wrote:
>>> On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
>>>> From: David Heidelberg <david@ixit.cz>
>>>>
>>>> This adds initial device tree support for the following phones:
>>>>
>>>> - Google Pixel 3 (blueline)
>>>> - Google Pixel 3 XL (crosshatch)
>>>
>>> Great to finally see it being submitted!
>>>
>>>>
>>>> Both phone boards use the same identifiers and differ only slightly
>>>> in their connected peripherals.
>>>>
>>>> Supported functionality includes:
>>>> - Debug UART
>>>> - UFS
>>>> - Charger
>>>> - USB-C (peripheral mode)
>>>> - Display (Pixel 3 only)
>>>
>>> No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
>>> accessible to download from Google and it can be further repackaged (but
>>> not redistributed). See [1], [2].
>>>
>>> The phones share all firmware except for the bdwlan, so hopefully you
>>> can add 'Google/blueline/foo.mbn' to the common file.
>>
>> Would it be acceptable to use path format qcom/sdm845/$codename/ e.g.
>> qcom/sdm845/blueline as it's used elsewhere?
>
> We have settled on qcom/SoC/Vendor/device/ long ago. Could you please
> follow? All upstream Qualcomm devices follow this approach.
Sure, in next version it's done! Would you be open if I sent changes to
the existing firmware paths for sdm845 firmwares?
Thank you
>
> bdwlan should be sent to ath10k ML:
> https://wireless.docs.kernel.org/en/latest/en/users/drivers/ath10k/boardfiles.html
>
>> As I'm looking at the Google scripts, I assume both blueline/crosshatch use
>> same firmware (which makes sense, as only the battery and display is
>> different).
>>
>> David
>>
>
--
David Heidelberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
2025-10-19 13:02 ` David Heidelberg
@ 2025-10-19 14:53 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2025-10-19 14:53 UTC (permalink / raw)
To: David Heidelberg
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Amit Pundir, Casey Connolly, Joel Selvaraj, Sumit Semwal,
Vinod Koul
On Sun, Oct 19, 2025 at 03:02:36PM +0200, David Heidelberg wrote:
> On 19/10/2025 13:51, Dmitry Baryshkov wrote:
> > On Fri, Oct 17, 2025 at 06:59:14PM +0200, David Heidelberg wrote:
> > > On 06/10/2025 00:03, Dmitry Baryshkov wrote:
> > > > On Sun, Oct 05, 2025 at 03:16:29PM +0200, David Heidelberg via B4 Relay wrote:
> > > > > From: David Heidelberg <david@ixit.cz>
> > > > >
> > > > > This adds initial device tree support for the following phones:
> > > > >
> > > > > - Google Pixel 3 (blueline)
> > > > > - Google Pixel 3 XL (crosshatch)
> > > >
> > > > Great to finally see it being submitted!
> > > >
> > > > >
> > > > > Both phone boards use the same identifiers and differ only slightly
> > > > > in their connected peripherals.
> > > > >
> > > > > Supported functionality includes:
> > > > > - Debug UART
> > > > > - UFS
> > > > > - Charger
> > > > > - USB-C (peripheral mode)
> > > > > - Display (Pixel 3 only)
> > > >
> > > > No remoteprocs / IPA / GPU / Venus / WiFi / BT? The firmware is
> > > > accessible to download from Google and it can be further repackaged (but
> > > > not redistributed). See [1], [2].
> > > >
> > > > The phones share all firmware except for the bdwlan, so hopefully you
> > > > can add 'Google/blueline/foo.mbn' to the common file.
> > >
> > > Would it be acceptable to use path format qcom/sdm845/$codename/ e.g.
> > > qcom/sdm845/blueline as it's used elsewhere?
> >
> > We have settled on qcom/SoC/Vendor/device/ long ago. Could you please
> > follow? All upstream Qualcomm devices follow this approach.
>
> Sure, in next version it's done! Would you be open if I sent changes to the
> existing firmware paths for sdm845 firmwares?
Yes, please.
>
> Thank you
>
> >
> > bdwlan should be sent to ath10k ML:
> > https://wireless.docs.kernel.org/en/latest/en/users/drivers/ath10k/boardfiles.html
> >
> > > As I'm looking at the Google scripts, I assume both blueline/crosshatch use
> > > same firmware (which makes sense, as only the battery and display is
> > > different).
> > >
> > > David
> > >
> >
>
> --
> David Heidelberg
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2025-10-19 14:53 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-05 13:16 [PATCH 0/2] Add support for Pixel 3 and Pixel 3 XL David Heidelberg via B4 Relay
2025-10-05 13:16 ` [PATCH 1/2] Documentation: dt-bindings: arm: qcom: Add Pixel 3 and " David Heidelberg via B4 Relay
2025-10-05 22:21 ` Dmitry Baryshkov
2025-10-06 8:09 ` Konrad Dybcio
2025-10-06 10:09 ` David Heidelberg
2025-10-06 10:16 ` Konrad Dybcio
2025-10-06 10:17 ` Dmitry Baryshkov
2025-10-05 13:16 ` [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel " David Heidelberg via B4 Relay
2025-10-05 13:25 ` David Heidelberg
2025-10-05 22:03 ` Dmitry Baryshkov
2025-10-09 21:20 ` David Heidelberg
2025-10-09 21:50 ` Dmitry Baryshkov
2025-10-10 7:51 ` David Heidelberg
2025-10-10 8:17 ` Dmitry Baryshkov
2025-10-17 16:59 ` David Heidelberg
2025-10-19 11:51 ` Dmitry Baryshkov
2025-10-19 13:02 ` David Heidelberg
2025-10-19 14:53 ` Dmitry Baryshkov
2025-10-17 22:23 ` David Heidelberg
2025-10-19 11:51 ` Dmitry Baryshkov
2025-10-06 12:41 ` Konrad Dybcio
2025-10-17 23:32 ` David Heidelberg
2025-10-05 22:15 ` [PATCH 0/2] " Dmitry Baryshkov
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