* [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
@ 2025-09-30 9:37 Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
` (20 more replies)
0 siblings, 21 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
This patch series includes changes related to the PLL and peripheral
clocks for both the A4 and A5 SoCs.
The patches for A5 were previously submitted up to V3 by Xianwei.
https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
After friendly coordination, I’ve taken over and continued the
submission as part of this series. The dt-bindings patch retains Rob's
original "Reviewed-by" tag, and I hope this hasn’t caused any
additional confusion.
Both A4 and A5 belong to the Audio series. Judging by their names, one
might assume that A5 is an upgrade to A4, but in fact, A5 was released
a year earlier than A4.
Since there are differences in the PLLs and peripheral clocks between
the A4 and A5 SoCs (especially the PLL), and taking into account factors
such as memory footprint and maintainability, this series does not
attempt to merge the two into a shared driver as was done for
G12A/G12B/SM1.
This patch series includes all related dt-bindings, driver, and dts
changes for the PLLs and peripheral clocks. Following our past convention
for clock-related submissions, the dts changes are placed at the end
and submitted separately. If this ordering makes it harder for
maintainers to review or pick patches, please feel free to point it out.
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
Chuan Liu (19):
dt-bindings: clock: Add Amlogic A4 SCMI clock controller
dt-bindings: clock: Add Amlogic A4 PLL clock controller
dt-bindings: clock: Add Amlogic A4 peripherals clock controller
clk: amlogic: Optimize PLL enable timing
clk: amlogic: Correct l_detect bit control
clk: amlogic: Fix out-of-range PLL frequency setting
clk: amlogic: Add A4 PLL clock controller driver
clk: amlogic: Add A4 clock peripherals controller driver
arm64: dts: amlogic: A4: Add scmi-clk node
arm64: dts: amlogic: A4: Add PLL controller node
arm64: dts: amlogic: A4: Add peripherals clock controller node
dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
dt-bindings: clock: Add Amlogic A5 PLL clock controller
dt-bindings: clock: Add Amlogic A5 peripherals clock controller
clk: amlogic: Add A5 PLL clock controller driver
clk: amlogic: Add A5 clock peripherals controller driver
arm64: dts: amlogic: A5: Add scmi-clk node
arm64: dts: amlogic: A5: Add PLL controller node
arm64: dts: amlogic: A5: Add peripheral clock controller node
.../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
.../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
.../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
.../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
drivers/clk/meson/Kconfig | 53 ++
drivers/clk/meson/Makefile | 4 +
drivers/clk/meson/a1-pll.c | 1 +
drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
drivers/clk/meson/a4-pll.c | 242 ++++++
drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
drivers/clk/meson/a5-pll.c | 476 +++++++++++
drivers/clk/meson/clk-pll.c | 76 +-
drivers/clk/meson/clk-pll.h | 2 +
.../clock/amlogic,a4-peripherals-clkc.h | 129 +++
include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
.../clock/amlogic,a5-peripherals-clkc.h | 132 +++
include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
21 files changed, 3406 insertions(+), 28 deletions(-)
---
base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
Best regards,
--
Chuan Liu <chuan.liu@amlogic.com>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-10-09 18:07 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL " Chuan Liu via B4 Relay
` (19 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the SCMI clock controller dt-bindings for Amlogic A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 ++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h
new file mode 100644
index 000000000000..454e492f8f6f
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a4-scmi-clkc.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef __AMLOGIC_A4_SCMI_CLKC_H
+#define __AMLOGIC_A4_SCMI_CLKC_H
+
+#define CLKID_OSC 0
+#define CLKID_SYS_CLK 1
+#define CLKID_AXI_CLK 2
+#define CLKID_CPU_CLK 3
+#define CLKID_FIXED_PLL 4
+#define CLKID_GP1_PLL 5
+#define CLKID_ACLKM 6
+#define CLKID_SYS_PLL_DIV16 7
+#define CLKID_CPU_CLK_DIV16 8
+#define CLKID_FCLK_50M_PREDIV 9
+#define CLKID_FCLK_50M_DIV 10
+#define CLKID_FCLK_50M 11
+#define CLKID_FCLK_DIV2_DIV 12
+#define CLKID_FCLK_DIV2 13
+#define CLKID_FCLK_DIV2P5_DIV 14
+#define CLKID_FCLK_DIV2P5 15
+#define CLKID_FCLK_DIV3_DIV 16
+#define CLKID_FCLK_DIV3 17
+#define CLKID_FCLK_DIV4_DIV 18
+#define CLKID_FCLK_DIV4 19
+#define CLKID_FCLK_DIV5_DIV 20
+#define CLKID_FCLK_DIV5 21
+#define CLKID_FCLK_DIV7_DIV 22
+#define CLKID_FCLK_DIV7 23
+#define CLKID_SYS_MMC_PCLK 24
+#define CLKID_SYS_CPU_CTRL 25
+#define CLKID_SYS_IRQ_CTRL 26
+#define CLKID_SYS_GIC 27
+#define CLKID_SYS_BIG_NIC 28
+#define CLKID_AXI_SYS_NIC 29
+#define CLKID_AXI_CPU_DMC 30
+
+#endif /* __AMLOGIC_A4_SCMI_CLKC_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL clock controller
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-10-09 18:04 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals " Chuan Liu via B4 Relay
` (18 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the PLL clock controller dt-bindings for Amlogic A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
.../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++++++++++++++++++++++
include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 ++++++
2 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml
new file mode 100644
index 000000000000..dafad7bd4407
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a4-pll-clkc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a4-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A4 series PLL Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Chuan Liu <chuan.liu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,a4-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input oscillator
+ - description: input fix pll
+
+ clock-names:
+ items:
+ - const: xtal
+ - const: fix
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a4-scmi-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8000 {
+ compatible = "amlogic,a4-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x110>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_FIXED_PLL>;
+ clock-names = "xtal",
+ "fix";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a4-pll-clkc.h b/include/dt-bindings/clock/amlogic,a4-pll-clkc.h
new file mode 100644
index 000000000000..0950dcd68e0a
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a4-pll-clkc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H
+
+#define CLKID_GP0_PLL_DCO 0
+#define CLKID_GP0_PLL 1
+#define CLKID_HIFI_PLL_DCO 2
+#define CLKID_HIFI_PLL 3
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A4_PLL_CLKC_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals clock controller
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL " Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-10-09 18:04 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 04/19] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
` (17 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the peripherals clock controller dt-bindings for the Amlogic A4
SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
.../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++++++++++++++++++
.../clock/amlogic,a4-peripherals-clkc.h | 129 +++++++++++++++++++++
2 files changed, 251 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a4-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a4-peripherals-clkc.yaml
new file mode 100644
index 000000000000..13a0622f1f64
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a4-peripherals-clkc.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a4-peripherals-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A4 series Peripheral Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+ - Chuan Liu <chuan.liu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,a4-peripherals-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 16
+ items:
+ - description: input oscillator
+ - description: input oscillators multiplexer
+ - description: input fix pll
+ - description: input fclk div 2
+ - description: input fclk div 2p5
+ - description: input fclk div 3
+ - description: input fclk div 4
+ - description: input fclk div 5
+ - description: input fclk div 7
+ - description: input gp0 pll
+ - description: input gp1 pll
+ - description: input hifi pll
+ - description: input sys clk
+ - description: input axi clk
+ - description: input sys pll div 16
+ - description: input cpu clk div 16
+ - description: input pad clock for rtc clk (optional)
+
+ clock-names:
+ minItems: 16
+ items:
+ - const: xtal
+ - const: oscin
+ - const: fix
+ - const: fdiv2
+ - const: fdiv2p5
+ - const: fdiv3
+ - const: fdiv4
+ - const: fdiv5
+ - const: fdiv7
+ - const: gp0
+ - const: gp1
+ - const: hifi
+ - const: sysclk
+ - const: axiclk
+ - const: sysplldiv16
+ - const: cpudiv16
+ - const: pad_osc
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a4-scmi-clkc.h>
+ #include <dt-bindings/clock/amlogic,a4-pll-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@0 {
+ compatible = "amlogic,a4-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x20c>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_OSC>,
+ <&scmi_clk CLKID_FIXED_PLL>,
+ <&scmi_clk CLKID_FCLK_DIV2>,
+ <&scmi_clk CLKID_FCLK_DIV2P5>,
+ <&scmi_clk CLKID_FCLK_DIV3>,
+ <&scmi_clk CLKID_FCLK_DIV4>,
+ <&scmi_clk CLKID_FCLK_DIV5>,
+ <&scmi_clk CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_GP0_PLL>,
+ <&scmi_clk CLKID_GP1_PLL>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&scmi_clk CLKID_SYS_CLK>,
+ <&scmi_clk CLKID_AXI_CLK>,
+ <&scmi_clk CLKID_SYS_PLL_DIV16>,
+ <&scmi_clk CLKID_CPU_CLK_DIV16>;
+ clock-names = "xtal",
+ "oscin",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "gp0",
+ "gp1",
+ "hifi",
+ "sysclk",
+ "axiclk",
+ "sysplldiv16",
+ "cpudiv16";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a4-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a4-peripherals-clkc.h
new file mode 100644
index 000000000000..b09f4bb4d0d0
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a4-peripherals-clkc.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A4_PERIPHERALS_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_A4_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_DUALDIV_CLKIN 0
+#define CLKID_RTC_DUALDIV 1
+#define CLKID_RTC_DUALDIV_SEL 2
+#define CLKID_RTC_DUALDIV_CLKOUT 3
+#define CLKID_RTC_CLK 4
+#define CLKID_SYS_RESET_CTRL 5
+#define CLKID_SYS_PWR_CTRL 6
+#define CLKID_SYS_PAD_CTRL 7
+#define CLKID_SYS_CTRL 8
+#define CLKID_SYS_TS_PLL 9
+#define CLKID_SYS_DEV_ARB 10
+#define CLKID_SYS_MAILBOX 11
+#define CLKID_SYS_JTAG_CTRL 12
+#define CLKID_SYS_IR_CTRL 13
+#define CLKID_SYS_MSR_CLK 14
+#define CLKID_SYS_ROM 15
+#define CLKID_SYS_CPU_ARB 16
+#define CLKID_SYS_RSA 17
+#define CLKID_SYS_SARADC 18
+#define CLKID_SYS_STARTUP 19
+#define CLKID_SYS_SECURE 20
+#define CLKID_SYS_SPIFC 21
+#define CLKID_SYS_LED_CTRL 22
+#define CLKID_SYS_ETH_PHY 23
+#define CLKID_SYS_ETH_MAC 24
+#define CLKID_SYS_RAMA 25
+#define CLKID_SYS_RAMB 26
+#define CLKID_SYS_AUDIO_TOP 27
+#define CLKID_SYS_AUDIO_VAD 28
+#define CLKID_SYS_USB 29
+#define CLKID_SYS_SD_EMMC_A 30
+#define CLKID_SYS_SD_EMMC_C 31
+#define CLKID_SYS_PWM_AB 32
+#define CLKID_SYS_PWM_CD 33
+#define CLKID_SYS_PWM_EF 34
+#define CLKID_SYS_PWM_GH 35
+#define CLKID_SYS_SPICC_1 36
+#define CLKID_SYS_SPICC_0 37
+#define CLKID_SYS_UART_A 38
+#define CLKID_SYS_UART_B 39
+#define CLKID_SYS_UART_C 40
+#define CLKID_SYS_UART_D 41
+#define CLKID_SYS_UART_E 42
+#define CLKID_SYS_I2C_M_A 43
+#define CLKID_SYS_I2C_M_B 44
+#define CLKID_SYS_I2C_M_C 45
+#define CLKID_SYS_I2C_M_D 46
+#define CLKID_SYS_RTC 47
+#define CLKID_SYS_VOUT 48
+#define CLKID_SYS_ACODEC 49
+#define CLKID_SYS_USB_CTRL 50
+#define CLKID_AXI_AUDIO_VAD 51
+#define CLKID_AXI_AUDIO_TOP 52
+#define CLKID_AXI_RAMA 53
+#define CLKID_AXI_DEV1_DMC 54
+#define CLKID_AXI_DEV0_DMC 55
+#define CLKID_AXI_DSP_DMC 56
+#define CLKID_12_24M_IN 57
+#define CLKID_12M_24M 58
+#define CLKID_FCLK_25M_DIV 59
+#define CLKID_FCLK_25M 60
+#define CLKID_GEN_SEL 61
+#define CLKID_GEN_DIV 62
+#define CLKID_GEN 63
+#define CLKID_SARADC_SEL 64
+#define CLKID_SARADC_DIV 65
+#define CLKID_SARADC 66
+#define CLKID_PWM_A_SEL 67
+#define CLKID_PWM_A_DIV 68
+#define CLKID_PWM_A 69
+#define CLKID_PWM_B_SEL 70
+#define CLKID_PWM_B_DIV 71
+#define CLKID_PWM_B 72
+#define CLKID_PWM_C_SEL 73
+#define CLKID_PWM_C_DIV 74
+#define CLKID_PWM_C 75
+#define CLKID_PWM_D_SEL 76
+#define CLKID_PWM_D_DIV 77
+#define CLKID_PWM_D 78
+#define CLKID_PWM_E_SEL 79
+#define CLKID_PWM_E_DIV 80
+#define CLKID_PWM_E 81
+#define CLKID_PWM_F_SEL 82
+#define CLKID_PWM_F_DIV 83
+#define CLKID_PWM_F 84
+#define CLKID_PWM_G_SEL 85
+#define CLKID_PWM_G_DIV 86
+#define CLKID_PWM_G 87
+#define CLKID_PWM_H_SEL 88
+#define CLKID_PWM_H_DIV 89
+#define CLKID_PWM_H 90
+#define CLKID_SPICC_0_SEL 91
+#define CLKID_SPICC_0_DIV 92
+#define CLKID_SPICC_0 93
+#define CLKID_SPICC_1_SEL 94
+#define CLKID_SPICC_1_DIV 95
+#define CLKID_SPICC_1 96
+#define CLKID_SD_EMMC_A_SEL 97
+#define CLKID_SD_EMMC_A_DIV 98
+#define CLKID_SD_EMMC_A 99
+#define CLKID_SD_EMMC_C_SEL 100
+#define CLKID_SD_EMMC_C_DIV 101
+#define CLKID_SD_EMMC_C 102
+#define CLKID_TS_DIV 103
+#define CLKID_TS 104
+#define CLKID_ETH_125M_DIV 105
+#define CLKID_ETH_125M 106
+#define CLKID_ETH_RMII_DIV 107
+#define CLKID_ETH_RMII 108
+#define CLKID_VOUT_MCLK_SEL 109
+#define CLKID_VOUT_MCLK_DIV 110
+#define CLKID_VOUT_MCLK 111
+#define CLKID_VOUT_ENC_SEL 112
+#define CLKID_VOUT_ENC_DIV 113
+#define CLKID_VOUT_ENC 114
+#define CLKID_AUDIO_CORE_SEL 115
+#define CLKID_AUDIO_CORE_DIV 116
+#define CLKID_AUDIO_CORE 117
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A4_PERIPHERALS_CLKC_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 04/19] clk: amlogic: Optimize PLL enable timing
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (2 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals " Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 05/19] clk: amlogic: Correct l_detect bit control Chuan Liu via B4 Relay
` (16 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Amlogic PLL locking procedure shall follow this timing sequence:
1 Assert reset signal: Ensures PLL circuits enter known initial state.
2 Deassert lock-detect signal: Avoid lock signal false triggering.
3 Assert enable signal: Powers up PLL supply.
4 udelay(20): Wait for Bandgap and LDO to power up and stabilize.
5 Enable self-adaptation current module (Optional).
6 Deassert reset signal: Releases PLL to begin normal operation.
7 udelay(20): Wait for PLL loop stabilization.
8 Assert lock-detect signal: lock detection circuit starts to work.
9 Monitor lock status signal: Wait for PLL lock completion.
10 If the PLL fails to lock, it should be disabled, This makes the
logic more complete, and also helps save unnecessary power consumption
when the PLL is malfunctioning.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/clk-pll.c | 68 ++++++++++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 28 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 1ea6579a760f..8bddd44d4738 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -353,6 +353,23 @@ static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
return -EIO;
}
+static void meson_clk_pll_disable(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+
+ /* Put the pll is in reset */
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 1);
+
+ /* Disable the pll */
+ meson_parm_write(clk->map, &pll->en, 0);
+
+ /* Disable PLL internal self-adaption current module */
+ if (MESON_PARM_APPLICABLE(&pll->current_en))
+ meson_parm_write(clk->map, &pll->current_en, 0);
+}
+
static int meson_clk_pll_enable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
@@ -366,53 +383,48 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
+ /* Disable the PLL lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
-
- /* Take the pll out reset */
- if (MESON_PARM_APPLICABLE(&pll->rst))
- meson_parm_write(clk->map, &pll->rst, 0);
+ /* Wait for Bandgap and LDO to power up and stabilize */
+ udelay(20);
/*
* Compared with the previous SoCs, self-adaption current module
* is newly added for A1, keep the new power-on sequence to enable the
* PLL. The sequence is:
- * 1. enable the pll, delay for 10us
+ * 1. enable the pll, ensure a minimum delay of 10μs
* 2. enable the pll self-adaption current module, delay for 40us
* 3. enable the lock detect module
*/
if (MESON_PARM_APPLICABLE(&pll->current_en)) {
- udelay(10);
meson_parm_write(clk->map, &pll->current_en, 1);
- udelay(40);
- }
-
- if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
- meson_parm_write(clk->map, &pll->l_detect, 1);
- meson_parm_write(clk->map, &pll->l_detect, 0);
+ udelay(20);
}
- if (meson_clk_pll_wait_lock(hw))
- return -EIO;
+ /* Take the pll out reset */
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 0);
- return 0;
-}
+ /* Wait for PLL loop stabilization */
+ udelay(20);
-static void meson_clk_pll_disable(struct clk_hw *hw)
-{
- struct clk_regmap *clk = to_clk_regmap(hw);
- struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+ /* Enable the lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
+ meson_parm_write(clk->map, &pll->l_detect, 0);
- /* Put the pll is in reset */
- if (MESON_PARM_APPLICABLE(&pll->rst))
- meson_parm_write(clk->map, &pll->rst, 1);
+ if (meson_clk_pll_wait_lock(hw)) {
+ /* disable PLL when PLL lock failed. */
+ meson_clk_pll_disable(hw);
+ pr_warn("%s: PLL lock failed!!!\n", clk_hw_get_name(hw));
- /* Disable the pll */
- meson_parm_write(clk->map, &pll->en, 0);
+ return -EIO;
+ }
- /* Disable PLL internal self-adaption current module */
- if (MESON_PARM_APPLICABLE(&pll->current_en))
- meson_parm_write(clk->map, &pll->current_en, 0);
+ return 0;
}
static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 05/19] clk: amlogic: Correct l_detect bit control
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (3 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 04/19] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
` (15 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
l_detect controls the enable/disable of the PLL lock-detect module.
For A1, the l_detect signal is active-low:
0 -> Enable lock-detect module;
1 -> Disable lock-detect module.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/a1-pll.c | 1 +
drivers/clk/meson/clk-pll.c | 16 ++++++++++++----
drivers/clk/meson/clk-pll.h | 2 ++
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index 1f82e9c7c14e..bfe559c71402 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -137,6 +137,7 @@ static struct clk_regmap a1_hifi_pll = {
.range = &a1_hifi_pll_range,
.init_regs = a1_hifi_pll_init_regs,
.init_count = ARRAY_SIZE(a1_hifi_pll_init_regs),
+ .flags = CLK_MESON_PLL_L_DETECT_N
},
.hw.init = &(struct clk_init_data){
.name = "hifi_pll",
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 8bddd44d4738..c1e4c5710015 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -384,8 +384,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
meson_parm_write(clk->map, &pll->rst, 1);
/* Disable the PLL lock-detect module */
- if (MESON_PARM_APPLICABLE(&pll->l_detect))
- meson_parm_write(clk->map, &pll->l_detect, 1);
+ if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
+ if (pll->flags & CLK_MESON_PLL_L_DETECT_N)
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+ else
+ meson_parm_write(clk->map, &pll->l_detect, 0);
+ }
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
@@ -413,8 +417,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
udelay(20);
/* Enable the lock-detect module */
- if (MESON_PARM_APPLICABLE(&pll->l_detect))
- meson_parm_write(clk->map, &pll->l_detect, 0);
+ if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
+ if (pll->flags & CLK_MESON_PLL_L_DETECT_N)
+ meson_parm_write(clk->map, &pll->l_detect, 0);
+ else
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+ }
if (meson_clk_pll_wait_lock(hw)) {
/* disable PLL when PLL lock failed. */
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 949157fb7bf5..83295a24721f 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -29,6 +29,8 @@ struct pll_mult_range {
#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
#define CLK_MESON_PLL_NOINIT_ENABLED BIT(1)
+/* l_detect signal is active-low */
+#define CLK_MESON_PLL_L_DETECT_N BIT(2)
struct meson_clk_pll_data {
struct parm en;
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (4 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 05/19] clk: amlogic: Correct l_detect bit control Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver Chuan Liu via B4 Relay
` (14 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
meson_clk_get_pll_range_index incorrectly determines the maximum value
of 'm'.
Fixes: 8eed1db1adec6 ("clk: meson: pll: update driver for the g12a")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index c1e4c5710015..602c93aba3cc 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -191,7 +191,7 @@ static int meson_clk_get_pll_range_index(unsigned long rate,
*m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
/* the pre-divider gives a multiplier too big - stop */
- if (*m >= (1 << pll->m.width))
+ if (*m > pll->range->max)
return -EINVAL;
return 0;
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (5 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 08/19] clk: amlogic: Add A4 clock peripherals " Chuan Liu via B4 Relay
` (13 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the PLL clock controller driver for the Amlogic A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/Kconfig | 13 +++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a4-pll.c | 242 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 256 insertions(+)
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 71481607a6d5..2339abfa2c4e 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -132,6 +132,19 @@ config COMMON_CLK_A1_PERIPHERALS
device, A1 SoC Family. Say Y if you want A1 Peripherals clock
controller to work.
+config COMMON_CLK_A4_PLL
+ tristate "Amlogic A4 PLL clock controller"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_PLL
+ select COMMON_CLK_MESON_CLKC_UTILS
+ imply COMMON_CLK_SCMI
+ help
+ Support for the PLL clock controller on Amlogic BA40X device, AKA A4.
+ Say Y if you want the board to work, because PLLs are the parent
+ of most peripherals.
+
config COMMON_CLK_C3_PLL
tristate "Amlogic C3 PLL clock controller"
depends on ARM64
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index c6998e752c68..22312393663f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
+obj-$(CONFIG_COMMON_CLK_A4_PLL) += a4-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/a4-pll.c b/drivers/clk/meson/a4-pll.c
new file mode 100644
index 000000000000..b77d4f610843
--- /dev/null
+++ b/drivers/clk/meson/a4-pll.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Amlogic A4 PLL Controller Driver
+ *
+ * Copyright (c) 2025 Amlogic, inc.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,a4-pll-clkc.h>
+
+#define GP0PLL_CTRL0 0x80
+#define GP0PLL_CTRL1 0x84
+#define GP0PLL_CTRL2 0x88
+#define GP0PLL_CTRL3 0x8c
+#define HIFIPLL_CTRL0 0x100
+#define HIFIPLL_CTRL1 0x104
+#define HIFIPLL_CTRL2 0x108
+#define HIFIPLL_CTRL3 0x10c
+
+static const struct reg_sequence a4_gp0_init_regs[] = {
+ { .reg = GP0PLL_CTRL1, .def = 0x03a00000 },
+ { .reg = GP0PLL_CTRL2, .def = 0x00040000 },
+ { .reg = GP0PLL_CTRL3, .def = 0x090da200 }
+};
+
+static const struct pll_mult_range a4_gp0_pll_mult_range = {
+ .min = 67,
+ .max = 133,
+};
+
+static struct clk_regmap a4_gp0_pll_dco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 0,
+ .width = 9,
+ },
+ .frac = {
+ .reg_off = GP0PLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .n = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .l_detect = {
+ .reg_off = GP0PLL_CTRL3,
+ .shift = 9,
+ .width = 1,
+ },
+ .range = &a4_gp0_pll_mult_range,
+ .init_regs = a4_gp0_init_regs,
+ .init_count = ARRAY_SIZE(a4_gp0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp0_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+/* The maximum frequency divider supports is 16, not 128(2^7) */
+static const struct clk_div_table a4_gp0_pll_od_table[] = {
+ { 0, 1 },
+ { 1, 2 },
+ { 2, 4 },
+ { 3, 8 },
+ { 4, 16 },
+ { /* sentinel */ }
+};
+
+static struct clk_regmap a4_gp0_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = GP0PLL_CTRL0,
+ .shift = 10,
+ .width = 3,
+ .table = a4_gp0_pll_od_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp0_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_gp0_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence a4_hifi_init_regs[] = {
+ { .reg = HIFIPLL_CTRL1, .def = 0x03a00000 },
+ { .reg = HIFIPLL_CTRL2, .def = 0x00040000 },
+ { .reg = HIFIPLL_CTRL3, .def = 0x0a0da200 }
+};
+
+static const struct pll_mult_range a4_hifi_pll_mult_range = {
+ .min = 67,
+ .max = 133,
+};
+
+static struct clk_regmap a4_hifi_pll_dco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .frac = {
+ .reg_off = HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .n = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .l_detect = {
+ .reg_off = HIFIPLL_CTRL3,
+ .shift = 9,
+ .width = 1,
+ },
+ .range = &a4_hifi_pll_mult_range,
+ .init_regs = a4_hifi_init_regs,
+ .init_count = ARRAY_SIZE(a4_hifi_init_regs),
+ .frac_max = 100000,
+ .flags = CLK_MESON_PLL_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+/* The maximum frequency divider supports is 16, not 128(2^7) */
+static const struct clk_div_table a4_hifi_pll_od_table[] = {
+ { 0, 1 },
+ { 1, 2 },
+ { 2, 4 },
+ { 3, 8 },
+ { 4, 16 },
+ { /* sentinel */ }
+};
+
+static struct clk_regmap a4_hifi_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 3,
+ .table = a4_hifi_pll_od_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_hifi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_hw *a4_pll_hw_clks[] = {
+ [CLKID_GP0_PLL_DCO] = &a4_gp0_pll_dco.hw,
+ [CLKID_GP0_PLL] = &a4_gp0_pll.hw,
+ [CLKID_HIFI_PLL_DCO] = &a4_hifi_pll_dco.hw,
+ [CLKID_HIFI_PLL] = &a4_hifi_pll.hw
+};
+
+static const struct meson_clkc_data a4_pll_clkc_data = {
+ .hw_clks = {
+ .hws = a4_pll_hw_clks,
+ .num = ARRAY_SIZE(a4_pll_hw_clks),
+ },
+};
+
+static const struct of_device_id a4_pll_clkc_match_table[] = {
+ {
+ .compatible = "amlogic,a4-pll-clkc",
+ .data = &a4_pll_clkc_data,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, a4_pll_clkc_match_table);
+
+static struct platform_driver a4_pll_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "a4-pll-clkc",
+ .of_match_table = a4_pll_clkc_match_table,
+ },
+};
+module_platform_driver(a4_pll_clkc_driver);
+
+MODULE_DESCRIPTION("Amlogic A4 PLL Clock Controller driver");
+MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 08/19] clk: amlogic: Add A4 clock peripherals controller driver
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (6 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node Chuan Liu via B4 Relay
` (12 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the peripherals clock controller driver for the Amlogic A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/Kconfig | 13 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a4-peripherals.c | 764 +++++++++++++++++++++++++++++++++++++
3 files changed, 778 insertions(+)
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 2339abfa2c4e..860625ca6e9b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -145,6 +145,19 @@ config COMMON_CLK_A4_PLL
Say Y if you want the board to work, because PLLs are the parent
of most peripherals.
+config COMMON_CLK_A4_PERIPHERALS
+ tristate "Amlogic A4 peripherals clock controller"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_CLKC_UTILS
+ imply COMMON_CLK_SCMI
+ imply COMMON_CLK_A4_PLL
+ help
+ Support for the Peripherals clock controller on Amlogic BA40X device,
+ AKA A4. Say Y if you want the peripherals clock to work.
+
config COMMON_CLK_C3_PLL
tristate "Amlogic C3 PLL clock controller"
depends on ARM64
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 22312393663f..88f6b336a6ca 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
obj-$(CONFIG_COMMON_CLK_A4_PLL) += a4-pll.o
+obj-$(CONFIG_COMMON_CLK_A4_PERIPHERALS) += a4-peripherals.o
obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/a4-peripherals.c b/drivers/clk/meson/a4-peripherals.c
new file mode 100644
index 000000000000..188a61f71653
--- /dev/null
+++ b/drivers/clk/meson/a4-peripherals.c
@@ -0,0 +1,764 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Amlogic A4 Peripherals Clock Controller Driver
+ *
+ * Copyright (c) 2025 Amlogic, inc.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-regmap.h"
+#include "clk-dualdiv.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,a4-peripherals-clkc.h>
+
+#define RTC_BY_OSCIN_CTRL0 0x8
+#define RTC_BY_OSCIN_CTRL1 0xc
+#define RTC_CTRL 0x10
+#define SYS_CLK_EN0_REG0 0x44
+#define SYS_CLK_EN0_REG1 0x48
+#define CLK12_24_CTRL 0xa8
+#define AXI_CLK_EN0 0xac
+#define TS_CLK_CTRL 0x158
+#define ETH_CLK_CTRL 0x164
+#define NAND_CLK_CTRL 0x168
+#define SD_EMMC_CLK_CTRL 0x16c
+#define SPICC_CLK_CTRL 0x174
+#define GEN_CLK_CTRL 0x178
+#define SAR_CLK_CTRL0 0x17c
+#define PWM_CLK_AB_CTRL 0x180
+#define PWM_CLK_CD_CTRL 0x184
+#define PWM_CLK_EF_CTRL 0x188
+#define PWM_CLK_GH_CTRL 0x18c
+#define VOUTENC_CLK_CTRL 0x204
+#define AUDIO_CLK_CTRL 0x208
+
+static struct clk_regmap a4_rtc_dualdiv_clkin = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "oscin",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param a4_rtc_dualdiv_table[] = {
+ { 733, 732, 8, 11, 1 },
+ { /* sentinel */ }
+};
+
+static struct clk_regmap a4_rtc_dualdiv = {
+ .data = &(struct meson_clk_dualdiv_data) {
+ .n1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = a4_rtc_dualdiv_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_rtc_dualdiv_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data a4_rtc_dualdiv_parent_data[] = {
+ { .hw = &a4_rtc_dualdiv.hw },
+ { .hw = &a4_rtc_dualdiv_clkin.hw }
+};
+
+static struct clk_regmap a4_rtc_dualdiv_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_BY_OSCIN_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = a4_rtc_dualdiv_parent_data,
+ .num_parents = ARRAY_SIZE(a4_rtc_dualdiv_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a4_rtc_dualdiv_clkout = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv_clkout",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_rtc_dualdiv_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data a4_rtc_clk_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .hw = &a4_rtc_dualdiv_clkout.hw },
+ { .fw_name = "pad_osc" }
+};
+
+static struct clk_regmap a4_rtc_clk = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x3,
+ .shift = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_clk",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = a4_rtc_clk_parent_data,
+ .num_parents = ARRAY_SIZE(a4_rtc_clk_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+#define A4_PCLK(_name, _reg, _bit, _pdata, _flags) \
+struct clk_regmap a4_##_name = { \
+ .data = &(struct clk_regmap_gate_data) { \
+ .offset = (_reg), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) { \
+ .name = #_name, \
+ .ops = &clk_regmap_gate_ops, \
+ .parent_data = (_pdata), \
+ .num_parents = 1, \
+ .flags = (_flags), \
+ }, \
+}
+
+static const struct clk_parent_data a4_sys_pclk_parents = { .fw_name = "sysclk" };
+
+#define A4_SYS_PCLK(_name, _reg, _bit, _flags) \
+ A4_PCLK(_name, _reg, _bit, &a4_sys_pclk_parents, _flags)
+
+static A4_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
+static A4_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
+static A4_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0);
+static A4_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0);
+static A4_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0);
+
+/*
+ * NOTE: sys_dev_arb provides the clock to the SPICC0 and SPICC1 arbiters that
+ * access the AXI bus.
+ */
+static A4_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0);
+static A4_SYS_PCLK(sys_mailbox, SYS_CLK_EN0_REG0, 10, 0);
+static A4_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0);
+static A4_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0);
+static A4_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0);
+static A4_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0);
+static A4_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0);
+static A4_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0);
+static A4_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG0, 20, 0);
+static A4_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0);
+static A4_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0);
+static A4_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0);
+static A4_SYS_PCLK(sys_led_ctrl, SYS_CLK_EN0_REG0, 24, 0);
+static A4_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG0, 25, 0);
+static A4_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0);
+static A4_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0);
+static A4_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0);
+static A4_SYS_PCLK(sys_audio_top, SYS_CLK_EN0_REG1, 0, 0);
+static A4_SYS_PCLK(sys_audio_vad, SYS_CLK_EN0_REG1, 1, 0);
+static A4_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0);
+static A4_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0);
+static A4_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0);
+static A4_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0);
+static A4_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0);
+static A4_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0);
+static A4_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0);
+static A4_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0);
+static A4_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0);
+static A4_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0);
+static A4_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0);
+static A4_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0);
+static A4_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0);
+static A4_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0);
+static A4_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0);
+static A4_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0);
+static A4_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0);
+static A4_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0);
+static A4_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0);
+static A4_SYS_PCLK(sys_vout, SYS_CLK_EN0_REG1, 22, 0);
+static A4_SYS_PCLK(sys_usb_ctrl, SYS_CLK_EN0_REG1, 26, 0);
+static A4_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG1, 27, 0);
+
+static const struct clk_parent_data a4_axi_clk_parents = { .fw_name = "axiclk" };
+
+#define A4_AXI_CLK(_name, _reg, _bit, _flags) \
+ A4_PCLK(_name, _reg, _bit, &a4_axi_clk_parents, _flags)
+
+static A4_AXI_CLK(axi_audio_vad, AXI_CLK_EN0, 0, 0);
+static A4_AXI_CLK(axi_audio_top, AXI_CLK_EN0, 1, 0);
+static A4_AXI_CLK(axi_rama, AXI_CLK_EN0, 6, 0);
+
+/*
+ * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO,
+ * sec_top, USB, Audio) to access the AXI bus of the DDR.
+ */
+static A4_AXI_CLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0);
+
+/*
+ * NOTE: axi_dev0_dmc provides the clock for the peripherals(ETH and SPICC)
+ * to access the AXI bus of the DDR.
+ */
+static A4_AXI_CLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0);
+static A4_AXI_CLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0);
+
+static struct clk_regmap a4_clk_12_24m_in = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "clk_12_24m_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a4_clk_12_24m = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLK12_24_CTRL,
+ .shift = 10,
+ .width = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "clk_12_24m",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_clk_12_24m_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a4_fclk_25m_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLK12_24_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_25m_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fix",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a4_fclk_25m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 12,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_25m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_fclk_25m_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; channel 12(cts_msr_clk)
+ * is manged by clock measures module. Their hardware are out of clock tree.
+ * Channel 4 5 8 9 10 11 13 14 15 16 18 are not connected.
+ */
+static u32 a4_gen_parent_table[] = { 0, 1, 2, 6, 7, 17, 19, 20, 21, 22, 23, 24};
+
+static const struct clk_parent_data gen_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .hw = &a4_rtc_clk.hw },
+ { .fw_name = "sysplldiv16" },
+ { .fw_name = "gp1" },
+ { .fw_name = "hifi" },
+ { .fw_name = "cpudiv16" },
+ { .fw_name = "fdiv2" },
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv5" },
+ { .fw_name = "fdiv7" }
+};
+
+static struct clk_regmap a4_gen_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = GEN_CLK_CTRL,
+ .mask = 0x1f,
+ .shift = 12,
+ .table = a4_gen_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gen_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = gen_parent_data,
+ .num_parents = ARRAY_SIZE(gen_parent_data),
+ },
+};
+
+static struct clk_regmap a4_gen_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = GEN_CLK_CTRL,
+ .shift = 0,
+ .width = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gen_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_gen_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a4_gen = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = GEN_CLK_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gen",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_gen_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+#define A4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
+ MESON_COMP_SEL(a4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
+
+#define A4_COMP_DIV(_name, _reg, _shift, _width) \
+ MESON_COMP_DIV(a4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
+
+#define A4_COMP_GATE(_name, _reg, _bit) \
+ MESON_COMP_GATE(a4_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
+
+static const struct clk_parent_data a4_saradc_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "sysclk" }
+};
+
+static A4_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x3, a4_saradc_parent_data);
+static A4_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
+static A4_COMP_GATE(saradc, SAR_CLK_CTRL0, 8);
+
+static const struct clk_parent_data a4_pwm_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .hw = &a4_rtc_clk.hw },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv3" }
+};
+
+static A4_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
+static A4_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
+
+static A4_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
+static A4_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
+
+static A4_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
+static A4_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
+
+static A4_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
+static A4_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
+
+static A4_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
+static A4_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
+
+static A4_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
+static A4_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
+
+static A4_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8);
+static A4_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
+
+static A4_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, a4_pwm_parent_data);
+static A4_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8);
+static A4_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
+
+static const struct clk_parent_data a4_spicc_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "sysclk" },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "fdiv2" },
+ { .fw_name = "fdiv5" },
+ { .fw_name = "fdiv7" },
+ { .fw_name = "gp1" }
+};
+
+static A4_COMP_SEL(spicc_0, SPICC_CLK_CTRL, 7, 0x7, a4_spicc_parent_data);
+static A4_COMP_DIV(spicc_0, SPICC_CLK_CTRL, 0, 6);
+static A4_COMP_GATE(spicc_0, SPICC_CLK_CTRL, 6);
+
+static A4_COMP_SEL(spicc_1, SPICC_CLK_CTRL, 23, 0x7, a4_spicc_parent_data);
+static A4_COMP_DIV(spicc_1, SPICC_CLK_CTRL, 16, 6);
+static A4_COMP_GATE(spicc_1, SPICC_CLK_CTRL, 22);
+
+#define A4_COMP_SEL_WITH_TAB(_name, _reg, _shift, _mask, _pdata, _table) \
+ MESON_COMP_SEL(a4_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0)
+
+/* Channel 5 6 are not connected. */
+static u32 a4_sd_emmc_parent_table[] = { 0, 1, 2, 3, 4, 7};
+
+static const struct clk_parent_data a4_sd_emmc_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "fdiv2" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "hifi" },
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "gp0" }
+};
+
+static A4_COMP_SEL_WITH_TAB(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7,
+ a4_sd_emmc_parent_data, a4_sd_emmc_parent_table);
+static A4_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
+static A4_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7);
+
+static A4_COMP_SEL_WITH_TAB(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7,
+ a4_sd_emmc_parent_data, a4_sd_emmc_parent_table);
+static A4_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
+static A4_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7);
+
+static struct clk_regmap a4_ts_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = TS_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ts_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "oscin",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a4_ts = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = TS_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ts",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_ts_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor a4_eth_125m_div = {
+ .mult = 1,
+ .div = 8,
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_125m_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fdiv2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a4_eth_125m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_125m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_eth_125m_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a4_eth_rmii_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ETH_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_rmii_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fdiv2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a4_eth_rmii = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_rmii",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a4_eth_rmii_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data a4_vout_mclk_parent_data[] = {
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv5" },
+ { .fw_name = "gp0" },
+ { .fw_name = "hifi" },
+ { .fw_name = "gp1" },
+ { .fw_name = "fdiv7" }
+};
+
+static A4_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7,
+ a4_vout_mclk_parent_data);
+static A4_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7);
+static A4_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8);
+
+static const struct clk_parent_data a4_vout_enc_parent_data[] = {
+ { .fw_name = "gp1" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv5" },
+ { .fw_name = "gp0" },
+ { .fw_name = "hifi" },
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "fdiv7" }
+};
+
+static A4_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7,
+ a4_vout_enc_parent_data);
+static A4_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7);
+static A4_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24);
+
+static const struct clk_parent_data a4_audio_core_parent_data[] = {
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "gp1" }
+};
+
+static A4_COMP_SEL(audio_core, AUDIO_CLK_CTRL, 9, 0x3,
+ a4_audio_core_parent_data);
+static A4_COMP_DIV(audio_core, AUDIO_CLK_CTRL, 0, 8);
+static A4_COMP_GATE(audio_core, AUDIO_CLK_CTRL, 8);
+
+static struct clk_hw *a4_peripherals_hw_clks[] = {
+ [CLKID_RTC_DUALDIV_CLKIN] = &a4_rtc_dualdiv_clkin.hw,
+ [CLKID_RTC_DUALDIV] = &a4_rtc_dualdiv.hw,
+ [CLKID_RTC_DUALDIV_SEL] = &a4_rtc_dualdiv_sel.hw,
+ [CLKID_RTC_DUALDIV_CLKOUT] = &a4_rtc_dualdiv_clkout.hw,
+ [CLKID_RTC_CLK] = &a4_rtc_clk.hw,
+ [CLKID_SYS_RESET_CTRL] = &a4_sys_reset_ctrl.hw,
+ [CLKID_SYS_PWR_CTRL] = &a4_sys_pwr_ctrl.hw,
+ [CLKID_SYS_PAD_CTRL] = &a4_sys_pad_ctrl.hw,
+ [CLKID_SYS_CTRL] = &a4_sys_ctrl.hw,
+ [CLKID_SYS_TS_PLL] = &a4_sys_ts_pll.hw,
+ [CLKID_SYS_DEV_ARB] = &a4_sys_dev_arb.hw,
+ [CLKID_SYS_MAILBOX] = &a4_sys_mailbox.hw,
+ [CLKID_SYS_JTAG_CTRL] = &a4_sys_jtag_ctrl.hw,
+ [CLKID_SYS_IR_CTRL] = &a4_sys_ir_ctrl.hw,
+ [CLKID_SYS_MSR_CLK] = &a4_sys_msr_clk.hw,
+ [CLKID_SYS_ROM] = &a4_sys_rom.hw,
+ [CLKID_SYS_CPU_ARB] = &a4_sys_cpu_apb.hw,
+ [CLKID_SYS_RSA] = &a4_sys_rsa.hw,
+ [CLKID_SYS_SARADC] = &a4_sys_saradc.hw,
+ [CLKID_SYS_STARTUP] = &a4_sys_startup.hw,
+ [CLKID_SYS_SECURE] = &a4_sys_secure.hw,
+ [CLKID_SYS_SPIFC] = &a4_sys_spifc.hw,
+ [CLKID_SYS_LED_CTRL] = &a4_sys_led_ctrl.hw,
+ [CLKID_SYS_ETH_PHY] = &a4_sys_eth_phy.hw,
+ [CLKID_SYS_ETH_MAC] = &a4_sys_eth_mac.hw,
+ [CLKID_SYS_RAMA] = &a4_sys_rama.hw,
+ [CLKID_SYS_RAMB] = &a4_sys_ramb.hw,
+ [CLKID_SYS_AUDIO_TOP] = &a4_sys_audio_top.hw,
+ [CLKID_SYS_AUDIO_VAD] = &a4_sys_audio_vad.hw,
+ [CLKID_SYS_USB] = &a4_sys_usb.hw,
+ [CLKID_SYS_SD_EMMC_A] = &a4_sys_sd_emmc_a.hw,
+ [CLKID_SYS_SD_EMMC_C] = &a4_sys_sd_emmc_c.hw,
+ [CLKID_SYS_PWM_AB] = &a4_sys_pwm_ab.hw,
+ [CLKID_SYS_PWM_CD] = &a4_sys_pwm_cd.hw,
+ [CLKID_SYS_PWM_EF] = &a4_sys_pwm_ef.hw,
+ [CLKID_SYS_PWM_GH] = &a4_sys_pwm_gh.hw,
+ [CLKID_SYS_SPICC_1] = &a4_sys_spicc_1.hw,
+ [CLKID_SYS_SPICC_0] = &a4_sys_spicc_0.hw,
+ [CLKID_SYS_UART_A] = &a4_sys_uart_a.hw,
+ [CLKID_SYS_UART_B] = &a4_sys_uart_b.hw,
+ [CLKID_SYS_UART_C] = &a4_sys_uart_c.hw,
+ [CLKID_SYS_UART_D] = &a4_sys_uart_d.hw,
+ [CLKID_SYS_UART_E] = &a4_sys_uart_e.hw,
+ [CLKID_SYS_I2C_M_A] = &a4_sys_i2c_m_a.hw,
+ [CLKID_SYS_I2C_M_B] = &a4_sys_i2c_m_b.hw,
+ [CLKID_SYS_I2C_M_C] = &a4_sys_i2c_m_c.hw,
+ [CLKID_SYS_I2C_M_D] = &a4_sys_i2c_m_d.hw,
+ [CLKID_SYS_RTC] = &a4_sys_rtc.hw,
+ [CLKID_SYS_VOUT] = &a4_sys_vout.hw,
+ [CLKID_SYS_USB_CTRL] = &a4_sys_usb_ctrl.hw,
+ [CLKID_SYS_ACODEC] = &a4_sys_acodec.hw,
+ [CLKID_AXI_AUDIO_VAD] = &a4_axi_audio_vad.hw,
+ [CLKID_AXI_AUDIO_TOP] = &a4_axi_audio_top.hw,
+ [CLKID_AXI_RAMA] = &a4_axi_rama.hw,
+ [CLKID_AXI_DEV1_DMC] = &a4_axi_dev1_dmc.hw,
+ [CLKID_AXI_DEV0_DMC] = &a4_axi_dev0_dmc.hw,
+ [CLKID_AXI_DSP_DMC] = &a4_axi_dsp_dmc.hw,
+ [CLKID_12_24M_IN] = &a4_clk_12_24m_in.hw,
+ [CLKID_12M_24M] = &a4_clk_12_24m.hw,
+ [CLKID_FCLK_25M_DIV] = &a4_fclk_25m_div.hw,
+ [CLKID_FCLK_25M] = &a4_fclk_25m.hw,
+ [CLKID_GEN_SEL] = &a4_gen_sel.hw,
+ [CLKID_GEN_DIV] = &a4_gen_div.hw,
+ [CLKID_GEN] = &a4_gen.hw,
+ [CLKID_SARADC_SEL] = &a4_saradc_sel.hw,
+ [CLKID_SARADC_DIV] = &a4_saradc_div.hw,
+ [CLKID_SARADC] = &a4_saradc.hw,
+ [CLKID_PWM_A_SEL] = &a4_pwm_a_sel.hw,
+ [CLKID_PWM_A_DIV] = &a4_pwm_a_div.hw,
+ [CLKID_PWM_A] = &a4_pwm_a.hw,
+ [CLKID_PWM_B_SEL] = &a4_pwm_b_sel.hw,
+ [CLKID_PWM_B_DIV] = &a4_pwm_b_div.hw,
+ [CLKID_PWM_B] = &a4_pwm_b.hw,
+ [CLKID_PWM_C_SEL] = &a4_pwm_c_sel.hw,
+ [CLKID_PWM_C_DIV] = &a4_pwm_c_div.hw,
+ [CLKID_PWM_C] = &a4_pwm_c.hw,
+ [CLKID_PWM_D_SEL] = &a4_pwm_d_sel.hw,
+ [CLKID_PWM_D_DIV] = &a4_pwm_d_div.hw,
+ [CLKID_PWM_D] = &a4_pwm_d.hw,
+ [CLKID_PWM_E_SEL] = &a4_pwm_e_sel.hw,
+ [CLKID_PWM_E_DIV] = &a4_pwm_e_div.hw,
+ [CLKID_PWM_E] = &a4_pwm_e.hw,
+ [CLKID_PWM_F_SEL] = &a4_pwm_f_sel.hw,
+ [CLKID_PWM_F_DIV] = &a4_pwm_f_div.hw,
+ [CLKID_PWM_F] = &a4_pwm_f.hw,
+ [CLKID_PWM_G_SEL] = &a4_pwm_g_sel.hw,
+ [CLKID_PWM_G_DIV] = &a4_pwm_g_div.hw,
+ [CLKID_PWM_G] = &a4_pwm_g.hw,
+ [CLKID_PWM_H_SEL] = &a4_pwm_h_sel.hw,
+ [CLKID_PWM_H_DIV] = &a4_pwm_h_div.hw,
+ [CLKID_PWM_H] = &a4_pwm_h.hw,
+ [CLKID_SPICC_0_SEL] = &a4_spicc_0_sel.hw,
+ [CLKID_SPICC_0_DIV] = &a4_spicc_0_div.hw,
+ [CLKID_SPICC_0] = &a4_spicc_0.hw,
+ [CLKID_SPICC_1_SEL] = &a4_spicc_1_sel.hw,
+ [CLKID_SPICC_1_DIV] = &a4_spicc_1_div.hw,
+ [CLKID_SPICC_1] = &a4_spicc_1.hw,
+ [CLKID_SD_EMMC_A_SEL] = &a4_sd_emmc_a_sel.hw,
+ [CLKID_SD_EMMC_A_DIV] = &a4_sd_emmc_a_div.hw,
+ [CLKID_SD_EMMC_A] = &a4_sd_emmc_a.hw,
+ [CLKID_SD_EMMC_C_SEL] = &a4_sd_emmc_c_sel.hw,
+ [CLKID_SD_EMMC_C_DIV] = &a4_sd_emmc_c_div.hw,
+ [CLKID_SD_EMMC_C] = &a4_sd_emmc_c.hw,
+ [CLKID_TS_DIV] = &a4_ts_div.hw,
+ [CLKID_TS] = &a4_ts.hw,
+ [CLKID_ETH_125M_DIV] = &a4_eth_125m_div.hw,
+ [CLKID_ETH_125M] = &a4_eth_125m.hw,
+ [CLKID_ETH_RMII_DIV] = &a4_eth_rmii_div.hw,
+ [CLKID_ETH_RMII] = &a4_eth_rmii.hw,
+ [CLKID_VOUT_MCLK_SEL] = &a4_vout_mclk_sel.hw,
+ [CLKID_VOUT_MCLK_DIV] = &a4_vout_mclk_div.hw,
+ [CLKID_VOUT_MCLK] = &a4_vout_mclk.hw,
+ [CLKID_VOUT_ENC_SEL] = &a4_vout_enc_sel.hw,
+ [CLKID_VOUT_ENC_DIV] = &a4_vout_enc_div.hw,
+ [CLKID_VOUT_ENC] = &a4_vout_enc.hw,
+ [CLKID_AUDIO_CORE_SEL] = &a4_audio_core_sel.hw,
+ [CLKID_AUDIO_CORE_DIV] = &a4_audio_core_div.hw,
+ [CLKID_AUDIO_CORE] = &a4_audio_core.hw,
+};
+
+static const struct meson_clkc_data a4_peripherals_clkc_data = {
+ .hw_clks = {
+ .hws = a4_peripherals_hw_clks,
+ .num = ARRAY_SIZE(a4_peripherals_hw_clks),
+ },
+};
+
+static const struct of_device_id a4_peripherals_clkc_match_table[] = {
+ {
+ .compatible = "amlogic,a4-peripherals-clkc",
+ .data = &a4_peripherals_clkc_data,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, a4_peripherals_clkc_match_table);
+
+static struct platform_driver a4_peripherals_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "a4-peripherals-clkc",
+ .of_match_table = a4_peripherals_clkc_match_table,
+ },
+};
+module_platform_driver(a4_peripherals_clkc_driver);
+
+MODULE_DESCRIPTION("Amlogic A4 Peripherals Clock Controller driver");
+MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (7 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 08/19] clk: amlogic: Add A4 clock peripherals " Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node Chuan Liu via B4 Relay
` (11 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add scmi-clk device node information for the Amlogic A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index 563bc2e662fa..75a87f093d8d 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -49,6 +49,34 @@ pwrc: power-controller {
#power-domain-cells = <1>;
};
};
+
+ sram0: sram@f7033000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0xf7033000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xf7033000 0x100>;
+
+ scmi_buf0: scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x820000C1>;
+ shmem = <&scmi_buf0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
};
&apb {
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (8 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
` (10 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the PLL controller node for A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index 75a87f093d8d..aca81e658654 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -7,6 +7,9 @@
#include "amlogic-a4-reset.h"
#include <dt-bindings/power/amlogic,a4-pwrc.h>
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
+#include <dt-bindings/clock/amlogic,a4-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,a4-scmi-clkc.h>
+
/ {
cpus {
#address-cells = <2>;
@@ -198,6 +201,16 @@ gpio_intc: interrupt-controller@4080 {
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
+ clkc_pll: clock-controller@8000 {
+ compatible = "amlogic,a4-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x1a4>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_FIXED_PLL>;
+ clock-names = "xtal",
+ "fix";
+ };
+
ao_pinctrl: pinctrl@8e700 {
compatible = "amlogic,pinctrl-a4";
#address-cells = <2>;
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (9 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-10-07 19:33 ` kernel test robot
2025-10-10 4:21 ` kernel test robot
2025-09-30 9:37 ` [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
` (9 subsequent siblings)
20 siblings, 2 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the peripherals clock controller node for A4 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 39 +++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index aca81e658654..3404358aff58 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
#include <dt-bindings/clock/amlogic,a4-pll-clkc.h>
#include <dt-bindings/clock/amlogic,a4-scmi-clkc.h>
+#include <dt-bindings/clock/amlogic,a4-peripherals-clkc.h>
/ {
cpus {
@@ -83,6 +84,44 @@ scmi_clk: protocol@14 {
};
&apb {
+ clkc_periphs: clock-controller@0 {
+ compatible = "amlogic,a4-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x20c>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_OSC>,
+ <&scmi_clk CLKID_FIXED_PLL>,
+ <&scmi_clk CLKID_FCLK_DIV2>,
+ <&scmi_clk CLKID_FCLK_DIV2P5>,
+ <&scmi_clk CLKID_FCLK_DIV3>,
+ <&scmi_clk CLKID_FCLK_DIV4>,
+ <&scmi_clk CLKID_FCLK_DIV5>,
+ <&scmi_clk CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_GP0_PLL>,
+ <&scmi_clk CLKID_GP1_PLL>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&scmi_clk CLKID_SYS_CLK>,
+ <&scmi_clk CLKID_AXI_CLK>,
+ <&scmi_clk CLKID_SYS_PLL_DIV16>,
+ <&scmi_clk CLKID_CPU_CLK_DIV16>;
+ clock-names = "xtal",
+ "oscin",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "gp0",
+ "gp1",
+ "hifi",
+ "sysclk",s
+ "axiclk",
+ "sysplldiv16",
+ "cpudiv16";
+ };
+
reset: reset-controller@2000 {
compatible = "amlogic,a4-reset",
"amlogic,meson-s4-reset";
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (10 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
` (8 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the SCMI clock controller dt-bindings for the Amlogic A5 SoC family.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
new file mode 100644
index 000000000000..1bf027d0110a
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a5-scmi-clkc.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef __AMLOGIC_A5_SCMI_CLKC_H
+#define __AMLOGIC_A5_SCMI_CLKC_H
+
+#define CLKID_OSC 0
+#define CLKID_SYS_CLK 1
+#define CLKID_AXI_CLK 2
+#define CLKID_CPU_CLK 3
+#define CLKID_DSU_CLK 4
+#define CLKID_GP1_PLL 5
+#define CLKID_FIXED_PLL_DCO 6
+#define CLKID_FIXED_PLL 7
+#define CLKID_ACLKM 8
+#define CLKID_SYS_PLL_DIV16 9
+#define CLKID_CPU_CLK_DIV16 10
+#define CLKID_FCLK_50M_PREDIV 11
+#define CLKID_FCLK_50M_DIV 12
+#define CLKID_FCLK_50M 13
+#define CLKID_FCLK_DIV2_DIV 14
+#define CLKID_FCLK_DIV2 15
+#define CLKID_FCLK_DIV2P5_DIV 16
+#define CLKID_FCLK_DIV2P5 17
+#define CLKID_FCLK_DIV3_DIV 18
+#define CLKID_FCLK_DIV3 19
+#define CLKID_FCLK_DIV4_DIV 20
+#define CLKID_FCLK_DIV4 21
+#define CLKID_FCLK_DIV5_DIV 22
+#define CLKID_FCLK_DIV5 23
+#define CLKID_FCLK_DIV7_DIV 24
+#define CLKID_FCLK_DIV7 25
+#define CLKID_SYS_MMC_PCLK 26
+#define CLKID_SYS_CPU_CTRL 27
+#define CLKID_SYS_IRQ_CTRL 28
+#define CLKID_SYS_GIC 29
+#define CLKID_SYS_BIG_NIC 30
+#define CLKID_AXI_SYS_NIC 31
+#define CLKID_AXI_CPU_DMC 32
+
+#endif /* __AMLOGIC_A5_SCMI_CLKC_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (11 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
` (7 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the PLL clock controller dt-bindings for the Amlogic A5 SoC family.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
.../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++++++++++++++++++++++
include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +++++++++
2 files changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml
new file mode 100644
index 000000000000..d74570a90926
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a5-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A5 series PLL Clock Controller
+
+maintainers:
+ - Chuan Liu <chuan.liu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,a5-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input oscillator
+ - description: input fix pll dco
+ - description: input fix pll
+
+ clock-names:
+ items:
+ - const: xtal
+ - const: fix_dco
+ - const: fix
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a5-scmi-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8000 {
+ compatible = "amlogic,a5-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x1a4>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_FIXED_PLL_DCO>,
+ <&scmi_clk CLKID_FIXED_PLL>;
+ clock-names = "xtal",
+ "fix_dco",
+ "fix";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a5-pll-clkc.h b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h
new file mode 100644
index 000000000000..a74c448a8d8a
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H
+
+#define CLKID_MPLL_PREDIV 0
+#define CLKID_MPLL0_DIV 1
+#define CLKID_MPLL0 2
+#define CLKID_MPLL1_DIV 3
+#define CLKID_MPLL1 4
+#define CLKID_MPLL2_DIV 5
+#define CLKID_MPLL2 6
+#define CLKID_MPLL3_DIV 7
+#define CLKID_MPLL3 8
+#define CLKID_GP0_PLL_DCO 9
+#define CLKID_GP0_PLL 10
+#define CLKID_HIFI_PLL_DCO 11
+#define CLKID_HIFI_PLL 12
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals clock controller
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (12 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:46 ` Chuan Liu
2025-09-30 9:37 ` [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
` (6 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the peripherals clock controller dt-bindings for the Amlogic A5
SoC family.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
.../clock/amlogic,a5-peripherals-clkc.yaml | 134 +++++++++++++++++++++
.../clock/amlogic,a5-peripherals-clkc.h | 132 ++++++++++++++++++++
2 files changed, 266 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml
new file mode 100644
index 000000000000..88d71d9a72ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a5-peripherals-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A5 series Peripheral Clock Controller
+
+maintainers:
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+ - Chuan Liu <chuan.liu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,a5-peripherals-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 18
+ items:
+ - description: input oscillator
+ - description: input oscillators multiplexer
+ - description: input fix pll
+ - description: input fclk div 2
+ - description: input fclk div 2p5
+ - description: input fclk div 3
+ - description: input fclk div 4
+ - description: input fclk div 5
+ - description: input fclk div 7
+ - description: input mpll2
+ - description: input mpll3
+ - description: input gp0 pll
+ - description: input gp1 pll
+ - description: input hifi pll
+ - description: input sys clk
+ - description: input axi clk
+ - description: input sys pll div 16
+ - description: input cpu clk div 16
+ - description: input pad clock for rtc clk (optional)
+ - description: input ddr pll (optional)
+ - description: input source from clk-measure (optional)
+ - description: input rtc pll (optional)
+
+ clock-names:
+ minItems: 18
+ items:
+ - const: xtal
+ - const: oscin
+ - const: fix
+ - const: fdiv2
+ - const: fdiv2p5
+ - const: fdiv3
+ - const: fdiv4
+ - const: fdiv5
+ - const: fdiv7
+ - const: mpll2
+ - const: mpll3
+ - const: gp0
+ - const: gp1
+ - const: hifi
+ - const: sysclk
+ - const: axiclk
+ - const: sysplldiv16
+ - const: cpudiv16
+ - const: pad_osc
+ - const: ddr
+ - const: clkmsr
+ - const: rtc
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a5-scmi-clkc.h>
+ #include <dt-bindings/clock/amlogic,a5-pll-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@0 {
+ compatible = "amlogic,a5-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x224>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_OSC>,
+ <&scmi_clk CLKID_FIXED_PLL>,
+ <&scmi_clk CLKID_FCLK_DIV2>,
+ <&scmi_clk CLKID_FCLK_DIV2P5>,
+ <&scmi_clk CLKID_FCLK_DIV3>,
+ <&scmi_clk CLKID_FCLK_DIV4>,
+ <&scmi_clk CLKID_FCLK_DIV5>,
+ <&scmi_clk CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_MPLL2>,
+ <&clkc_pll CLKID_MPLL3>,
+ <&clkc_pll CLKID_GP0_PLL>,
+ <&scmi_clk CLKID_GP1_PLL>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&scmi_clk CLKID_SYS_CLK>,
+ <&scmi_clk CLKID_AXI_CLK>,
+ <&scmi_clk CLKID_SYS_PLL_DIV16>,
+ <&scmi_clk CLKID_CPU_CLK_DIV16>;
+ clock-names = "xtal",
+ "oscin",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "mpll2",
+ "mpll3",
+ "gp0",
+ "gp1",
+ "hifi",
+ "sysclk",
+ "axiclk",
+ "sysplldiv16",
+ "cpudiv16";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h
new file mode 100644
index 000000000000..b8a68b7f29dc
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_DUALDIV_CLKIN 0
+#define CLKID_RTC_DUALDIV 1
+#define CLKID_RTC_DUALDIV_SEL 2
+#define CLKID_RTC_DUALDIV_CLKOUT 3
+#define CLKID_RTC_CLK 4
+#define CLKID_SYS_RESET_CTRL 5
+#define CLKID_SYS_PWR_CTRL 6
+#define CLKID_SYS_PAD_CTRL 7
+#define CLKID_SYS_CTRL 8
+#define CLKID_SYS_TS_PLL 9
+#define CLKID_SYS_DEV_ARB 10
+#define CLKID_SYS_MAILBOX 11
+#define CLKID_SYS_JTAG_CTRL 12
+#define CLKID_SYS_IR_CTRL 13
+#define CLKID_SYS_MSR_CLK 14
+#define CLKID_SYS_ROM 15
+#define CLKID_SYS_CPU_ARB 16
+#define CLKID_SYS_RSA 17
+#define CLKID_SYS_SARADC 18
+#define CLKID_SYS_STARTUP 19
+#define CLKID_SYS_SECURE 20
+#define CLKID_SYS_SPIFC 21
+#define CLKID_SYS_DSPA 22
+#define CLKID_SYS_NNA 23
+#define CLKID_SYS_ETH_MAC 24
+#define CLKID_SYS_RAMA 25
+#define CLKID_SYS_RAMB 26
+#define CLKID_SYS_AUDIO_TOP 27
+#define CLKID_SYS_AUDIO_VAD 28
+#define CLKID_SYS_USB 29
+#define CLKID_SYS_SD_EMMC_A 30
+#define CLKID_SYS_SD_EMMC_C 31
+#define CLKID_SYS_PWM_AB 32
+#define CLKID_SYS_PWM_CD 33
+#define CLKID_SYS_PWM_EF 34
+#define CLKID_SYS_PWM_GH 35
+#define CLKID_SYS_SPICC_1 36
+#define CLKID_SYS_SPICC_0 37
+#define CLKID_SYS_UART_A 38
+#define CLKID_SYS_UART_B 39
+#define CLKID_SYS_UART_C 40
+#define CLKID_SYS_UART_D 41
+#define CLKID_SYS_UART_E 42
+#define CLKID_SYS_I2C_M_A 43
+#define CLKID_SYS_I2C_M_B 44
+#define CLKID_SYS_I2C_M_C 45
+#define CLKID_SYS_I2C_M_D 46
+#define CLKID_SYS_RTC 47
+#define CLKID_AXI_AUDIO_VAD 48
+#define CLKID_AXI_AUDIO_TOP 49
+#define CLKID_AXI_RAMB 50
+#define CLKID_AXI_RAMA 51
+#define CLKID_AXI_NNA 52
+#define CLKID_AXI_DEV1_DMC 53
+#define CLKID_AXI_DEV0_DMC 54
+#define CLKID_AXI_DSP_DMC 55
+#define CLKID_12_24M_IN 56
+#define CLKID_12M_24M 57
+#define CLKID_FCLK_25M_DIV 58
+#define CLKID_FCLK_25M 59
+#define CLKID_GEN_SEL 60
+#define CLKID_GEN_DIV 61
+#define CLKID_GEN 62
+#define CLKID_SARADC_SEL 63
+#define CLKID_SARADC_DIV 64
+#define CLKID_SARADC 65
+#define CLKID_PWM_A_SEL 66
+#define CLKID_PWM_A_DIV 67
+#define CLKID_PWM_A 68
+#define CLKID_PWM_B_SEL 69
+#define CLKID_PWM_B_DIV 70
+#define CLKID_PWM_B 71
+#define CLKID_PWM_C_SEL 72
+#define CLKID_PWM_C_DIV 73
+#define CLKID_PWM_C 74
+#define CLKID_PWM_D_SEL 75
+#define CLKID_PWM_D_DIV 76
+#define CLKID_PWM_D 77
+#define CLKID_PWM_E_SEL 78
+#define CLKID_PWM_E_DIV 79
+#define CLKID_PWM_E 80
+#define CLKID_PWM_F_SEL 81
+#define CLKID_PWM_F_DIV 82
+#define CLKID_PWM_F 83
+#define CLKID_PWM_G_SEL 84
+#define CLKID_PWM_G_DIV 85
+#define CLKID_PWM_G 86
+#define CLKID_PWM_H_SEL 87
+#define CLKID_PWM_H_DIV 88
+#define CLKID_PWM_H 89
+#define CLKID_SPICC_0_SEL 90
+#define CLKID_SPICC_0_DIV 91
+#define CLKID_SPICC_0 92
+#define CLKID_SPICC_1_SEL 93
+#define CLKID_SPICC_1_DIV 94
+#define CLKID_SPICC_1 95
+#define CLKID_SD_EMMC_A_SEL 96
+#define CLKID_SD_EMMC_A_DIV 97
+#define CLKID_SD_EMMC_A 98
+#define CLKID_SD_EMMC_C_SEL 99
+#define CLKID_SD_EMMC_C_DIV 100
+#define CLKID_SD_EMMC_C 101
+#define CLKID_TS_DIV 102
+#define CLKID_TS 103
+#define CLKID_ETH_125M_DIV 104
+#define CLKID_ETH_125M 105
+#define CLKID_ETH_RMII_DIV 106
+#define CLKID_ETH_RMII 107
+#define CLKID_DSPA_0_SEL 108
+#define CLKID_DSPA_0_DIV 109
+#define CLKID_DSPA_0 110
+#define CLKID_DSPA_1_SEL 111
+#define CLKID_DSPA_1_DIV 112
+#define CLKID_DSPA_1 113
+#define CLKID_DSPA 114
+#define CLKID_NNA_CORE_SEL 115
+#define CLKID_NNA_CORE_DIV 116
+#define CLKID_NNA_CORE 117
+#define CLKID_NNA_AXI_SEL 118
+#define CLKID_NNA_AXI_DIV 119
+#define CLKID_NNA_AXI 120
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (13 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 16/19] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
` (5 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the PLL clock controller driver for the Amlogic A5 SoC family.
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/Kconfig | 14 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a5-pll.c | 476 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 491 insertions(+)
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 860625ca6e9b..db4b98abf4f4 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -158,6 +158,20 @@ config COMMON_CLK_A4_PERIPHERALS
Support for the Peripherals clock controller on Amlogic BA40X device,
AKA A4. Say Y if you want the peripherals clock to work.
+config COMMON_CLK_A5_PLL
+ tristate "Amlogic A5 PLL clock controller"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_PLL
+ select COMMON_CLK_MESON_MPLL
+ select COMMON_CLK_MESON_CLKC_UTILS
+ imply COMMON_CLK_SCMI
+ help
+ Support for the PLL clock controller on Amlogic A113X2 device, AKA A5.
+ Say Y if you want the board to work, because PLLs are the parent
+ of most peripherals.
+
config COMMON_CLK_C3_PLL
tristate "Amlogic C3 PLL clock controller"
depends on ARM64
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 88f6b336a6ca..ff73d2486f05 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
obj-$(CONFIG_COMMON_CLK_A4_PLL) += a4-pll.o
obj-$(CONFIG_COMMON_CLK_A4_PERIPHERALS) += a4-peripherals.o
+obj-$(CONFIG_COMMON_CLK_A5_PLL) += a5-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/a5-pll.c b/drivers/clk/meson/a5-pll.c
new file mode 100644
index 000000000000..1789a7e6470d
--- /dev/null
+++ b/drivers/clk/meson/a5-pll.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Amlogic A5 PLL Controller Driver
+ *
+ * Copyright (c) 2024-2025 Amlogic, inc.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-mpll.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,a5-pll-clkc.h>
+
+#define GP0PLL_CTRL0 0x80
+#define GP0PLL_CTRL1 0x84
+#define GP0PLL_CTRL2 0x88
+#define GP0PLL_CTRL3 0x8c
+#define GP0PLL_CTRL4 0x90
+#define GP0PLL_CTRL5 0x94
+#define GP0PLL_CTRL6 0x98
+#define HIFIPLL_CTRL0 0x100
+#define HIFIPLL_CTRL1 0x104
+#define HIFIPLL_CTRL2 0x108
+#define HIFIPLL_CTRL3 0x10c
+#define HIFIPLL_CTRL4 0x110
+#define HIFIPLL_CTRL5 0x114
+#define HIFIPLL_CTRL6 0x118
+#define MPLL_CTRL0 0x180
+#define MPLL_CTRL1 0x184
+#define MPLL_CTRL2 0x188
+#define MPLL_CTRL3 0x18c
+#define MPLL_CTRL4 0x190
+#define MPLL_CTRL5 0x194
+#define MPLL_CTRL6 0x198
+#define MPLL_CTRL7 0x19c
+#define MPLL_CTRL8 0x1a0
+
+static struct clk_fixed_factor a5_mpll_prediv = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_prediv",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fix_dco"
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence a5_mpll0_init_regs[] = {
+ { .reg = MPLL_CTRL2, .def = 0x40000033 },
+};
+
+static struct clk_regmap a5_mpll0_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL1,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = a5_mpll0_init_regs,
+ .init_count = ARRAY_SIZE(a5_mpll0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_mpll0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL1,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &a5_mpll0_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence a5_mpll1_init_regs[] = {
+ { .reg = MPLL_CTRL4, .def = 0x40000033 },
+};
+
+static struct clk_regmap a5_mpll1_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL3,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = a5_mpll1_init_regs,
+ .init_count = ARRAY_SIZE(a5_mpll1_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_mpll1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL3,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "a5_mpll1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &a5_mpll1_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence a5_mpll2_init_regs[] = {
+ { .reg = MPLL_CTRL6, .def = 0x40000033 },
+};
+
+static struct clk_regmap a5_mpll2_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL5,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = a5_mpll2_init_regs,
+ .init_count = ARRAY_SIZE(a5_mpll2_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_mpll2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL5,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &a5_mpll2_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence a5_mpll3_init_regs[] = {
+ { .reg = MPLL_CTRL8, .def = 0x40000033 },
+};
+
+static struct clk_regmap a5_mpll3_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = MPLL_CTRL7,
+ .shift = 29,
+ .width = 1,
+ },
+ .init_regs = a5_mpll3_init_regs,
+ .init_count = ARRAY_SIZE(a5_mpll3_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_mpll3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = MPLL_CTRL7,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &a5_mpll3_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence a5_gp0_init_regs[] = {
+ { .reg = GP0PLL_CTRL3, .def = 0x6a295c00 },
+ { .reg = GP0PLL_CTRL4, .def = 0x65771290 },
+ { .reg = GP0PLL_CTRL5, .def = 0x3927200a },
+ { .reg = GP0PLL_CTRL6, .def = 0x54540000 }
+};
+
+static const struct pll_mult_range a5_gp0_pll_mult_range = {
+ .min = 125,
+ .max = 250,
+};
+
+static struct clk_regmap a5_gp0_pll_dco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .frac = {
+ .reg_off = GP0PLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .n = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = GP0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &a5_gp0_pll_mult_range,
+ .init_regs = a5_gp0_init_regs,
+ .init_count = ARRAY_SIZE(a5_gp0_init_regs),
+ .frac_max = 100000,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp0_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+/* The maximum frequency divider supports is 32, not 128(2^7) */
+static const struct clk_div_table a5_gp0_pll_od_table[] = {
+ { 0, 1 },
+ { 1, 2 },
+ { 2, 4 },
+ { 3, 8 },
+ { 4, 16 },
+ { 5, 32 },
+ { /* sentinel */ }
+};
+
+static struct clk_regmap a5_gp0_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = GP0PLL_CTRL0,
+ .shift = 16,
+ .width = 3,
+ .table = a5_gp0_pll_od_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gp0_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_gp0_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence a5_hifi_init_regs[] = {
+ { .reg = HIFIPLL_CTRL3, .def = 0x6a285c00 },
+ { .reg = HIFIPLL_CTRL4, .def = 0x65771290 },
+ { .reg = HIFIPLL_CTRL5, .def = 0x3927200a },
+ { .reg = HIFIPLL_CTRL6, .def = 0x56540000 }
+};
+
+static const struct pll_mult_range a5_hifi_pll_mult_range = {
+ .min = 125,
+ .max = 250,
+};
+
+static struct clk_regmap a5_hifi_pll_dco = {
+ .data = &(struct meson_clk_pll_data) {
+ .en = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .frac = {
+ .reg_off = HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .n = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HIFIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &a5_hifi_pll_mult_range,
+ .init_regs = a5_hifi_init_regs,
+ .init_count = ARRAY_SIZE(a5_hifi_init_regs),
+ .frac_max = 100000,
+ .flags = CLK_MESON_PLL_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_hifi_pll = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = HIFIPLL_CTRL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "hifi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_hifi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_hw *a5_pll_hw_clks[] = {
+ [CLKID_MPLL_PREDIV] = &a5_mpll_prediv.hw,
+ [CLKID_MPLL0_DIV] = &a5_mpll0_div.hw,
+ [CLKID_MPLL0] = &a5_mpll0.hw,
+ [CLKID_MPLL1_DIV] = &a5_mpll1_div.hw,
+ [CLKID_MPLL1] = &a5_mpll1.hw,
+ [CLKID_MPLL2_DIV] = &a5_mpll2_div.hw,
+ [CLKID_MPLL2] = &a5_mpll2.hw,
+ [CLKID_MPLL3_DIV] = &a5_mpll3_div.hw,
+ [CLKID_MPLL3] = &a5_mpll3.hw,
+ [CLKID_GP0_PLL_DCO] = &a5_gp0_pll_dco.hw,
+ [CLKID_GP0_PLL] = &a5_gp0_pll.hw,
+ [CLKID_HIFI_PLL_DCO] = &a5_hifi_pll_dco.hw,
+ [CLKID_HIFI_PLL] = &a5_hifi_pll.hw
+};
+
+static const struct meson_clkc_data a5_pll_clkc_data = {
+ .hw_clks = {
+ .hws = a5_pll_hw_clks,
+ .num = ARRAY_SIZE(a5_pll_hw_clks),
+ },
+};
+
+static const struct of_device_id a5_pll_clkc_match_table[] = {
+ {
+ .compatible = "amlogic,a5-pll-clkc",
+ .data = &a5_pll_clkc_data,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, a5_pll_clkc_match_table);
+
+static struct platform_driver a5_pll_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "a5-pll-clkc",
+ .of_match_table = a5_pll_clkc_match_table,
+ },
+};
+module_platform_driver(a5_pll_clkc_driver);
+
+MODULE_DESCRIPTION("Amlogic A5 PLL Clock Controller driver");
+MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 16/19] clk: amlogic: Add A5 clock peripherals controller driver
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (14 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
` (4 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add the peripherals clock controller driver for the Amlogic A5 SoC family.
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/Kconfig | 13 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++++++++++++++++++
3 files changed, 897 insertions(+)
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index db4b98abf4f4..eae9386d8e51 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -172,6 +172,19 @@ config COMMON_CLK_A5_PLL
Say Y if you want the board to work, because PLLs are the parent
of most peripherals.
+config COMMON_CLK_A5_PERIPHERALS
+ tristate "Amlogic A5 peripherals clock controller"
+ depends on ARM64
+ default ARCH_MESON
+ select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_DUALDIV
+ select COMMON_CLK_MESON_CLKC_UTILS
+ imply COMMON_CLK_SCMI
+ imply COMMON_CLK_A5_PLL
+ help
+ Support for the Peripherals clock controller on Amlogic A113X2 device,
+ AKA A5. Say Y if you want the peripherals clock to work.
+
config COMMON_CLK_C3_PLL
tristate "Amlogic C3 PLL clock controller"
depends on ARM64
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ff73d2486f05..15001947ba1f 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
obj-$(CONFIG_COMMON_CLK_A4_PLL) += a4-pll.o
obj-$(CONFIG_COMMON_CLK_A4_PERIPHERALS) += a4-peripherals.o
obj-$(CONFIG_COMMON_CLK_A5_PLL) += a5-pll.o
+obj-$(CONFIG_COMMON_CLK_A5_PERIPHERALS) += a5-peripherals.o
obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/a5-peripherals.c b/drivers/clk/meson/a5-peripherals.c
new file mode 100644
index 000000000000..eca9f3dcc256
--- /dev/null
+++ b/drivers/clk/meson/a5-peripherals.c
@@ -0,0 +1,883 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Amlogic A5 Peripherals Clock Controller Driver
+ *
+ * Copyright (c) 2024-2025 Amlogic, inc.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include "clk-regmap.h"
+#include "clk-dualdiv.h"
+#include "meson-clkc-utils.h"
+#include <dt-bindings/clock/amlogic,a5-peripherals-clkc.h>
+
+#define RTC_BY_OSCIN_CTRL0 0x8
+#define RTC_BY_OSCIN_CTRL1 0xc
+#define RTC_CTRL 0x10
+#define SYS_CLK_EN0_REG0 0x44
+#define SYS_CLK_EN0_REG1 0x48
+#define DSPA_CLK_CTRL0 0x9c
+#define CLK12_24_CTRL 0xa8
+#define AXI_CLK_EN0 0xac
+#define TS_CLK_CTRL 0x158
+#define ETH_CLK_CTRL 0x164
+#define NAND_CLK_CTRL 0x168
+#define SD_EMMC_CLK_CTRL 0x16c
+#define SPICC_CLK_CTRL 0x174
+#define GEN_CLK_CTRL 0x178
+#define SAR_CLK_CTRL0 0x17c
+#define PWM_CLK_AB_CTRL 0x180
+#define PWM_CLK_CD_CTRL 0x184
+#define PWM_CLK_EF_CTRL 0x188
+#define PWM_CLK_GH_CTRL 0x18c
+#define NNA_CLK_CNTL 0x220
+
+static struct clk_regmap a5_rtc_dualdiv_clkin = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv_clkin",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "oscin",
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct meson_clk_dualdiv_param a5_rtc_dualdiv_table[] = {
+ { 733, 732, 8, 11, 1 },
+ { /* sentinel */ }
+};
+
+static struct clk_regmap a5_rtc_dualdiv = {
+ .data = &(struct meson_clk_dualdiv_data) {
+ .n1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 0,
+ .width = 12,
+ },
+ .n2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 12,
+ .width = 12,
+ },
+ .m1 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 0,
+ .width = 12,
+ },
+ .m2 = {
+ .reg_off = RTC_BY_OSCIN_CTRL1,
+ .shift = 12,
+ .width = 12,
+ },
+ .dual = {
+ .reg_off = RTC_BY_OSCIN_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .table = a5_rtc_dualdiv_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv",
+ .ops = &meson_clk_dualdiv_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_rtc_dualdiv_clkin.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct clk_parent_data a5_rtc_dualdiv_parent_data[] = {
+ { .hw = &a5_rtc_dualdiv.hw },
+ { .hw = &a5_rtc_dualdiv_clkin.hw }
+};
+
+static struct clk_regmap a5_rtc_dualdiv_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_BY_OSCIN_CTRL1,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = a5_rtc_dualdiv_parent_data,
+ .num_parents = ARRAY_SIZE(a5_rtc_dualdiv_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a5_rtc_dualdiv_clkout = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = RTC_BY_OSCIN_CTRL0,
+ .bit_idx = 30,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_dualdiv_clkout",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_rtc_dualdiv_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data a5_rtc_clk_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .hw = &a5_rtc_dualdiv_clkout.hw },
+ { .fw_name = "pad_osc" }
+};
+
+static struct clk_regmap a5_rtc_clk = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = RTC_CTRL,
+ .mask = 0x3,
+ .shift = 0,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "rtc_clk",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = a5_rtc_clk_parent_data,
+ .num_parents = ARRAY_SIZE(a5_rtc_clk_parent_data),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+#define A5_PCLK(_name, _reg, _bit, _pdata, _flags) \
+struct clk_regmap a5_##_name = { \
+ .data = &(struct clk_regmap_gate_data) { \
+ .offset = (_reg), \
+ .bit_idx = (_bit), \
+ }, \
+ .hw.init = &(struct clk_init_data) { \
+ .name = #_name, \
+ .ops = &clk_regmap_gate_ops, \
+ .parent_data = (_pdata), \
+ .num_parents = 1, \
+ .flags = (_flags), \
+ }, \
+}
+
+static const struct clk_parent_data a5_sys_pclk_parents = { .fw_name = "sysclk" };
+
+#define A5_SYS_PCLK(_name, _reg, _bit, _flags) \
+ A5_PCLK(_name, _reg, _bit, &a5_sys_pclk_parents, _flags)
+
+static A5_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
+static A5_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
+static A5_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0);
+static A5_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0);
+static A5_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0);
+
+/*
+ * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that
+ * access the AXI bus.
+ */
+static A5_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0);
+static A5_SYS_PCLK(sys_mailbox, SYS_CLK_EN0_REG0, 10, 0);
+static A5_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0);
+static A5_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0);
+static A5_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0);
+static A5_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0);
+static A5_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0);
+static A5_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0);
+static A5_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG0, 20, 0);
+static A5_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0);
+static A5_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0);
+static A5_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0);
+static A5_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG0, 24, 0);
+static A5_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 25, 0);
+static A5_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0);
+static A5_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0);
+static A5_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0);
+static A5_SYS_PCLK(sys_audio_top, SYS_CLK_EN0_REG1, 0, 0);
+static A5_SYS_PCLK(sys_audio_vad, SYS_CLK_EN0_REG1, 1, 0);
+static A5_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0);
+static A5_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0);
+static A5_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0);
+static A5_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0);
+static A5_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0);
+static A5_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0);
+static A5_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0);
+static A5_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0);
+static A5_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0);
+static A5_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0);
+static A5_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0);
+static A5_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0);
+static A5_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0);
+static A5_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0);
+static A5_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0);
+static A5_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0);
+static A5_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0);
+static A5_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0);
+static A5_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0);
+
+static const struct clk_parent_data a5_axi_clk_parents = { .fw_name = "axiclk" };
+
+#define A5_AXI_CLK(_name, _reg, _bit, _flags) \
+ A5_PCLK(_name, _reg, _bit, &a5_axi_clk_parents, _flags)
+
+static A5_AXI_CLK(axi_audio_vad, AXI_CLK_EN0, 0, 0);
+static A5_AXI_CLK(axi_audio_top, AXI_CLK_EN0, 1, 0);
+static A5_AXI_CLK(axi_ramb, AXI_CLK_EN0, 5, 0);
+static A5_AXI_CLK(axi_rama, AXI_CLK_EN0, 6, 0);
+static A5_AXI_CLK(axi_nna, AXI_CLK_EN0, 12, 0);
+
+/*
+ * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO,
+ * sec_top, USB, Audio) to access the AXI bus of the DDR.
+ */
+static A5_AXI_CLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0);
+
+/*
+ * NOTE: axi_dev0_dmc provides the clock for the peripherals(ETH and SPICC)
+ * to access the AXI bus of the DDR.
+ */
+static A5_AXI_CLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0);
+static A5_AXI_CLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0);
+
+static struct clk_regmap a5_clk_12_24m_in = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "clk_12_24m_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_clk_12_24m = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLK12_24_CTRL,
+ .shift = 10,
+ .width = 1,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "clk_12_24m",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_clk_12_24m_in.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_fclk_25m_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLK12_24_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_25m_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fix",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_fclk_25m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLK12_24_CTRL,
+ .bit_idx = 12,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "fclk_25m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_fclk_25m_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * Channel 4 5 8 9 10 11 13 14 15 16 18 are not connected.
+ *
+ * gp1 is designed for DSU (DynamIQ Shared Unit) alone. It cannot be changed
+ * arbitrarily. gp1 is read-only in the kernel and is only open for debug
+ * purposes.
+ */
+static u32 a5_gen_parent_table[] = { 0, 1, 2, 3, 6, 7, 12, 17, 19, 20, 21, 22,
+ 23, 24, 25, 26, 27, 28};
+
+static const struct clk_parent_data a5_gen_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .hw = &a5_rtc_clk.hw },
+ { .fw_name = "sysplldiv16" },
+ { .fw_name = "ddr" },
+ { .fw_name = "gp1" },
+ { .fw_name = "hifi" },
+ { .fw_name = "clkmsr" },
+ { .fw_name = "cpudiv16" },
+ { .fw_name = "fdiv2" },
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv5" },
+ { .fw_name = "fdiv7" },
+ { .fw_name = "mpll0" },
+ { .fw_name = "mpll1" },
+ { .fw_name = "mpll2" },
+ { .fw_name = "mpll3" }
+};
+
+static struct clk_regmap a5_gen_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = GEN_CLK_CTRL,
+ .mask = 0x1f,
+ .shift = 12,
+ .table = a5_gen_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gen_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = a5_gen_parent_data,
+ .num_parents = ARRAY_SIZE(a5_gen_parent_data),
+ },
+};
+
+static struct clk_regmap a5_gen_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = GEN_CLK_CTRL,
+ .shift = 0,
+ .width = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gen_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_gen_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a5_gen = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = GEN_CLK_CTRL,
+ .bit_idx = 11,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "gen",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_gen_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+#define A5_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
+ MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
+
+#define A5_COMP_DIV(_name, _reg, _shift, _width) \
+ MESON_COMP_DIV(a5_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
+
+#define A5_COMP_GATE(_name, _reg, _bit) \
+ MESON_COMP_GATE(a5_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
+
+static const struct clk_parent_data a5_saradc_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "sysclk" }
+};
+
+static A5_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x3, a5_saradc_parent_data);
+static A5_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
+static A5_COMP_GATE(saradc, SAR_CLK_CTRL0, 8);
+
+static const struct clk_parent_data a5_pwm_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .hw = &a5_rtc_clk.hw },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv3" }
+};
+
+static A5_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
+static A5_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
+
+static A5_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
+static A5_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
+
+static A5_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
+static A5_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
+
+static A5_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
+static A5_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
+
+static A5_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
+static A5_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
+
+static A5_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
+static A5_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
+
+static A5_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8);
+static A5_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
+
+static A5_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, a5_pwm_parent_data);
+static A5_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8);
+static A5_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
+
+/*
+ * NOTE: Channel 7 is gp1, because gp1 is designed for DSU, so spicc does not
+ * support this source in the driver.
+ */
+static const struct clk_parent_data a5_spicc_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "sysclk" },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "fdiv2" },
+ { .fw_name = "fdiv5" },
+ { .fw_name = "fdiv7" }
+};
+
+static A5_COMP_SEL(spicc_0, SPICC_CLK_CTRL, 7, 0x7, a5_spicc_parent_data);
+static A5_COMP_DIV(spicc_0, SPICC_CLK_CTRL, 0, 6);
+static A5_COMP_GATE(spicc_0, SPICC_CLK_CTRL, 6);
+
+static A5_COMP_SEL(spicc_1, SPICC_CLK_CTRL, 23, 0x7, a5_spicc_parent_data);
+static A5_COMP_DIV(spicc_1, SPICC_CLK_CTRL, 16, 6);
+static A5_COMP_GATE(spicc_1, SPICC_CLK_CTRL, 22);
+
+static const struct clk_parent_data a5_sd_emmc_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "fdiv2" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "hifi" },
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "mpll2" },
+ { .fw_name = "mpll3" },
+ { .fw_name = "gp0" }
+};
+
+static A5_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, a5_sd_emmc_parent_data);
+static A5_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
+static A5_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7);
+
+static A5_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, a5_sd_emmc_parent_data);
+static A5_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
+static A5_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7);
+
+static struct clk_regmap a5_ts_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = TS_CLK_CTRL,
+ .shift = 0,
+ .width = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ts_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "oscin",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_ts = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = TS_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "ts",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_ts_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor a5_eth_125m_div = {
+ .mult = 1,
+ .div = 8,
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_125m_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fdiv2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_eth_125m = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_125m",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_eth_125m_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_eth_rmii_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = ETH_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_rmii_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "fdiv2",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap a5_eth_rmii = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = ETH_CLK_CTRL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "eth_rmii",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_eth_rmii_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* Channel 6 is gp1. */
+static u32 a5_dspa_parent_table[] = { 0, 1, 2, 3, 4, 5, 7};
+
+static const struct clk_parent_data a5_dspa_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "rtc" }, /* rtc_pll */
+ { .fw_name = "hifi" },
+ { .fw_name = "fdiv4" },
+ { .hw = &a5_rtc_clk.hw }
+};
+
+static struct clk_regmap a5_dspa_0_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 10,
+ .table = a5_dspa_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_0_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = a5_dspa_parent_data,
+ .num_parents = ARRAY_SIZE(a5_dspa_parent_data),
+ },
+};
+
+static struct clk_regmap a5_dspa_0_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = DSPA_CLK_CTRL0,
+ .shift = 0,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_0_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_dspa_0_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a5_dspa_0 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = DSPA_CLK_CTRL0,
+ .bit_idx = 13,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_dspa_0_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a5_dspa_1_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x7,
+ .shift = 26,
+ .table = a5_dspa_parent_table,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_1_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = a5_dspa_parent_data,
+ .num_parents = ARRAY_SIZE(a5_dspa_parent_data),
+ },
+};
+
+static struct clk_regmap a5_dspa_1_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = DSPA_CLK_CTRL0,
+ .shift = 16,
+ .width = 10,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_dspa_1_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a5_dspa_1 = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = DSPA_CLK_CTRL0,
+ .bit_idx = 29,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_dspa_1_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap a5_dspa = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = DSPA_CLK_CTRL0,
+ .mask = 0x1,
+ .shift = 15,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "dspa",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &a5_dspa_0.hw,
+ &a5_dspa_1.hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+#define A5_COMP_SEL_WITH_TAB(_name, _reg, _shift, _mask, _pdata, _table) \
+ MESON_COMP_SEL(a5_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0)
+
+/* Channel 6 is gp1. */
+static u32 a5_nna_parent_table[] = { 0, 1, 2, 3, 4, 5, 7};
+
+static const struct clk_parent_data a5_nna_parent_data[] = {
+ { .fw_name = "oscin" },
+ { .fw_name = "fdiv2p5" },
+ { .fw_name = "fdiv4" },
+ { .fw_name = "fdiv3" },
+ { .fw_name = "fdiv5" },
+ { .fw_name = "fdiv2" },
+ { .fw_name = "hifi" }
+};
+
+static A5_COMP_SEL_WITH_TAB(nna_core, NNA_CLK_CNTL, 9, 0x7,
+ a5_nna_parent_data, a5_nna_parent_table);
+static A5_COMP_DIV(nna_core, NNA_CLK_CNTL, 0, 7);
+static A5_COMP_GATE(nna_core, NNA_CLK_CNTL, 8);
+
+static A5_COMP_SEL_WITH_TAB(nna_axi, NNA_CLK_CNTL, 25, 0x7,
+ a5_nna_parent_data, a5_nna_parent_table);
+static A5_COMP_DIV(nna_axi, NNA_CLK_CNTL, 16, 7);
+static A5_COMP_GATE(nna_axi, NNA_CLK_CNTL, 24);
+
+static struct clk_hw *a5_peripherals_hw_clks[] = {
+ [CLKID_RTC_DUALDIV_CLKIN] = &a5_rtc_dualdiv_clkin.hw,
+ [CLKID_RTC_DUALDIV] = &a5_rtc_dualdiv.hw,
+ [CLKID_RTC_DUALDIV_SEL] = &a5_rtc_dualdiv_sel.hw,
+ [CLKID_RTC_DUALDIV_CLKOUT] = &a5_rtc_dualdiv_clkout.hw,
+ [CLKID_RTC_CLK] = &a5_rtc_clk.hw,
+ [CLKID_SYS_RESET_CTRL] = &a5_sys_reset_ctrl.hw,
+ [CLKID_SYS_PWR_CTRL] = &a5_sys_pwr_ctrl.hw,
+ [CLKID_SYS_PAD_CTRL] = &a5_sys_pad_ctrl.hw,
+ [CLKID_SYS_CTRL] = &a5_sys_ctrl.hw,
+ [CLKID_SYS_TS_PLL] = &a5_sys_ts_pll.hw,
+ [CLKID_SYS_DEV_ARB] = &a5_sys_dev_arb.hw,
+ [CLKID_SYS_MAILBOX] = &a5_sys_mailbox.hw,
+ [CLKID_SYS_JTAG_CTRL] = &a5_sys_jtag_ctrl.hw,
+ [CLKID_SYS_IR_CTRL] = &a5_sys_ir_ctrl.hw,
+ [CLKID_SYS_MSR_CLK] = &a5_sys_msr_clk.hw,
+ [CLKID_SYS_ROM] = &a5_sys_rom.hw,
+ [CLKID_SYS_CPU_ARB] = &a5_sys_cpu_apb.hw,
+ [CLKID_SYS_RSA] = &a5_sys_rsa.hw,
+ [CLKID_SYS_SARADC] = &a5_sys_saradc.hw,
+ [CLKID_SYS_STARTUP] = &a5_sys_startup.hw,
+ [CLKID_SYS_SECURE] = &a5_sys_secure.hw,
+ [CLKID_SYS_SPIFC] = &a5_sys_spifc.hw,
+ [CLKID_SYS_DSPA] = &a5_sys_dspa.hw,
+ [CLKID_SYS_NNA] = &a5_sys_nna.hw,
+ [CLKID_SYS_ETH_MAC] = &a5_sys_eth_mac.hw,
+ [CLKID_SYS_RAMA] = &a5_sys_rama.hw,
+ [CLKID_SYS_RAMB] = &a5_sys_ramb.hw,
+ [CLKID_SYS_AUDIO_TOP] = &a5_sys_audio_top.hw,
+ [CLKID_SYS_AUDIO_VAD] = &a5_sys_audio_vad.hw,
+ [CLKID_SYS_USB] = &a5_sys_usb.hw,
+ [CLKID_SYS_SD_EMMC_A] = &a5_sys_sd_emmc_a.hw,
+ [CLKID_SYS_SD_EMMC_C] = &a5_sys_sd_emmc_c.hw,
+ [CLKID_SYS_PWM_AB] = &a5_sys_pwm_ab.hw,
+ [CLKID_SYS_PWM_CD] = &a5_sys_pwm_cd.hw,
+ [CLKID_SYS_PWM_EF] = &a5_sys_pwm_ef.hw,
+ [CLKID_SYS_PWM_GH] = &a5_sys_pwm_gh.hw,
+ [CLKID_SYS_SPICC_1] = &a5_sys_spicc_1.hw,
+ [CLKID_SYS_SPICC_0] = &a5_sys_spicc_0.hw,
+ [CLKID_SYS_UART_A] = &a5_sys_uart_a.hw,
+ [CLKID_SYS_UART_B] = &a5_sys_uart_b.hw,
+ [CLKID_SYS_UART_C] = &a5_sys_uart_c.hw,
+ [CLKID_SYS_UART_D] = &a5_sys_uart_d.hw,
+ [CLKID_SYS_UART_E] = &a5_sys_uart_e.hw,
+ [CLKID_SYS_I2C_M_A] = &a5_sys_i2c_m_a.hw,
+ [CLKID_SYS_I2C_M_B] = &a5_sys_i2c_m_b.hw,
+ [CLKID_SYS_I2C_M_C] = &a5_sys_i2c_m_c.hw,
+ [CLKID_SYS_I2C_M_D] = &a5_sys_i2c_m_d.hw,
+ [CLKID_SYS_RTC] = &a5_sys_rtc.hw,
+ [CLKID_AXI_AUDIO_VAD] = &a5_axi_audio_vad.hw,
+ [CLKID_AXI_AUDIO_TOP] = &a5_axi_audio_top.hw,
+ [CLKID_AXI_RAMB] = &a5_axi_ramb.hw,
+ [CLKID_AXI_RAMA] = &a5_axi_rama.hw,
+ [CLKID_AXI_NNA] = &a5_axi_nna.hw,
+ [CLKID_AXI_DEV1_DMC] = &a5_axi_dev1_dmc.hw,
+ [CLKID_AXI_DEV0_DMC] = &a5_axi_dev0_dmc.hw,
+ [CLKID_AXI_DSP_DMC] = &a5_axi_dsp_dmc.hw,
+ [CLKID_12_24M_IN] = &a5_clk_12_24m_in.hw,
+ [CLKID_12M_24M] = &a5_clk_12_24m.hw,
+ [CLKID_FCLK_25M_DIV] = &a5_fclk_25m_div.hw,
+ [CLKID_FCLK_25M] = &a5_fclk_25m.hw,
+ [CLKID_GEN_SEL] = &a5_gen_sel.hw,
+ [CLKID_GEN_DIV] = &a5_gen_div.hw,
+ [CLKID_GEN] = &a5_gen.hw,
+ [CLKID_SARADC_SEL] = &a5_saradc_sel.hw,
+ [CLKID_SARADC_DIV] = &a5_saradc_div.hw,
+ [CLKID_SARADC] = &a5_saradc.hw,
+ [CLKID_PWM_A_SEL] = &a5_pwm_a_sel.hw,
+ [CLKID_PWM_A_DIV] = &a5_pwm_a_div.hw,
+ [CLKID_PWM_A] = &a5_pwm_a.hw,
+ [CLKID_PWM_B_SEL] = &a5_pwm_b_sel.hw,
+ [CLKID_PWM_B_DIV] = &a5_pwm_b_div.hw,
+ [CLKID_PWM_B] = &a5_pwm_b.hw,
+ [CLKID_PWM_C_SEL] = &a5_pwm_c_sel.hw,
+ [CLKID_PWM_C_DIV] = &a5_pwm_c_div.hw,
+ [CLKID_PWM_C] = &a5_pwm_c.hw,
+ [CLKID_PWM_D_SEL] = &a5_pwm_d_sel.hw,
+ [CLKID_PWM_D_DIV] = &a5_pwm_d_div.hw,
+ [CLKID_PWM_D] = &a5_pwm_d.hw,
+ [CLKID_PWM_E_SEL] = &a5_pwm_e_sel.hw,
+ [CLKID_PWM_E_DIV] = &a5_pwm_e_div.hw,
+ [CLKID_PWM_E] = &a5_pwm_e.hw,
+ [CLKID_PWM_F_SEL] = &a5_pwm_f_sel.hw,
+ [CLKID_PWM_F_DIV] = &a5_pwm_f_div.hw,
+ [CLKID_PWM_F] = &a5_pwm_f.hw,
+ [CLKID_PWM_G_SEL] = &a5_pwm_g_sel.hw,
+ [CLKID_PWM_G_DIV] = &a5_pwm_g_div.hw,
+ [CLKID_PWM_G] = &a5_pwm_g.hw,
+ [CLKID_PWM_H_SEL] = &a5_pwm_h_sel.hw,
+ [CLKID_PWM_H_DIV] = &a5_pwm_h_div.hw,
+ [CLKID_PWM_H] = &a5_pwm_h.hw,
+ [CLKID_SPICC_0_SEL] = &a5_spicc_0_sel.hw,
+ [CLKID_SPICC_0_DIV] = &a5_spicc_0_div.hw,
+ [CLKID_SPICC_0] = &a5_spicc_0.hw,
+ [CLKID_SPICC_1_SEL] = &a5_spicc_1_sel.hw,
+ [CLKID_SPICC_1_DIV] = &a5_spicc_1_div.hw,
+ [CLKID_SPICC_1] = &a5_spicc_1.hw,
+ [CLKID_SD_EMMC_A_SEL] = &a5_sd_emmc_a_sel.hw,
+ [CLKID_SD_EMMC_A_DIV] = &a5_sd_emmc_a_div.hw,
+ [CLKID_SD_EMMC_A] = &a5_sd_emmc_a.hw,
+ [CLKID_SD_EMMC_C_SEL] = &a5_sd_emmc_c_sel.hw,
+ [CLKID_SD_EMMC_C_DIV] = &a5_sd_emmc_c_div.hw,
+ [CLKID_SD_EMMC_C] = &a5_sd_emmc_c.hw,
+ [CLKID_TS_DIV] = &a5_ts_div.hw,
+ [CLKID_TS] = &a5_ts.hw,
+ [CLKID_ETH_125M_DIV] = &a5_eth_125m_div.hw,
+ [CLKID_ETH_125M] = &a5_eth_125m.hw,
+ [CLKID_ETH_RMII_DIV] = &a5_eth_rmii_div.hw,
+ [CLKID_ETH_RMII] = &a5_eth_rmii.hw,
+ [CLKID_DSPA_0_SEL] = &a5_dspa_0_sel.hw,
+ [CLKID_DSPA_0_DIV] = &a5_dspa_0_div.hw,
+ [CLKID_DSPA_0] = &a5_dspa_0.hw,
+ [CLKID_DSPA_1_SEL] = &a5_dspa_1_sel.hw,
+ [CLKID_DSPA_1_DIV] = &a5_dspa_1_div.hw,
+ [CLKID_DSPA_1] = &a5_dspa_1.hw,
+ [CLKID_DSPA] = &a5_dspa.hw,
+ [CLKID_NNA_CORE_SEL] = &a5_nna_core_sel.hw,
+ [CLKID_NNA_CORE_DIV] = &a5_nna_core_div.hw,
+ [CLKID_NNA_CORE] = &a5_nna_core.hw,
+ [CLKID_NNA_AXI_SEL] = &a5_nna_axi_sel.hw,
+ [CLKID_NNA_AXI_DIV] = &a5_nna_axi_div.hw,
+ [CLKID_NNA_AXI] = &a5_nna_axi.hw,
+};
+
+static const struct meson_clkc_data a5_peripherals_clkc_data = {
+ .hw_clks = {
+ .hws = a5_peripherals_hw_clks,
+ .num = ARRAY_SIZE(a5_peripherals_hw_clks),
+ },
+};
+
+static const struct of_device_id a5_peripherals_clkc_match_table[] = {
+ {
+ .compatible = "amlogic,a5-peripherals-clkc",
+ .data = &a5_peripherals_clkc_data,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, a5_peripherals_clkc_match_table);
+
+static struct platform_driver a5_peripherals_clkc_driver = {
+ .probe = meson_clkc_mmio_probe,
+ .driver = {
+ .name = "a5-peripherals-clkc",
+ .of_match_table = a5_peripherals_clkc_match_table,
+ },
+};
+module_platform_driver(a5_peripherals_clkc_driver);
+
+MODULE_DESCRIPTION("Amlogic A5 Peripherals Clock Controller driver");
+MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("CLK_MESON");
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (15 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 16/19] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
` (3 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add scmi-clk device node information for the Amlogic A5 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index b1da8cbaa25a..3b0e70211268 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -48,6 +48,35 @@ pwrc: power-controller {
#power-domain-cells = <1>;
};
};
+
+ sram0: sram@f702a000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0xf702a000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xf702a000 0x100>;
+
+ scmi_buf0: scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x820000C1>;
+ shmem = <&scmi_buf0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
};
&apb {
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (16 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
` (2 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add PLL controller node for A5 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 3b0e70211268..89f7b5ff4ea3 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -6,6 +6,9 @@
#include "amlogic-a4-common.dtsi"
#include "amlogic-a5-reset.h"
#include <dt-bindings/power/amlogic,a5-pwrc.h>
+#include <dt-bindings/clock/amlogic,a5-scmi-clkc.h>
+#include <dt-bindings/clock/amlogic,a5-pll-clkc.h>
+
/ {
cpus {
#address-cells = <2>;
@@ -96,4 +99,16 @@ gpio_intc: interrupt-controller@4080 {
amlogic,channel-interrupts =
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
+
+ clkc_pll: clock-controller@8000 {
+ compatible = "amlogic,a5-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x1a4>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_FIXED_PLL_DCO>,
+ <&scmi_clk CLKID_FIXED_PLL>;
+ clock-names = "xtal",
+ "fix_dco",
+ "fix";
+ };
};
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock controller node
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (17 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
@ 2025-09-30 9:37 ` Chuan Liu via B4 Relay
2025-09-30 14:39 ` [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Rob Herring (Arm)
2025-10-01 7:45 ` Jerome Brunet
20 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu via B4 Relay @ 2025-09-30 9:37 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
From: Chuan Liu <chuan.liu@amlogic.com>
Add peripheral clock controller node for A5 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 43 +++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 89f7b5ff4ea3..406cd52a6474 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/power/amlogic,a5-pwrc.h>
#include <dt-bindings/clock/amlogic,a5-scmi-clkc.h>
#include <dt-bindings/clock/amlogic,a5-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,a5-peripherals-clkc.h>
/ {
cpus {
@@ -83,6 +84,48 @@ scmi_clk: protocol@14 {
};
&apb {
+ clkc_periphs: clock-controller@0 {
+ compatible = "amlogic,a5-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x224>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_OSC>,
+ <&scmi_clk CLKID_FIXED_PLL>,
+ <&scmi_clk CLKID_FCLK_DIV2>,
+ <&scmi_clk CLKID_FCLK_DIV2P5>,
+ <&scmi_clk CLKID_FCLK_DIV3>,
+ <&scmi_clk CLKID_FCLK_DIV4>,
+ <&scmi_clk CLKID_FCLK_DIV5>,
+ <&scmi_clk CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_MPLL2>,
+ <&clkc_pll CLKID_MPLL3>,
+ <&clkc_pll CLKID_GP0_PLL>,
+ <&scmi_clk CLKID_GP1_PLL>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&scmi_clk CLKID_SYS_CLK>,
+ <&scmi_clk CLKID_AXI_CLK>,
+ <&scmi_clk CLKID_SYS_PLL_DIV16>,
+ <&scmi_clk CLKID_CPU_CLK_DIV16>;
+ clock-names = "xtal",
+ "oscin",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "mpll2",
+ "mpll3",
+ "gp0",
+ "gp1",
+ "hifi",
+ "sysclk",
+ "axiclk",
+ "sysplldiv16",
+ "cpudiv16";
+ };
+
reset: reset-controller@2000 {
compatible = "amlogic,a5-reset",
"amlogic,meson-s4-reset";
--
2.42.0
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals clock controller
2025-09-30 9:37 ` [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
@ 2025-09-30 9:46 ` Chuan Liu
0 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu @ 2025-09-30 9:46 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Jerome Brunet, Kevin Hilman,
Martin Blumenstingl
Cc: linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao
Hi Rob,
On 9/30/2025 5:37 PM, Chuan Liu via B4 Relay wrote:
> [ EXTERNAL EMAIL ]
>
> From: Chuan Liu <chuan.liu@amlogic.com>
>
> Add the peripherals clock controller dt-bindings for the Amlogic A5
> SoC family.
>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 +++++++++++++++++++++
> .../clock/amlogic,a5-peripherals-clkc.h | 132 ++++++++++++++++++++
> 2 files changed, 266 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml
> new file mode 100644
> index 000000000000..88d71d9a72ea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml
> @@ -0,0 +1,134 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,a5-peripherals-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic A5 series Peripheral Clock Controller
> +
> +maintainers:
> + - Xianwei Zhao <xianwei.zhao@amlogic.com>
> + - Chuan Liu <chuan.liu@amlogic.com>
> +
> +properties:
> + compatible:
> + const: amlogic,a5-peripherals-clkc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 18
> + items:
> + - description: input oscillator
> + - description: input oscillators multiplexer
> + - description: input fix pll
> + - description: input fclk div 2
> + - description: input fclk div 2p5
> + - description: input fclk div 3
> + - description: input fclk div 4
> + - description: input fclk div 5
> + - description: input fclk div 7
> + - description: input mpll2
> + - description: input mpll3
> + - description: input gp0 pll
> + - description: input gp1 pll
> + - description: input hifi pll
> + - description: input sys clk
> + - description: input axi clk
> + - description: input sys pll div 16
> + - description: input cpu clk div 16
> + - description: input pad clock for rtc clk (optional)
> + - description: input ddr pll (optional)
> + - description: input source from clk-measure (optional)
> + - description: input rtc pll (optional)
Compared to the previous V3 version submitted by Xianwei, this update
adds an optional "rtc pll" clock source. Since the change is minor,
your "Reviewed-by" tag has been retained. I hope this doesn't cause
you too much trouble. If it doesn't make sense, please point it out.
> +
> + clock-names:
> + minItems: 18
> + items:
> + - const: xtal
> + - const: oscin
> + - const: fix
> + - const: fdiv2
> + - const: fdiv2p5
> + - const: fdiv3
> + - const: fdiv4
> + - const: fdiv5
> + - const: fdiv7
> + - const: mpll2
> + - const: mpll3
> + - const: gp0
> + - const: gp1
> + - const: hifi
> + - const: sysclk
> + - const: axiclk
> + - const: sysplldiv16
> + - const: cpudiv16
> + - const: pad_osc
> + - const: ddr
> + - const: clkmsr
> + - const: rtc
> +
> + "#clock-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/amlogic,a5-scmi-clkc.h>
> + #include <dt-bindings/clock/amlogic,a5-pll-clkc.h>
> + apb {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clock-controller@0 {
> + compatible = "amlogic,a5-peripherals-clkc";
> + reg = <0x0 0x0 0x0 0x224>;
> + #clock-cells = <1>;
> + clocks = <&xtal>,
> + <&scmi_clk CLKID_OSC>,
> + <&scmi_clk CLKID_FIXED_PLL>,
> + <&scmi_clk CLKID_FCLK_DIV2>,
> + <&scmi_clk CLKID_FCLK_DIV2P5>,
> + <&scmi_clk CLKID_FCLK_DIV3>,
> + <&scmi_clk CLKID_FCLK_DIV4>,
> + <&scmi_clk CLKID_FCLK_DIV5>,
> + <&scmi_clk CLKID_FCLK_DIV7>,
> + <&clkc_pll CLKID_MPLL2>,
> + <&clkc_pll CLKID_MPLL3>,
> + <&clkc_pll CLKID_GP0_PLL>,
> + <&scmi_clk CLKID_GP1_PLL>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&scmi_clk CLKID_SYS_CLK>,
> + <&scmi_clk CLKID_AXI_CLK>,
> + <&scmi_clk CLKID_SYS_PLL_DIV16>,
> + <&scmi_clk CLKID_CPU_CLK_DIV16>;
> + clock-names = "xtal",
> + "oscin",
> + "fix",
> + "fdiv2",
> + "fdiv2p5",
> + "fdiv3",
> + "fdiv4",
> + "fdiv5",
> + "fdiv7",
> + "mpll2",
> + "mpll3",
> + "gp0",
> + "gp1",
> + "hifi",
> + "sysclk",
> + "axiclk",
> + "sysplldiv16",
> + "cpudiv16";
> + };
> + };
> diff --git a/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h
> new file mode 100644
> index 000000000000..b8a68b7f29dc
> --- /dev/null
> +++ b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h
> @@ -0,0 +1,132 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
> + * Author: Chuan Liu <chuan.liu@amlogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H
> +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H
> +
> +#define CLKID_RTC_DUALDIV_CLKIN 0
> +#define CLKID_RTC_DUALDIV 1
> +#define CLKID_RTC_DUALDIV_SEL 2
> +#define CLKID_RTC_DUALDIV_CLKOUT 3
> +#define CLKID_RTC_CLK 4
> +#define CLKID_SYS_RESET_CTRL 5
> +#define CLKID_SYS_PWR_CTRL 6
> +#define CLKID_SYS_PAD_CTRL 7
> +#define CLKID_SYS_CTRL 8
> +#define CLKID_SYS_TS_PLL 9
> +#define CLKID_SYS_DEV_ARB 10
> +#define CLKID_SYS_MAILBOX 11
> +#define CLKID_SYS_JTAG_CTRL 12
> +#define CLKID_SYS_IR_CTRL 13
> +#define CLKID_SYS_MSR_CLK 14
> +#define CLKID_SYS_ROM 15
> +#define CLKID_SYS_CPU_ARB 16
> +#define CLKID_SYS_RSA 17
> +#define CLKID_SYS_SARADC 18
> +#define CLKID_SYS_STARTUP 19
> +#define CLKID_SYS_SECURE 20
> +#define CLKID_SYS_SPIFC 21
> +#define CLKID_SYS_DSPA 22
> +#define CLKID_SYS_NNA 23
> +#define CLKID_SYS_ETH_MAC 24
> +#define CLKID_SYS_RAMA 25
> +#define CLKID_SYS_RAMB 26
> +#define CLKID_SYS_AUDIO_TOP 27
> +#define CLKID_SYS_AUDIO_VAD 28
> +#define CLKID_SYS_USB 29
> +#define CLKID_SYS_SD_EMMC_A 30
> +#define CLKID_SYS_SD_EMMC_C 31
> +#define CLKID_SYS_PWM_AB 32
> +#define CLKID_SYS_PWM_CD 33
> +#define CLKID_SYS_PWM_EF 34
> +#define CLKID_SYS_PWM_GH 35
> +#define CLKID_SYS_SPICC_1 36
> +#define CLKID_SYS_SPICC_0 37
> +#define CLKID_SYS_UART_A 38
> +#define CLKID_SYS_UART_B 39
> +#define CLKID_SYS_UART_C 40
> +#define CLKID_SYS_UART_D 41
> +#define CLKID_SYS_UART_E 42
> +#define CLKID_SYS_I2C_M_A 43
> +#define CLKID_SYS_I2C_M_B 44
> +#define CLKID_SYS_I2C_M_C 45
> +#define CLKID_SYS_I2C_M_D 46
> +#define CLKID_SYS_RTC 47
> +#define CLKID_AXI_AUDIO_VAD 48
> +#define CLKID_AXI_AUDIO_TOP 49
> +#define CLKID_AXI_RAMB 50
> +#define CLKID_AXI_RAMA 51
> +#define CLKID_AXI_NNA 52
> +#define CLKID_AXI_DEV1_DMC 53
> +#define CLKID_AXI_DEV0_DMC 54
> +#define CLKID_AXI_DSP_DMC 55
> +#define CLKID_12_24M_IN 56
> +#define CLKID_12M_24M 57
> +#define CLKID_FCLK_25M_DIV 58
> +#define CLKID_FCLK_25M 59
> +#define CLKID_GEN_SEL 60
> +#define CLKID_GEN_DIV 61
> +#define CLKID_GEN 62
> +#define CLKID_SARADC_SEL 63
> +#define CLKID_SARADC_DIV 64
> +#define CLKID_SARADC 65
> +#define CLKID_PWM_A_SEL 66
> +#define CLKID_PWM_A_DIV 67
> +#define CLKID_PWM_A 68
> +#define CLKID_PWM_B_SEL 69
> +#define CLKID_PWM_B_DIV 70
> +#define CLKID_PWM_B 71
> +#define CLKID_PWM_C_SEL 72
> +#define CLKID_PWM_C_DIV 73
> +#define CLKID_PWM_C 74
> +#define CLKID_PWM_D_SEL 75
> +#define CLKID_PWM_D_DIV 76
> +#define CLKID_PWM_D 77
> +#define CLKID_PWM_E_SEL 78
> +#define CLKID_PWM_E_DIV 79
> +#define CLKID_PWM_E 80
> +#define CLKID_PWM_F_SEL 81
> +#define CLKID_PWM_F_DIV 82
> +#define CLKID_PWM_F 83
> +#define CLKID_PWM_G_SEL 84
> +#define CLKID_PWM_G_DIV 85
> +#define CLKID_PWM_G 86
> +#define CLKID_PWM_H_SEL 87
> +#define CLKID_PWM_H_DIV 88
> +#define CLKID_PWM_H 89
> +#define CLKID_SPICC_0_SEL 90
> +#define CLKID_SPICC_0_DIV 91
> +#define CLKID_SPICC_0 92
> +#define CLKID_SPICC_1_SEL 93
> +#define CLKID_SPICC_1_DIV 94
> +#define CLKID_SPICC_1 95
> +#define CLKID_SD_EMMC_A_SEL 96
> +#define CLKID_SD_EMMC_A_DIV 97
> +#define CLKID_SD_EMMC_A 98
> +#define CLKID_SD_EMMC_C_SEL 99
> +#define CLKID_SD_EMMC_C_DIV 100
> +#define CLKID_SD_EMMC_C 101
> +#define CLKID_TS_DIV 102
> +#define CLKID_TS 103
> +#define CLKID_ETH_125M_DIV 104
> +#define CLKID_ETH_125M 105
> +#define CLKID_ETH_RMII_DIV 106
> +#define CLKID_ETH_RMII 107
> +#define CLKID_DSPA_0_SEL 108
> +#define CLKID_DSPA_0_DIV 109
> +#define CLKID_DSPA_0 110
> +#define CLKID_DSPA_1_SEL 111
> +#define CLKID_DSPA_1_DIV 112
> +#define CLKID_DSPA_1 113
> +#define CLKID_DSPA 114
> +#define CLKID_NNA_CORE_SEL 115
> +#define CLKID_NNA_CORE_DIV 116
> +#define CLKID_NNA_CORE 117
> +#define CLKID_NNA_AXI_SEL 118
> +#define CLKID_NNA_AXI_DIV 119
> +#define CLKID_NNA_AXI 120
> +
> +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H */
>
> --
> 2.42.0
>
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (18 preceding siblings ...)
2025-09-30 9:37 ` [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
@ 2025-09-30 14:39 ` Rob Herring (Arm)
2025-10-01 7:45 ` Jerome Brunet
20 siblings, 0 replies; 33+ messages in thread
From: Rob Herring (Arm) @ 2025-09-30 14:39 UTC (permalink / raw)
To: Chuan Liu
Cc: Conor Dooley, Jerome Brunet, Michael Turquette, Xianwei Zhao,
Krzysztof Kozlowski, Neil Armstrong, Martin Blumenstingl,
linux-clk, Stephen Boyd, linux-kernel, linux-amlogic,
linux-arm-kernel, devicetree, Kevin Hilman
On Tue, 30 Sep 2025 17:37:13 +0800, Chuan Liu wrote:
> This patch series includes changes related to the PLL and peripheral
> clocks for both the A4 and A5 SoCs.
>
> The patches for A5 were previously submitted up to V3 by Xianwei.
> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
> After friendly coordination, I’ve taken over and continued the
> submission as part of this series. The dt-bindings patch retains Rob's
> original "Reviewed-by" tag, and I hope this hasn’t caused any
> additional confusion.
>
> Both A4 and A5 belong to the Audio series. Judging by their names, one
> might assume that A5 is an upgrade to A4, but in fact, A5 was released
> a year earlier than A4.
>
> Since there are differences in the PLLs and peripheral clocks between
> the A4 and A5 SoCs (especially the PLL), and taking into account factors
> such as memory footprint and maintainability, this series does not
> attempt to merge the two into a shared driver as was done for
> G12A/G12B/SM1.
>
> This patch series includes all related dt-bindings, driver, and dts
> changes for the PLLs and peripheral clocks. Following our past convention
> for clock-related submissions, the dts changes are placed at the end
> and submitted separately. If this ordering makes it harder for
> maintainers to review or pick patches, please feel free to point it out.
>
> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> Chuan Liu (19):
> dt-bindings: clock: Add Amlogic A4 SCMI clock controller
> dt-bindings: clock: Add Amlogic A4 PLL clock controller
> dt-bindings: clock: Add Amlogic A4 peripherals clock controller
> clk: amlogic: Optimize PLL enable timing
> clk: amlogic: Correct l_detect bit control
> clk: amlogic: Fix out-of-range PLL frequency setting
> clk: amlogic: Add A4 PLL clock controller driver
> clk: amlogic: Add A4 clock peripherals controller driver
> arm64: dts: amlogic: A4: Add scmi-clk node
> arm64: dts: amlogic: A4: Add PLL controller node
> arm64: dts: amlogic: A4: Add peripherals clock controller node
> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
> dt-bindings: clock: Add Amlogic A5 PLL clock controller
> dt-bindings: clock: Add Amlogic A5 peripherals clock controller
> clk: amlogic: Add A5 PLL clock controller driver
> clk: amlogic: Add A5 clock peripherals controller driver
> arm64: dts: amlogic: A5: Add scmi-clk node
> arm64: dts: amlogic: A5: Add PLL controller node
> arm64: dts: amlogic: A5: Add peripheral clock controller node
>
> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
> drivers/clk/meson/Kconfig | 53 ++
> drivers/clk/meson/Makefile | 4 +
> drivers/clk/meson/a1-pll.c | 1 +
> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
> drivers/clk/meson/a4-pll.c | 242 ++++++
> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
> drivers/clk/meson/a5-pll.c | 476 +++++++++++
> drivers/clk/meson/clk-pll.c | 76 +-
> drivers/clk/meson/clk-pll.h | 2 +
> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++
> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++
> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
> 21 files changed, 3406 insertions(+), 28 deletions(-)
> ---
> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
>
> Best regards,
> --
> Chuan Liu <chuan.liu@amlogic.com>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: using specified base-commit 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/amlogic/' for 20250930-a4_a5_add_clock_driver-v1-0-a9acf7951589@amlogic.com:
Error: arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi:119.19-20 syntax error
FATAL ERROR: Unable to parse input tree
make[3]: *** [scripts/Makefile.dtbs:131: arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/amlogic] Error 2
make[2]: Target 'arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1480: amlogic/amlogic-a4-a113l2-ba400.dtb] Error 2
make: *** [Makefile:248: __sub-make] Error 2
make: Target 'amlogic/meson-gxl-s905x-hwacom-amazetv.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905d-sml5442tw.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905d-phicomm-n1.dtb' not remade because of errors.
make: Target 'amlogic/meson-s4-s805x2-aq222.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905w-p281.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-s912-libretech-pc.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12a-sei510.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-q200.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905x-khadas-vim.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxlx-s905l-p271.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-mecool-kiii-pro.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-vega-s96.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12a-fbx8am.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-bananapi-cm4-cm4io.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-c3-c308l-aw419.dtb' not remade because of errors.
make: Target 'amlogic/meson-axg-s400.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-nexbox-a1.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-dreambox-one.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-khadas-vim2.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-wetek-core2.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12a-radxa-zero.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-vega-s95-telos.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905x-libretech-cc-v2.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-a311d-khadas-vim3.dtb' not remade because of errors.
make: Target 'amlogic/meson-axg-jethome-jethub-j100.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-gsking-x.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-vega-s95-pro.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-q201.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905d-p230.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-a311d-bananapi-m2s.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-wetek-play2.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905d-mecool-kii-pro.dtb' not remade because of errors.
make: Target 'amlogic/meson-axg-jethome-jethub-j110-rev-2.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-odroidc2.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-s7d-s905x5m-bm202.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-gt1-ultimate.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12a-x96-max.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905d-libretech-pc.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905d-p231.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-ugoos-am3.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-x96-air.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905x-vero4k.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-vega-s95-meta.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905w-tx3-mini.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-minix-neo-u9h.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s805x-libretech-ac.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-a95xf3-air-gbit.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-khadas-vim3l.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905d-vero4k-plus.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-h96-max.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905x-p212.dtb' not remade because of errors.
make: Target 'amlogic/meson-a1-ad401.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-odroid-go-ultra.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-radxa-zero2.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-x96-air-gbit.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-dreambox-two.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-bananapi-m5.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12a-u200.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxm-rbox-pro.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-p201.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-a95xf3-air.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-a4-a113l2-ba400.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s805y-xiaomi-aquaman.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-bananapi-m2-pro.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-p200.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-odroid-c4.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-s922x-bananapi-m2s.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-sei610.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-odroid-hc4.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-odroid-n2l.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905x-libretech-cc.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-c3-c302x-aw409.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905x-nexbox-a95x.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-a311d-libretech-cc.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-t7-a311d2-khadas-vim4.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s905w-jethome-jethub-j80.dtb' not remade because of errors.
make: Target 'amlogic/meson-sm1-s905d3-libretech-cc.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-a5-a113x2-av400.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-wetek-hub.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-s922x-khadas-vim3.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-s6-s905x5-bl209.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-t7-a311d2-an400.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-kii-pro.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-odroid-n2.dtb' not remade because of errors.
make: Target 'amlogic/meson-a1-ad402.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-nexbox-a95x.dtb' not remade because of errors.
make: Target 'amlogic/meson-axg-jethome-jethub-j110-rev-3.dtb' not remade because of errors.
make: Target 'amlogic/amlogic-s7-s805x3-bp201.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-odroid-n2-plus.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-gtking-pro.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-ugoos-am6.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxl-s805x-p241.dtb' not remade because of errors.
make: Target 'amlogic/meson-g12b-gtking.dtb' not remade because of errors.
make: Target 'amlogic/meson-gxbb-nanopi-k2.dtb' not remade because of errors.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
` (19 preceding siblings ...)
2025-09-30 14:39 ` [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Rob Herring (Arm)
@ 2025-10-01 7:45 ` Jerome Brunet
2025-10-09 3:09 ` Chuan Liu
20 siblings, 1 reply; 33+ messages in thread
From: Jerome Brunet @ 2025-10-01 7:45 UTC (permalink / raw)
To: Chuan Liu via B4 Relay
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
chuan.liu, linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao
On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
> This patch series includes changes related to the PLL and peripheral
> clocks for both the A4 and A5 SoCs.
>
> The patches for A5 were previously submitted up to V3 by Xianwei.
> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
> After friendly coordination, I’ve taken over and continued the
> submission as part of this series. The dt-bindings patch retains Rob's
> original "Reviewed-by" tag, and I hope this hasn’t caused any
> additional confusion.
... and yet you restart the versioning of the series making it harder
for people to follow that
>
> Both A4 and A5 belong to the Audio series. Judging by their names, one
> might assume that A5 is an upgrade to A4, but in fact, A5 was released
> a year earlier than A4.
>
> Since there are differences in the PLLs and peripheral clocks between
> the A4 and A5 SoCs (especially the PLL), and taking into account factors
> such as memory footprint and maintainability, this series does not
> attempt to merge the two into a shared driver as was done for
> G12A/G12B/SM1.
... and we end up with 19 patches series while it could be splitted into
manageable series, for each controller of each SoC
>
> This patch series includes all related dt-bindings, driver, and dts
> changes for the PLLs and peripheral clocks. Following our past convention
> for clock-related submissions, the dts changes are placed at the end
> and submitted separately. If this ordering makes it harder for
> maintainers to review or pick patches, please feel free to point it out.
>
> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> Chuan Liu (19):
> dt-bindings: clock: Add Amlogic A4 SCMI clock controller
> dt-bindings: clock: Add Amlogic A4 PLL clock controller
> dt-bindings: clock: Add Amlogic A4 peripherals clock controller
> clk: amlogic: Optimize PLL enable timing
> clk: amlogic: Correct l_detect bit control
> clk: amlogic: Fix out-of-range PLL frequency setting
> clk: amlogic: Add A4 PLL clock controller driver
> clk: amlogic: Add A4 clock peripherals controller driver
> arm64: dts: amlogic: A4: Add scmi-clk node
> arm64: dts: amlogic: A4: Add PLL controller node
> arm64: dts: amlogic: A4: Add peripherals clock controller node
> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
> dt-bindings: clock: Add Amlogic A5 PLL clock controller
> dt-bindings: clock: Add Amlogic A5 peripherals clock controller
> clk: amlogic: Add A5 PLL clock controller driver
> clk: amlogic: Add A5 clock peripherals controller driver
> arm64: dts: amlogic: A5: Add scmi-clk node
> arm64: dts: amlogic: A5: Add PLL controller node
> arm64: dts: amlogic: A5: Add peripheral clock controller node
>
> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
> drivers/clk/meson/Kconfig | 53 ++
> drivers/clk/meson/Makefile | 4 +
> drivers/clk/meson/a1-pll.c | 1 +
> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
> drivers/clk/meson/a4-pll.c | 242 ++++++
> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
> drivers/clk/meson/a5-pll.c | 476 +++++++++++
> drivers/clk/meson/clk-pll.c | 76 +-
> drivers/clk/meson/clk-pll.h | 2 +
> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++
> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++
> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
> 21 files changed, 3406 insertions(+), 28 deletions(-)
> ---
> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
>
> Best regards,
--
Jerome
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node
2025-09-30 9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
@ 2025-10-07 19:33 ` kernel test robot
2025-10-10 4:21 ` kernel test robot
1 sibling, 0 replies; 33+ messages in thread
From: kernel test robot @ 2025-10-07 19:33 UTC (permalink / raw)
To: Chuan Liu via B4 Relay, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Jerome Brunet, Kevin Hilman, Martin Blumenstingl
Cc: oe-kbuild-all, linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao, Chuan Liu
Hi Chuan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf]
url: https://github.com/intel-lab-lkp/linux/commits/Chuan-Liu-via-B4-Relay/dt-bindings-clock-Add-Amlogic-A4-SCMI-clock-controller/20250930-174011
base: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
patch link: https://lore.kernel.org/r/20250930-a4_a5_add_clock_driver-v1-11-a9acf7951589%40amlogic.com
patch subject: [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node
config: arm64-randconfig-2051-20251007 (https://download.01.org/0day-ci/archive/20251007/202510072131.VRSrXJh7-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project c410e88f0f8c0654d7744d6d029009f9cb736143)
dtschema version: 2025.8
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251007/202510072131.VRSrXJh7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510072131.VRSrXJh7-lkp@intel.com/
All errors (new ones prefixed by >>):
Error: arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi:119.19-20 syntax error
>> FATAL ERROR: Unable to parse input tree
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
2025-10-01 7:45 ` Jerome Brunet
@ 2025-10-09 3:09 ` Chuan Liu
2025-10-09 7:59 ` Jerome Brunet
0 siblings, 1 reply; 33+ messages in thread
From: Chuan Liu @ 2025-10-09 3:09 UTC (permalink / raw)
To: Jerome Brunet, Chuan Liu via B4 Relay
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
linux-kernel, linux-clk, devicetree, linux-amlogic,
linux-arm-kernel, Xianwei Zhao
Hi Jerome,
Thanks for your review, because the national day holidays did not
timely feedback.
On 10/1/2025 3:45 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>
>> This patch series includes changes related to the PLL and peripheral
>> clocks for both the A4 and A5 SoCs.
>>
>> The patches for A5 were previously submitted up to V3 by Xianwei.
>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
>> After friendly coordination, I’ve taken over and continued the
>> submission as part of this series. The dt-bindings patch retains Rob's
>> original "Reviewed-by" tag, and I hope this hasn’t caused any
>> additional confusion.
> ... and yet you restart the versioning of the series making it harder
> for people to follow that
Sorry for the inconvenience caused. The main changes compared to the
previous version by Xianwei are in the driver part.
The dt-bindings part only has minor modifications in [PATCH 14/19].
The driver part has relatively larger changes because it needs to be
based on the code base you previously submitted.
>> Both A4 and A5 belong to the Audio series. Judging by their names, one
>> might assume that A5 is an upgrade to A4, but in fact, A5 was released
>> a year earlier than A4.
>>
>> Since there are differences in the PLLs and peripheral clocks between
>> the A4 and A5 SoCs (especially the PLL), and taking into account factors
>> such as memory footprint and maintainability, this series does not
>> attempt to merge the two into a shared driver as was done for
>> G12A/G12B/SM1.
> ... and we end up with 19 patches series while it could be splitted into
> manageable series, for each controller of each SoC
I'm not sure if I understood you correctly.
Do you mean that I should split this series of 19 patches into multiple
patch series and send them separately? For example:
serie 1: A4 SCMI clock controller (dt-bindings)
serie 2: A4 PLL clock controller (dt-bindings, driver, dts)
serie 3: A4 peripherals clock controller (dt-bindings, driver, dts)
... A5 similarly?
>> This patch series includes all related dt-bindings, driver, and dts
>> changes for the PLLs and peripheral clocks. Following our past convention
>> for clock-related submissions, the dts changes are placed at the end
>> and submitted separately. If this ordering makes it harder for
>> maintainers to review or pick patches, please feel free to point it out.
>>
>> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
>> ---
>> Chuan Liu (19):
>> dt-bindings: clock: Add Amlogic A4 SCMI clock controller
>> dt-bindings: clock: Add Amlogic A4 PLL clock controller
>> dt-bindings: clock: Add Amlogic A4 peripherals clock controller
>> clk: amlogic: Optimize PLL enable timing
>> clk: amlogic: Correct l_detect bit control
>> clk: amlogic: Fix out-of-range PLL frequency setting
>> clk: amlogic: Add A4 PLL clock controller driver
>> clk: amlogic: Add A4 clock peripherals controller driver
>> arm64: dts: amlogic: A4: Add scmi-clk node
>> arm64: dts: amlogic: A4: Add PLL controller node
>> arm64: dts: amlogic: A4: Add peripherals clock controller node
>> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
>> dt-bindings: clock: Add Amlogic A5 PLL clock controller
>> dt-bindings: clock: Add Amlogic A5 peripherals clock controller
>> clk: amlogic: Add A5 PLL clock controller driver
>> clk: amlogic: Add A5 clock peripherals controller driver
>> arm64: dts: amlogic: A5: Add scmi-clk node
>> arm64: dts: amlogic: A5: Add PLL controller node
>> arm64: dts: amlogic: A5: Add peripheral clock controller node
>>
>> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
>> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
>> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
>> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
>> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
>> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
>> drivers/clk/meson/Kconfig | 53 ++
>> drivers/clk/meson/Makefile | 4 +
>> drivers/clk/meson/a1-pll.c | 1 +
>> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
>> drivers/clk/meson/a4-pll.c | 242 ++++++
>> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
>> drivers/clk/meson/a5-pll.c | 476 +++++++++++
>> drivers/clk/meson/clk-pll.c | 76 +-
>> drivers/clk/meson/clk-pll.h | 2 +
>> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++
>> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
>> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
>> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++
>> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
>> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
>> 21 files changed, 3406 insertions(+), 28 deletions(-)
>> ---
>> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
>> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
>>
>> Best regards,
> --
> Jerome
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
2025-10-09 3:09 ` Chuan Liu
@ 2025-10-09 7:59 ` Jerome Brunet
2025-10-10 2:38 ` Chuan Liu
0 siblings, 1 reply; 33+ messages in thread
From: Jerome Brunet @ 2025-10-09 7:59 UTC (permalink / raw)
To: Chuan Liu
Cc: Chuan Liu via B4 Relay, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Martin Blumenstingl, linux-kernel, linux-clk,
devicetree, linux-amlogic, linux-arm-kernel, Xianwei Zhao
On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote:
> Hi Jerome,
>
> Thanks for your review, because the national day holidays did not
> timely feedback.
>
>
> On 10/1/2025 3:45 PM, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay
>> <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>>
>>> This patch series includes changes related to the PLL and peripheral
>>> clocks for both the A4 and A5 SoCs.
>>>
>>> The patches for A5 were previously submitted up to V3 by Xianwei.
>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
>>> After friendly coordination, I’ve taken over and continued the
>>> submission as part of this series. The dt-bindings patch retains Rob's
>>> original "Reviewed-by" tag, and I hope this hasn’t caused any
>>> additional confusion.
>> ... and yet you restart the versioning of the series making it harder
>> for people to follow that
>
>
> Sorry for the inconvenience caused. The main changes compared to the
> previous version by Xianwei are in the driver part.
>
> The dt-bindings part only has minor modifications in [PATCH 14/19].
>
> The driver part has relatively larger changes because it needs to be
> based on the code base you previously submitted.
I'm not seeing a justification for the mess introduced and I'm not
looking for one to be honest
>
>>> Both A4 and A5 belong to the Audio series. Judging by their names, one
>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released
>>> a year earlier than A4.
>>>
>>> Since there are differences in the PLLs and peripheral clocks between
>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors
>>> such as memory footprint and maintainability, this series does not
>>> attempt to merge the two into a shared driver as was done for
>>> G12A/G12B/SM1.
>> ... and we end up with 19 patches series while it could be splitted into
>> manageable series, for each controller of each SoC
>
>
> I'm not sure if I understood you correctly.
>
> Do you mean that I should split this series of 19 patches into multiple
> patch series and send them separately? For example:
> serie 1: A4 SCMI clock controller (dt-bindings)
> serie 2: A4 PLL clock controller (dt-bindings, driver, dts)
> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts)
> ... A5 similarly?
Things that do not actually depends on each other or which are not
merged through the same tree should not be sent together. There is
nothing new here. Same basic reminders on each submission.
>
>
>>> This patch series includes all related dt-bindings, driver, and dts
>>> changes for the PLLs and peripheral clocks. Following our past convention
>>> for clock-related submissions, the dts changes are placed at the end
>>> and submitted separately. If this ordering makes it harder for
>>> maintainers to review or pick patches, please feel free to point it out.
>>>
>>> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
>>> ---
>>> Chuan Liu (19):
>>> dt-bindings: clock: Add Amlogic A4 SCMI clock controller
>>> dt-bindings: clock: Add Amlogic A4 PLL clock controller
>>> dt-bindings: clock: Add Amlogic A4 peripherals clock controller
>>> clk: amlogic: Optimize PLL enable timing
>>> clk: amlogic: Correct l_detect bit control
>>> clk: amlogic: Fix out-of-range PLL frequency setting
>>> clk: amlogic: Add A4 PLL clock controller driver
>>> clk: amlogic: Add A4 clock peripherals controller driver
>>> arm64: dts: amlogic: A4: Add scmi-clk node
>>> arm64: dts: amlogic: A4: Add PLL controller node
>>> arm64: dts: amlogic: A4: Add peripherals clock controller node
>>> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
>>> dt-bindings: clock: Add Amlogic A5 PLL clock controller
>>> dt-bindings: clock: Add Amlogic A5 peripherals clock controller
>>> clk: amlogic: Add A5 PLL clock controller driver
>>> clk: amlogic: Add A5 clock peripherals controller driver
>>> arm64: dts: amlogic: A5: Add scmi-clk node
>>> arm64: dts: amlogic: A5: Add PLL controller node
>>> arm64: dts: amlogic: A5: Add peripheral clock controller node
>>>
>>> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
>>> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
>>> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
>>> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
>>> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
>>> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
>>> drivers/clk/meson/Kconfig | 53 ++
>>> drivers/clk/meson/Makefile | 4 +
>>> drivers/clk/meson/a1-pll.c | 1 +
>>> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
>>> drivers/clk/meson/a4-pll.c | 242 ++++++
>>> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
>>> drivers/clk/meson/a5-pll.c | 476 +++++++++++
>>> drivers/clk/meson/clk-pll.c | 76 +-
>>> drivers/clk/meson/clk-pll.h | 2 +
>>> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++
>>> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
>>> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
>>> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++
>>> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
>>> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
>>> 21 files changed, 3406 insertions(+), 28 deletions(-)
>>> ---
>>> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
>>> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
>>>
>>> Best regards,
>> --
>> Jerome
--
Jerome
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals clock controller
2025-09-30 9:37 ` [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals " Chuan Liu via B4 Relay
@ 2025-10-09 18:04 ` Rob Herring (Arm)
0 siblings, 0 replies; 33+ messages in thread
From: Rob Herring (Arm) @ 2025-10-09 18:04 UTC (permalink / raw)
To: Chuan Liu
Cc: Kevin Hilman, Michael Turquette, Neil Armstrong,
Martin Blumenstingl, Stephen Boyd, linux-amlogic, Jerome Brunet,
linux-clk, Conor Dooley, Xianwei Zhao, Krzysztof Kozlowski,
linux-arm-kernel, linux-kernel, devicetree
On Tue, 30 Sep 2025 17:37:16 +0800, Chuan Liu wrote:
> Add the peripherals clock controller dt-bindings for the Amlogic A4
> SoC family.
>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++++++++++++++++++
> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++++++++++++++++++++
> 2 files changed, 251 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL clock controller
2025-09-30 9:37 ` [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL " Chuan Liu via B4 Relay
@ 2025-10-09 18:04 ` Rob Herring (Arm)
0 siblings, 0 replies; 33+ messages in thread
From: Rob Herring (Arm) @ 2025-10-09 18:04 UTC (permalink / raw)
To: Chuan Liu
Cc: Krzysztof Kozlowski, Martin Blumenstingl, Xianwei Zhao,
Neil Armstrong, devicetree, linux-clk, linux-kernel,
linux-amlogic, Jerome Brunet, Conor Dooley, linux-arm-kernel,
Kevin Hilman, Stephen Boyd, Michael Turquette
On Tue, 30 Sep 2025 17:37:15 +0800, Chuan Liu wrote:
> Add the PLL clock controller dt-bindings for Amlogic A4 SoC family.
>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++++++++++++++++++++++
> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 ++++++
> 2 files changed, 76 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller
2025-09-30 9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
@ 2025-10-09 18:07 ` Rob Herring (Arm)
0 siblings, 0 replies; 33+ messages in thread
From: Rob Herring (Arm) @ 2025-10-09 18:07 UTC (permalink / raw)
To: Chuan Liu
Cc: linux-clk, Conor Dooley, Krzysztof Kozlowski, linux-kernel,
devicetree, linux-arm-kernel, Xianwei Zhao, Neil Armstrong,
Kevin Hilman, Stephen Boyd, linux-amlogic, Jerome Brunet,
Michael Turquette, Martin Blumenstingl
On Tue, 30 Sep 2025 17:37:14 +0800, Chuan Liu wrote:
> Add the SCMI clock controller dt-bindings for Amlogic A4 SoC family.
>
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 ++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
2025-10-09 7:59 ` Jerome Brunet
@ 2025-10-10 2:38 ` Chuan Liu
2025-10-10 2:42 ` Krzysztof Kozlowski
0 siblings, 1 reply; 33+ messages in thread
From: Chuan Liu @ 2025-10-10 2:38 UTC (permalink / raw)
To: Jerome Brunet
Cc: Chuan Liu via B4 Relay, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Martin Blumenstingl, linux-kernel, linux-clk,
devicetree, linux-amlogic, linux-arm-kernel, Xianwei Zhao
Hi Jerome,
On 10/9/2025 3:59 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote:
>
>> Hi Jerome,
>>
>> Thanks for your review, because the national day holidays did not
>> timely feedback.
>>
>>
>> On 10/1/2025 3:45 PM, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay
>>> <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>>>
>>>> This patch series includes changes related to the PLL and peripheral
>>>> clocks for both the A4 and A5 SoCs.
>>>>
>>>> The patches for A5 were previously submitted up to V3 by Xianwei.
>>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
>>>> After friendly coordination, I’ve taken over and continued the
>>>> submission as part of this series. The dt-bindings patch retains Rob's
>>>> original "Reviewed-by" tag, and I hope this hasn’t caused any
>>>> additional confusion.
>>> ... and yet you restart the versioning of the series making it harder
>>> for people to follow that
>>
>> Sorry for the inconvenience caused. The main changes compared to the
>> previous version by Xianwei are in the driver part.
>>
>> The dt-bindings part only has minor modifications in [PATCH 14/19].
>>
>> The driver part has relatively larger changes because it needs to be
>> based on the code base you previously submitted.
> I'm not seeing a justification for the mess introduced and I'm not
> looking for one to be honest
Previously, I provided a basic version of the A5 clock driver to
Xianwei, and he helped improve it before submitting it.
Xianwei has been responsible for upstreaming many of our modules.
Since clock drivers require significant effort, I’m sharing the
workload by submitting some of the clock-related patches.
The three versions previously submitted by Xianwei mainly focused on
improving the dt-bindings based on Rob’s feedback. The driver part
remained unchanged.
The driver part in my current patch series has undergone relatively
large modifications to adapt to the latest code base, so comparing it
to the previous versions may not be very meaningful.
If it's more appropriate for the A5 clock-related patches to continue
evolving based on Xianwei's earlier v3 series, please feel free to
point it out. I will continue to assist Xianwei in completing the
submission of the remaining A5 clock patches.
>>>> Both A4 and A5 belong to the Audio series. Judging by their names, one
>>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released
>>>> a year earlier than A4.
>>>>
>>>> Since there are differences in the PLLs and peripheral clocks between
>>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors
>>>> such as memory footprint and maintainability, this series does not
>>>> attempt to merge the two into a shared driver as was done for
>>>> G12A/G12B/SM1.
>>> ... and we end up with 19 patches series while it could be splitted into
>>> manageable series, for each controller of each SoC
>>
>> I'm not sure if I understood you correctly.
>>
>> Do you mean that I should split this series of 19 patches into multiple
>> patch series and send them separately? For example:
>> serie 1: A4 SCMI clock controller (dt-bindings)
>> serie 2: A4 PLL clock controller (dt-bindings, driver, dts)
>> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts)
>> ... A5 similarly?
> Things that do not actually depends on each other or which are not
> merged through the same tree should not be sent together. There is
> nothing new here. Same basic reminders on each submission.
Sorry, but I'm still not quite sure if I understood you correctly.
This series of 19 patches mainly falls into three major categories:
* Optimize PLL driver
* PLLs and peripherals for A4
* PLLs and peripherals for A5
Are you suggesting that the PLL driver part should be sent as a
separate patch series, while the A4 and A5 parts should still follow
the previous A5/C3-style submission?
>>
>>>> This patch series includes all related dt-bindings, driver, and dts
>>>> changes for the PLLs and peripheral clocks. Following our past convention
>>>> for clock-related submissions, the dts changes are placed at the end
>>>> and submitted separately. If this ordering makes it harder for
>>>> maintainers to review or pick patches, please feel free to point it out.
>>>>
>>>> Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>>> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
>>>> ---
>>>> Chuan Liu (19):
>>>> dt-bindings: clock: Add Amlogic A4 SCMI clock controller
>>>> dt-bindings: clock: Add Amlogic A4 PLL clock controller
>>>> dt-bindings: clock: Add Amlogic A4 peripherals clock controller
>>>> clk: amlogic: Optimize PLL enable timing
>>>> clk: amlogic: Correct l_detect bit control
>>>> clk: amlogic: Fix out-of-range PLL frequency setting
>>>> clk: amlogic: Add A4 PLL clock controller driver
>>>> clk: amlogic: Add A4 clock peripherals controller driver
>>>> arm64: dts: amlogic: A4: Add scmi-clk node
>>>> arm64: dts: amlogic: A4: Add PLL controller node
>>>> arm64: dts: amlogic: A4: Add peripherals clock controller node
>>>> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
>>>> dt-bindings: clock: Add Amlogic A5 PLL clock controller
>>>> dt-bindings: clock: Add Amlogic A5 peripherals clock controller
>>>> clk: amlogic: Add A5 PLL clock controller driver
>>>> clk: amlogic: Add A5 clock peripherals controller driver
>>>> arm64: dts: amlogic: A5: Add scmi-clk node
>>>> arm64: dts: amlogic: A5: Add PLL controller node
>>>> arm64: dts: amlogic: A5: Add peripheral clock controller node
>>>>
>>>> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++
>>>> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++
>>>> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
>>>> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
>>>> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++
>>>> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++
>>>> drivers/clk/meson/Kconfig | 53 ++
>>>> drivers/clk/meson/Makefile | 4 +
>>>> drivers/clk/meson/a1-pll.c | 1 +
>>>> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++
>>>> drivers/clk/meson/a4-pll.c | 242 ++++++
>>>> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++
>>>> drivers/clk/meson/a5-pll.c | 476 +++++++++++
>>>> drivers/clk/meson/clk-pll.c | 76 +-
>>>> drivers/clk/meson/clk-pll.h | 2 +
>>>> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++
>>>> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 +
>>>> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 +
>>>> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++
>>>> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
>>>> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 +
>>>> 21 files changed, 3406 insertions(+), 28 deletions(-)
>>>> ---
>>>> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
>>>> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633
>>>>
>>>> Best regards,
>>> --
>>> Jerome
> --
> Jerome
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
2025-10-10 2:38 ` Chuan Liu
@ 2025-10-10 2:42 ` Krzysztof Kozlowski
2025-10-10 6:15 ` Chuan Liu
0 siblings, 1 reply; 33+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-10 2:42 UTC (permalink / raw)
To: Chuan Liu, Jerome Brunet
Cc: Chuan Liu via B4 Relay, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Martin Blumenstingl, linux-kernel, linux-clk,
devicetree, linux-amlogic, linux-arm-kernel, Xianwei Zhao
On 10/10/2025 04:38, Chuan Liu wrote:
> Hi Jerome,
>
>
> On 10/9/2025 3:59 PM, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote:
>>
>>> Hi Jerome,
>>>
>>> Thanks for your review, because the national day holidays did not
>>> timely feedback.
>>>
>>>
>>> On 10/1/2025 3:45 PM, Jerome Brunet wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay
>>>> <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>>>>
>>>>> This patch series includes changes related to the PLL and peripheral
>>>>> clocks for both the A4 and A5 SoCs.
>>>>>
>>>>> The patches for A5 were previously submitted up to V3 by Xianwei.
>>>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
>>>>> After friendly coordination, I’ve taken over and continued the
>>>>> submission as part of this series. The dt-bindings patch retains Rob's
>>>>> original "Reviewed-by" tag, and I hope this hasn’t caused any
>>>>> additional confusion.
>>>> ... and yet you restart the versioning of the series making it harder
>>>> for people to follow that
>>>
>>> Sorry for the inconvenience caused. The main changes compared to the
>>> previous version by Xianwei are in the driver part.
>>>
>>> The dt-bindings part only has minor modifications in [PATCH 14/19].
>>>
>>> The driver part has relatively larger changes because it needs to be
>>> based on the code base you previously submitted.
>> I'm not seeing a justification for the mess introduced and I'm not
>> looking for one to be honest
>
>
> Previously, I provided a basic version of the A5 clock driver to
> Xianwei, and he helped improve it before submitting it.
>
> Xianwei has been responsible for upstreaming many of our modules.
> Since clock drivers require significant effort, I’m sharing the
> workload by submitting some of the clock-related patches.
>
> The three versions previously submitted by Xianwei mainly focused on
> improving the dt-bindings based on Rob’s feedback. The driver part
> remained unchanged.
>
> The driver part in my current patch series has undergone relatively
> large modifications to adapt to the latest code base, so comparing it
> to the previous versions may not be very meaningful.
>
> If it's more appropriate for the A5 clock-related patches to continue
> evolving based on Xianwei's earlier v3 series, please feel free to
> point it out. I will continue to assist Xianwei in completing the
> submission of the remaining A5 clock patches.
>
>
>>>>> Both A4 and A5 belong to the Audio series. Judging by their names, one
>>>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released
>>>>> a year earlier than A4.
>>>>>
>>>>> Since there are differences in the PLLs and peripheral clocks between
>>>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors
>>>>> such as memory footprint and maintainability, this series does not
>>>>> attempt to merge the two into a shared driver as was done for
>>>>> G12A/G12B/SM1.
>>>> ... and we end up with 19 patches series while it could be splitted into
>>>> manageable series, for each controller of each SoC
>>>
>>> I'm not sure if I understood you correctly.
>>>
>>> Do you mean that I should split this series of 19 patches into multiple
>>> patch series and send them separately? For example:
>>> serie 1: A4 SCMI clock controller (dt-bindings)
>>> serie 2: A4 PLL clock controller (dt-bindings, driver, dts)
>>> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts)
>>> ... A5 similarly?
>> Things that do not actually depends on each other or which are not
>> merged through the same tree should not be sent together. There is
>> nothing new here. Same basic reminders on each submission.
>
>
> Sorry, but I'm still not quite sure if I understood you correctly.
>
> This series of 19 patches mainly falls into three major categories:
> * Optimize PLL driver
> * PLLs and peripherals for A4
> * PLLs and peripherals for A5
>
> Are you suggesting that the PLL driver part should be sent as a
> separate patch series, while the A4 and A5 parts should still follow
> the previous A5/C3-style submission?
>
Please read submitting patches, soc maintainer profile and DT submitting
patches documents. You ask us to repeat same knowledge multiple times.
It's waste of our time, so we have documented it for your convenience.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node
2025-09-30 9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
2025-10-07 19:33 ` kernel test robot
@ 2025-10-10 4:21 ` kernel test robot
1 sibling, 0 replies; 33+ messages in thread
From: kernel test robot @ 2025-10-10 4:21 UTC (permalink / raw)
To: Chuan Liu via B4 Relay, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Jerome Brunet, Kevin Hilman, Martin Blumenstingl
Cc: llvm, oe-kbuild-all, linux-kernel, linux-clk, devicetree,
linux-amlogic, linux-arm-kernel, Xianwei Zhao, Chuan Liu
Hi Chuan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf]
url: https://github.com/intel-lab-lkp/linux/commits/Chuan-Liu-via-B4-Relay/dt-bindings-clock-Add-Amlogic-A4-SCMI-clock-controller/20250930-174011
base: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
patch link: https://lore.kernel.org/r/20250930-a4_a5_add_clock_driver-v1-11-a9acf7951589%40amlogic.com
patch subject: [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock controller node
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20251010/202510101124.3xwn3STp-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251010/202510101124.3xwn3STp-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510101124.3xwn3STp-lkp@intel.com/
All errors (new ones prefixed by >>):
Error: arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi:119.19-20 syntax error
>> FATAL ERROR: Unable to parse input tree
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs
2025-10-10 2:42 ` Krzysztof Kozlowski
@ 2025-10-10 6:15 ` Chuan Liu
0 siblings, 0 replies; 33+ messages in thread
From: Chuan Liu @ 2025-10-10 6:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Jerome Brunet
Cc: Chuan Liu via B4 Relay, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Martin Blumenstingl, linux-kernel, linux-clk,
devicetree, linux-amlogic, linux-arm-kernel, Xianwei Zhao
Hi Krzysztof,
Sorry for bothering you unintentionally. I haven't fully understood
some of the details yet, I'll do my best to work through them.
Thanks again for your reminder.
On 10/10/2025 10:42 AM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 10/10/2025 04:38, Chuan Liu wrote:
>> Hi Jerome,
>>
>>
>> On 10/9/2025 3:59 PM, Jerome Brunet wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu 09 Oct 2025 at 11:09, Chuan Liu <chuan.liu@amlogic.com> wrote:
>>>
>>>> Hi Jerome,
>>>>
>>>> Thanks for your review, because the national day holidays did not
>>>> timely feedback.
>>>>
>>>>
>>>> On 10/1/2025 3:45 PM, Jerome Brunet wrote:
>>>>> [ EXTERNAL EMAIL ]
>>>>>
>>>>> On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay
>>>>> <devnull+chuan.liu.amlogic.com@kernel.org> wrote:
>>>>>
>>>>>> This patch series includes changes related to the PLL and peripheral
>>>>>> clocks for both the A4 and A5 SoCs.
>>>>>>
>>>>>> The patches for A5 were previously submitted up to V3 by Xianwei.
>>>>>> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/
>>>>>> After friendly coordination, I’ve taken over and continued the
>>>>>> submission as part of this series. The dt-bindings patch retains Rob's
>>>>>> original "Reviewed-by" tag, and I hope this hasn’t caused any
>>>>>> additional confusion.
>>>>> ... and yet you restart the versioning of the series making it harder
>>>>> for people to follow that
>>>>
>>>> Sorry for the inconvenience caused. The main changes compared to the
>>>> previous version by Xianwei are in the driver part.
>>>>
>>>> The dt-bindings part only has minor modifications in [PATCH 14/19].
>>>>
>>>> The driver part has relatively larger changes because it needs to be
>>>> based on the code base you previously submitted.
>>> I'm not seeing a justification for the mess introduced and I'm not
>>> looking for one to be honest
>>
>>
>> Previously, I provided a basic version of the A5 clock driver to
>> Xianwei, and he helped improve it before submitting it.
>>
>> Xianwei has been responsible for upstreaming many of our modules.
>> Since clock drivers require significant effort, I’m sharing the
>> workload by submitting some of the clock-related patches.
>>
>> The three versions previously submitted by Xianwei mainly focused on
>> improving the dt-bindings based on Rob’s feedback. The driver part
>> remained unchanged.
>>
>> The driver part in my current patch series has undergone relatively
>> large modifications to adapt to the latest code base, so comparing it
>> to the previous versions may not be very meaningful.
>>
>> If it's more appropriate for the A5 clock-related patches to continue
>> evolving based on Xianwei's earlier v3 series, please feel free to
>> point it out. I will continue to assist Xianwei in completing the
>> submission of the remaining A5 clock patches.
>>
>>
>>>>>> Both A4 and A5 belong to the Audio series. Judging by their names, one
>>>>>> might assume that A5 is an upgrade to A4, but in fact, A5 was released
>>>>>> a year earlier than A4.
>>>>>>
>>>>>> Since there are differences in the PLLs and peripheral clocks between
>>>>>> the A4 and A5 SoCs (especially the PLL), and taking into account factors
>>>>>> such as memory footprint and maintainability, this series does not
>>>>>> attempt to merge the two into a shared driver as was done for
>>>>>> G12A/G12B/SM1.
>>>>> ... and we end up with 19 patches series while it could be splitted into
>>>>> manageable series, for each controller of each SoC
>>>>
>>>> I'm not sure if I understood you correctly.
>>>>
>>>> Do you mean that I should split this series of 19 patches into multiple
>>>> patch series and send them separately? For example:
>>>> serie 1: A4 SCMI clock controller (dt-bindings)
>>>> serie 2: A4 PLL clock controller (dt-bindings, driver, dts)
>>>> serie 3: A4 peripherals clock controller (dt-bindings, driver, dts)
>>>> ... A5 similarly?
>>> Things that do not actually depends on each other or which are not
>>> merged through the same tree should not be sent together. There is
>>> nothing new here. Same basic reminders on each submission.
>>
>>
>> Sorry, but I'm still not quite sure if I understood you correctly.
>>
>> This series of 19 patches mainly falls into three major categories:
>> * Optimize PLL driver
>> * PLLs and peripherals for A4
>> * PLLs and peripherals for A5
>>
>> Are you suggesting that the PLL driver part should be sent as a
>> separate patch series, while the A4 and A5 parts should still follow
>> the previous A5/C3-style submission?
>>
>
> Please read submitting patches, soc maintainer profile and DT submitting
> patches documents. You ask us to repeat same knowledge multiple times.
> It's waste of our time, so we have documented it for your convenience.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2025-10-10 6:16 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-30 9:37 [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 01/19] dt-bindings: clock: Add Amlogic A4 SCMI clock controller Chuan Liu via B4 Relay
2025-10-09 18:07 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 02/19] dt-bindings: clock: Add Amlogic A4 PLL " Chuan Liu via B4 Relay
2025-10-09 18:04 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 03/19] dt-bindings: clock: Add Amlogic A4 peripherals " Chuan Liu via B4 Relay
2025-10-09 18:04 ` Rob Herring (Arm)
2025-09-30 9:37 ` [PATCH 04/19] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 05/19] clk: amlogic: Correct l_detect bit control Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 06/19] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 07/19] clk: amlogic: Add A4 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 08/19] clk: amlogic: Add A4 clock peripherals " Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 09/19] arm64: dts: amlogic: A4: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 10/19] arm64: dts: amlogic: A4: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 11/19] arm64: dts: amlogic: A4: Add peripherals clock " Chuan Liu via B4 Relay
2025-10-07 19:33 ` kernel test robot
2025-10-10 4:21 ` kernel test robot
2025-09-30 9:37 ` [PATCH 12/19] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 13/19] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 14/19] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2025-09-30 9:46 ` Chuan Liu
2025-09-30 9:37 ` [PATCH 15/19] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 16/19] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 17/19] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 18/19] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
2025-09-30 9:37 ` [PATCH 19/19] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
2025-09-30 14:39 ` [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Rob Herring (Arm)
2025-10-01 7:45 ` Jerome Brunet
2025-10-09 3:09 ` Chuan Liu
2025-10-09 7:59 ` Jerome Brunet
2025-10-10 2:38 ` Chuan Liu
2025-10-10 2:42 ` Krzysztof Kozlowski
2025-10-10 6:15 ` Chuan Liu
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