[PATCH RESEND 0/2] i2c: tegra: Add Tegra256 I2C controller support

[PATCH RESEND 0/2] i2c: tegra: Add Tegra256 I2C controller support

[Akhil R]

This series adds support for Tegra256 I2C controllers to the Tegra I2C driver.

Tegra256 consists of 8 generic I2C controllers similar to previous Tegra generations,
but with a different parent clock frequency requiring adjusted timing parameters.

The changes add the "nvidia,tegra256-i2c" compatible string to device tree bindings
and implement the corresponding hardware feature structure with appropriate timing
parameters and clock divisors.

Akhil R (2):
  dt-bindings: i2c: nvidia,tegra20-i2c: Add Tegra256 I2C
  i2c: tegra: Add Tegra256 support

 .../bindings/i2c/nvidia,tegra20-i2c.yaml      |  6 +++++
 drivers/i2c/busses/i2c-tegra.c                | 26 +++++++++++++++++++
 2 files changed, 32 insertions(+)

-- 
2.50.1

[PATCH RESEND 1/2] dt-bindings: i2c: nvidia,tegra20-i2c: Add Tegra256 I2C compatible

[Akhil R]

Add compatible for Tegra256 I2C controllers. Tegra256 consists of
8 generic Tegra I2C controllers similar to previous generations.
The parent clock frequency is different in these controllers and
hence the timing parameter values are different from the previous
ones.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>

---
 .../devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml         | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
index 6b6f6762d122..6f58eb79a7b3 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
@@ -80,6 +80,11 @@ properties:
           support for 64 KiB transactions whereas earlier chips supported no
           more than 4 KiB per transactions.
         const: nvidia,tegra194-i2c
+      - description: |
+          Tegra256 has 8 generic I2C controllers. The controllers are similar to
+          the previous generations, but have a different parent clock and hence
+          the timing parameters are configured differently.
+        const: nvidia,tegra256-i2c
 
   reg:
     maxItems: 1
@@ -186,6 +191,7 @@ allOf:
             contains:
               enum:
                 - nvidia,tegra194-i2c
+                - nvidia,tegra256-i2c
     then:
       required:
         - resets
-- 
2.50.1

[PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support

[Akhil R]

Add compatible and the hardware struct for Tegra256. Tegra256 controllers
use a different parent clock. Hence the timing parameters are different
from the previous generations to meet the expected frequencies.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>

---
 drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 4eb31b913c1a..e533460bccc3 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
 	.has_interface_timing_reg = true,
 };
 
+static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
+	.has_continue_xfer_support = true,
+	.has_per_pkt_xfer_complete_irq = true,
+	.clk_divisor_hs_mode = 7,
+	.clk_divisor_std_mode = 0x7a,
+	.clk_divisor_fast_mode = 0x40,
+	.clk_divisor_fast_plus_mode = 0x19,
+	.has_config_load_reg = true,
+	.has_multi_master_mode = true,
+	.has_slcg_override_reg = true,
+	.has_mst_fifo = true,
+	.has_mst_reset = true,
+	.quirks = &tegra194_i2c_quirks,
+	.supports_bus_clear = true,
+	.has_apb_dma = false,
+	.tlow_std_mode = 0x8,
+	.thigh_std_mode = 0x7,
+	.tlow_fast_fastplus_mode = 0x3,
+	.thigh_fast_fastplus_mode = 0x3,
+	.setup_hold_time_std_mode = 0x08080808,
+	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
+	.setup_hold_time_hs_mode = 0x090909,
+	.has_interface_timing_reg = true,
+};
+
 static const struct of_device_id tegra_i2c_of_match[] = {
+	{ .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
 	{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
 	{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
-- 
2.50.1

[PATCH RESEND 0/2] i2c: tegra: Add Tegra256 I2C controller support

[Akhil R]

On Mon, 18 Aug 2025 10:03:43 +0530, Akhil R wrote:

> This series adds support for Tegra256 I2C controllers to the Tegra I2C driver.
>
> Tegra256 consists of 8 generic I2C controllers similar to previous Tegra generations,
> but with a different parent clock frequency requiring adjusted timing parameters.
>
> The changes add the "nvidia,tegra256-i2c" compatible string to device tree bindings
> and implement the corresponding hardware feature structure with appropriate timing
> parameters and clock divisors.
>
> Akhil R (2):
>   dt-bindings: i2c: nvidia,tegra20-i2c: Add Tegra256 I2C
>   i2c: tegra: Add Tegra256 support
>
>  .../bindings/i2c/nvidia,tegra20-i2c.yaml      |  6 +++++
>  drivers/i2c/busses/i2c-tegra.c                | 26 +++++++++++++++++++
>  2 files changed, 32 insertions(+)

Hi Andi,

Did you get a chance to check this patchset, do you see any concerns?

Thanks & Regards,
Akhil

Re: [PATCH RESEND 0/2] i2c: tegra: Add Tegra256 I2C controller support

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1043 bytes --]

On Mon, Aug 18, 2025 at 10:03:43AM +0530, Akhil R wrote:
> This series adds support for Tegra256 I2C controllers to the Tegra I2C driver.
> 
> Tegra256 consists of 8 generic I2C controllers similar to previous Tegra generations,
> but with a different parent clock frequency requiring adjusted timing parameters.
> 
> The changes add the "nvidia,tegra256-i2c" compatible string to device tree bindings
> and implement the corresponding hardware feature structure with appropriate timing
> parameters and clock divisors.
> 
> Akhil R (2):
>   dt-bindings: i2c: nvidia,tegra20-i2c: Add Tegra256 I2C
>   i2c: tegra: Add Tegra256 support
> 
>  .../bindings/i2c/nvidia,tegra20-i2c.yaml      |  6 +++++
>  drivers/i2c/busses/i2c-tegra.c                | 26 +++++++++++++++++++
>  2 files changed, 32 insertions(+)

Hi Andi, Wolfram,

Do you want me to pick up the DT bindings patch? There's currently no DT
files that require this, so taking both through the I2C tree is fine,
but either way works for me.

Thanks,
Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH RESEND 0/2] i2c: tegra: Add Tegra256 I2C controller support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 218 bytes --]


> Do you want me to pick up the DT bindings patch? There's currently no DT
> files that require this, so taking both through the I2C tree is fine,
> but either way works for me.

Agreed, this should be I2C material.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH RESEND 1/2] dt-bindings: i2c: nvidia,tegra20-i2c: Add Tegra256 I2C compatible

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 532 bytes --]

On Mon, Aug 18, 2025 at 10:03:44AM +0530, Akhil R wrote:
> Add compatible for Tegra256 I2C controllers. Tegra256 consists of
> 8 generic Tegra I2C controllers similar to previous generations.
> The parent clock frequency is different in these controllers and
> hence the timing parameter values are different from the previous
> ones.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> Acked-by: Thierry Reding <treding@nvidia.com>
> 

Applied to for-next, thanks!


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 419 bytes --]

On Mon, Aug 18, 2025 at 10:03:45AM +0530, Akhil R wrote:
> Add compatible and the hardware struct for Tegra256. Tegra256 controllers
> use a different parent clock. Hence the timing parameters are different
> from the previous generations to meet the expected frequencies.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> 

Applied to for-next, thanks!


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support

[Jon Hunter]

Hi Akhil,

On 18/08/2025 05:33, Akhil R wrote:
> Add compatible and the hardware struct for Tegra256. Tegra256 controllers
> use a different parent clock. Hence the timing parameters are different
> from the previous generations to meet the expected frequencies.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> 
> ---
>   drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++
>   1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 4eb31b913c1a..e533460bccc3 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
>   	.has_interface_timing_reg = true,
>   };
>   
> +static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
> +	.has_continue_xfer_support = true,
> +	.has_per_pkt_xfer_complete_irq = true,
> +	.clk_divisor_hs_mode = 7,
> +	.clk_divisor_std_mode = 0x7a,
> +	.clk_divisor_fast_mode = 0x40,
> +	.clk_divisor_fast_plus_mode = 0x19,


Can you check this divisor value? I see we have been using a value of 
0x14 for this which does not align with what we have here. Can you 
confirm if this should be 0x19 or 0x14?

Thanks
Jon

-- 
nvpublic

Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support

[Akhil R]

Hi Jon,

On Tue, 7 Oct 2025 15:50:56 +0100, Jon Hunter wrote:
> On 18/08/2025 05:33, Akhil R wrote:
>> Add compatible and the hardware struct for Tegra256. Tegra256 controllers
>> use a different parent clock. Hence the timing parameters are different
>> from the previous generations to meet the expected frequencies.
>>
>> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>>
>> ---
>>   drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++
>>   1 file changed, 26 insertions(+)
>>
>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
>> index 4eb31b913c1a..e533460bccc3 100644
>> --- a/drivers/i2c/busses/i2c-tegra.c
>> +++ b/drivers/i2c/busses/i2c-tegra.c
>> @@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
>>        .has_interface_timing_reg = true,
>>   };
>>  
>> +static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>> +     .has_continue_xfer_support = true,
>> +     .has_per_pkt_xfer_complete_irq = true,
>> +     .clk_divisor_hs_mode = 7,
>> +     .clk_divisor_std_mode = 0x7a,
>> +     .clk_divisor_fast_mode = 0x40,
>> +     .clk_divisor_fast_plus_mode = 0x19,
> 
> 
> Can you check this divisor value? I see we have been using a value of
> 0x14 for this which does not align with what we have here. Can you
> confirm if this should be 0x19 or 0x14?

If you happen to notice, we are using a different tlow, thigh and hold
time values as well internally. We are also using separate variables
(tlow, thigh) for fast and fastplus modes, whereas this driver currently
uses the same variable (and value) for both fast and fastplus mode. With
that limitation, these are the closest timing values we can use now to
get the required frequency.

I am preparing the patches for the above changes and to align with the
internally used values. But I would probably wait for Kartik's patches
to conclude before sending this out, so as to reduce any conflicts.

Regards,
Akhil

Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support

[Jon Hunter]

Hi Akhil,

On 08/10/2025 06:35, Akhil R wrote:
> Hi Jon,
> 
> On Tue, 7 Oct 2025 15:50:56 +0100, Jon Hunter wrote:
>> On 18/08/2025 05:33, Akhil R wrote:
>>> Add compatible and the hardware struct for Tegra256. Tegra256 controllers
>>> use a different parent clock. Hence the timing parameters are different
>>> from the previous generations to meet the expected frequencies.
>>>
>>> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>
>>> ---
>>>    drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++
>>>    1 file changed, 26 insertions(+)
>>>
>>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
>>> index 4eb31b913c1a..e533460bccc3 100644
>>> --- a/drivers/i2c/busses/i2c-tegra.c
>>> +++ b/drivers/i2c/busses/i2c-tegra.c
>>> @@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
>>>         .has_interface_timing_reg = true,
>>>    };
>>>   
>>> +static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>>> +     .has_continue_xfer_support = true,
>>> +     .has_per_pkt_xfer_complete_irq = true,
>>> +     .clk_divisor_hs_mode = 7,
>>> +     .clk_divisor_std_mode = 0x7a,
>>> +     .clk_divisor_fast_mode = 0x40,
>>> +     .clk_divisor_fast_plus_mode = 0x19,
>>
>>
>> Can you check this divisor value? I see we have been using a value of
>> 0x14 for this which does not align with what we have here. Can you
>> confirm if this should be 0x19 or 0x14?
> 
> If you happen to notice, we are using a different tlow, thigh and hold
> time values as well internally. We are also using separate variables
> (tlow, thigh) for fast and fastplus modes, whereas this driver currently
> uses the same variable (and value) for both fast and fastplus mode. With
> that limitation, these are the closest timing values we can use now to
> get the required frequency.

Yes I did see that we have been re-working these variables and separated 
some of the variables. However, this parameter itself has not changed 
and now we have a different value in upstream. So regardless of the 
changes being planned, I don't see why we are not using the same value 
for this variable everywhere.

Jon

-- 
nvpublic

Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support

[Jon Hunter]

On 08/10/2025 10:33, Jon Hunter wrote:
> Hi Akhil,
> 
> On 08/10/2025 06:35, Akhil R wrote:
>> Hi Jon,
>>
>> On Tue, 7 Oct 2025 15:50:56 +0100, Jon Hunter wrote:
>>> On 18/08/2025 05:33, Akhil R wrote:
>>>> Add compatible and the hardware struct for Tegra256. Tegra256 
>>>> controllers
>>>> use a different parent clock. Hence the timing parameters are different
>>>> from the previous generations to meet the expected frequencies.
>>>>
>>>> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>>
>>>> ---
>>>>    drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++
>>>>    1 file changed, 26 insertions(+)
>>>>
>>>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/ 
>>>> i2c-tegra.c
>>>> index 4eb31b913c1a..e533460bccc3 100644
>>>> --- a/drivers/i2c/busses/i2c-tegra.c
>>>> +++ b/drivers/i2c/busses/i2c-tegra.c
>>>> @@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature 
>>>> tegra194_i2c_hw = {
>>>>         .has_interface_timing_reg = true,
>>>>    };
>>>> +static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>>>> +     .has_continue_xfer_support = true,
>>>> +     .has_per_pkt_xfer_complete_irq = true,
>>>> +     .clk_divisor_hs_mode = 7,
>>>> +     .clk_divisor_std_mode = 0x7a,
>>>> +     .clk_divisor_fast_mode = 0x40,
>>>> +     .clk_divisor_fast_plus_mode = 0x19,
>>>
>>>
>>> Can you check this divisor value? I see we have been using a value of
>>> 0x14 for this which does not align with what we have here. Can you
>>> confirm if this should be 0x19 or 0x14?
>>
>> If you happen to notice, we are using a different tlow, thigh and hold
>> time values as well internally. We are also using separate variables
>> (tlow, thigh) for fast and fastplus modes, whereas this driver currently
>> uses the same variable (and value) for both fast and fastplus mode. With
>> that limitation, these are the closest timing values we can use now to
>> get the required frequency.
> 
> Yes I did see that we have been re-working these variables and separated 
> some of the variables. However, this parameter itself has not changed 
> and now we have a different value in upstream. So regardless of the 
> changes being planned, I don't see why we are not using the same value 
> for this variable everywhere.

Or are you saying that this divisor value is correct per the other 
settings we have here? And when we push the other changes to separate 
the settings for fast mode and fast plus mode, we will then update this 
accordingly? If so, then that is fine.

Jon

-- 
nvpublic

Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support

[Akhil R]

On Wed, 8 Oct 2025 10:52:14 +0100, Jon Hunter wrote:
> On 08/10/2025 10:33, Jon Hunter wrote:
>> Hi Akhil,
>>
>> On 08/10/2025 06:35, Akhil R wrote:
>>> Hi Jon,
>>>
>>> On Tue, 7 Oct 2025 15:50:56 +0100, Jon Hunter wrote:
>>>> On 18/08/2025 05:33, Akhil R wrote:
>>>>> Add compatible and the hardware struct for Tegra256. Tegra256
>>>>> controllers
>>>>> use a different parent clock. Hence the timing parameters are different
>>>>> from the previous generations to meet the expected frequencies.
>>>>>
>>>>> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
>>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>>>
>>>>> ---
>>>>>    drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++
>>>>>    1 file changed, 26 insertions(+)
>>>>>
>>>>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/
>>>>> i2c-tegra.c
>>>>> index 4eb31b913c1a..e533460bccc3 100644
>>>>> --- a/drivers/i2c/busses/i2c-tegra.c
>>>>> +++ b/drivers/i2c/busses/i2c-tegra.c
>>>>> @@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature
>>>>> tegra194_i2c_hw = {
>>>>>         .has_interface_timing_reg = true,
>>>>>    };
>>>>> +static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>>>>> +     .has_continue_xfer_support = true,
>>>>> +     .has_per_pkt_xfer_complete_irq = true,
>>>>> +     .clk_divisor_hs_mode = 7,
>>>>> +     .clk_divisor_std_mode = 0x7a,
>>>>> +     .clk_divisor_fast_mode = 0x40,
>>>>> +     .clk_divisor_fast_plus_mode = 0x19,
>>>>
>>>>
>>>> Can you check this divisor value? I see we have been using a value of
>>>> 0x14 for this which does not align with what we have here. Can you
>>>> confirm if this should be 0x19 or 0x14?
>>>
>>> If you happen to notice, we are using a different tlow, thigh and hold
>>> time values as well internally. We are also using separate variables
>>> (tlow, thigh) for fast and fastplus modes, whereas this driver currently
>>> uses the same variable (and value) for both fast and fastplus mode. With
>>> that limitation, these are the closest timing values we can use now to
>>> get the required frequency.
>>
>> Yes I did see that we have been re-working these variables and separated
>> some of the variables. However, this parameter itself has not changed
>> and now we have a different value in upstream. So regardless of the
>> changes being planned, I don't see why we are not using the same value
>> for this variable everywhere.
> 
> Or are you saying that this divisor value is correct per the other
> settings we have here? And when we push the other changes to separate
> the settings for fast mode and fast plus mode, we will then update this
> accordingly? If so, then that is fine.

Correct. For this tlow/thigh etc values, we have to use 0x19 as the clock divisor
to get the required frequency.

Regards,
Akhil