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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-58b0118d22bsm6911016e87.85.2025.10.08.00.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 00:31:46 -0700 (PDT) From: Svyatoslav Ryhel To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Linus Walleij , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= , Dmitry Osipenko , Charan Pedumuru , Diogo Ivo , Aaron Kling , Arnd Bergmann Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v4 20/24] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422/YUV420p 1X16 Date: Wed, 8 Oct 2025 10:30:42 +0300 Message-ID: <20251008073046.23231-21-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251008073046.23231-1-clamor95@gmail.com> References: <20251008073046.23231-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for Bayer formats (RAW8 and RAW10) and YUV422/420p 1X16 versions of existing YUV422/YUV420p 2X8. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/staging/media/tegra-video/tegra20.c | 74 ++++++++++++++++++++- 1 file changed, 71 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c index 149386a15176..0457209b789a 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -187,6 +187,18 @@ static void tegra20_vi_get_input_formats(struct tegra_vi_channel *chan, case MEDIA_BUS_FMT_YVYU8_2X8: (*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_YVYU; break; + /* RAW8 */ + case MEDIA_BUS_FMT_SBGGR8_1X8: + case MEDIA_BUS_FMT_SGBRG8_1X8: + case MEDIA_BUS_FMT_SGRBG8_1X8: + case MEDIA_BUS_FMT_SRGGB8_1X8: + /* RAW10 */ + case MEDIA_BUS_FMT_SBGGR10_1X10: + case MEDIA_BUS_FMT_SGBRG10_1X10: + case MEDIA_BUS_FMT_SGRBG10_1X10: + case MEDIA_BUS_FMT_SRGGB10_1X10: + (*main_input_format) = VI_INPUT_INPUT_FORMAT_BAYER; + break; } } @@ -221,6 +233,18 @@ static void tegra20_vi_get_output_formats(struct tegra_vi_channel *chan, case V4L2_PIX_FMT_YVU420: (*main_output_format) = VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR; break; + /* RAW8 */ + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + /* RAW10 */ + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + (*main_output_format) = VI_OUTPUT_OUTPUT_FORMAT_VIP_BAYER_DIRECT; + break; } } @@ -308,6 +332,16 @@ static void tegra20_channel_queue_setup(struct tegra_vi_channel *chan) case V4L2_PIX_FMT_VYUY: case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_YVYU: + /* RAW8 */ + case V4L2_PIX_FMT_SRGGB8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SBGGR8: + /* RAW10 */ + case V4L2_PIX_FMT_SRGGB10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SBGGR10: if (chan->vflip) chan->start_offset += stride * (height - 1); if (chan->hflip) @@ -373,6 +407,19 @@ static void tegra20_channel_vi_buffer_setup(struct tegra_vi_channel *chan, tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(TEGRA_VI_OUT_1), base); tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(TEGRA_VI_OUT_1), base + chan->start_offset); break; + /* RAW8 */ + case V4L2_PIX_FMT_SRGGB8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SBGGR8: + /* RAW10 */ + case V4L2_PIX_FMT_SRGGB10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SBGGR10: + tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(TEGRA_VI_OUT_2), base); + tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(TEGRA_VI_OUT_2), base + chan->start_offset); + break; } } @@ -454,12 +501,15 @@ static int tegra20_chan_capture_kthread_start(void *data) static void tegra20_camera_capture_setup(struct tegra_vi_channel *chan) { u32 output_fourcc = chan->format.pixelformat; + u32 data_type = chan->fmtinfo->img_dt; int width = chan->format.width; int height = chan->format.height; int stride_l = chan->format.bytesperline; int stride_c = (output_fourcc == V4L2_PIX_FMT_YUV420 || output_fourcc == V4L2_PIX_FMT_YVU420) ? 1 : 0; - enum tegra_vi_out output_channel = TEGRA_VI_OUT_1; + enum tegra_vi_out output_channel = (data_type == TEGRA_IMAGE_DT_RAW8 || + data_type == TEGRA_IMAGE_DT_RAW10) ? + TEGRA_VI_OUT_2 : TEGRA_VI_OUT_1; int main_output_format; int yuv_output_format; @@ -586,9 +636,25 @@ static const struct tegra_video_format tegra20_video_formats[] = { TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 2, VYUY), TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 2, YUYV), TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 2, YVYU), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 2, UYVY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 2, VYUY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 2, YUYV), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 2, YVYU), /* YUV420P */ TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 1, YUV420), TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 1, YVU420), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 1, YUV420), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 1, YVU420), + /* RAW 8 */ + TEGRA20_VIDEO_FMT(RAW8, 8, SRGGB8_1X8, 2, SRGGB8), + TEGRA20_VIDEO_FMT(RAW8, 8, SGRBG8_1X8, 2, SGRBG8), + TEGRA20_VIDEO_FMT(RAW8, 8, SGBRG8_1X8, 2, SGBRG8), + TEGRA20_VIDEO_FMT(RAW8, 8, SBGGR8_1X8, 2, SBGGR8), + /* RAW 10 */ + TEGRA20_VIDEO_FMT(RAW10, 10, SRGGB10_1X10, 2, SRGGB10), + TEGRA20_VIDEO_FMT(RAW10, 10, SGRBG10_1X10, 2, SGRBG10), + TEGRA20_VIDEO_FMT(RAW10, 10, SGBRG10_1X10, 2, SGBRG10), + TEGRA20_VIDEO_FMT(RAW10, 10, SBGGR10_1X10, 2, SBGGR10), }; const struct tegra_vi_soc tegra20_vi_soc = { @@ -615,10 +681,12 @@ const struct tegra_vi_soc tegra20_vi_soc = { static int tegra20_vip_start_streaming(struct tegra_vip_channel *vip_chan) { struct tegra_vi_channel *vi_chan = v4l2_get_subdev_hostdata(&vip_chan->subdev); + u32 data_type = vi_chan->fmtinfo->img_dt; int width = vi_chan->format.width; int height = vi_chan->format.height; - enum tegra_vi_out output_channel = TEGRA_VI_OUT_1; - + enum tegra_vi_out output_channel = (data_type == TEGRA_IMAGE_DT_RAW8 || + data_type == TEGRA_IMAGE_DT_RAW10) ? + TEGRA_VI_OUT_2 : TEGRA_VI_OUT_1; unsigned int main_input_format; unsigned int yuv_input_format; -- 2.48.1