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Wed, 8 Oct 2025 03:17:41 -0700 From: Akhil R To: CC: , , , , , , , , , , , , Subject: Re: [PATCH RESEND 2/2] i2c: tegra: Add Tegra256 support Date: Wed, 8 Oct 2025 15:47:39 +0530 Message-ID: <20251008101740.63661-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7E:EE_|LV8PR12MB9111:EE_ X-MS-Office365-Filtering-Correlation-Id: 9bae0a73-889a-476e-8a2d-08de0653f31d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?K/OuA8py+y6IePDF892l4B57rGncwMnbxygfcNNSg0bEkYzCkMcxrOsRpQjF?= =?us-ascii?Q?qVEuBYYJ4M+2p5wZA04bLcdyjvfVZmMPx8xLtmcsS/xSIjleQlD2KySTt8AZ?= =?us-ascii?Q?M4lmvZbB9qYuknG8Xpe93Cd+oP6QKjG3hyTdDqbIVhXEvu4+SDggKiNeCjfs?= =?us-ascii?Q?ec59T4rZBJiyq38dly6rruYlI9GD7W9zTb7Ib44qROc4Z+mcq29m2SNyBJdB?= =?us-ascii?Q?JOMd5ccxURD2jAKlkuqu5ernat1OE9k/YL80BoJnq0t6LgqyDjr92k+UJEOP?= =?us-ascii?Q?zToUzprvA4OakwB5yAhMTTQxy3FTJkJQzdnxfEM7tCTMmBkJPo4aALNJgpZh?= =?us-ascii?Q?ivxh3K08PbafReXdg7aEeatY4kVWnHzqQXEb5ZyhTtYSf+wQAMxTA/0Y5ac6?= =?us-ascii?Q?05eRaPe3In+0QAdH6eOOOwHSNRWEornswx1skaz3rtPs8Js/dRjKbDIRKLDe?= =?us-ascii?Q?/LVjK/haDO6cgmTY3HFkxSK5HudGki0TfW4pg4CFxMMyYJkklF6rn4ITFDnY?= =?us-ascii?Q?qjTfLtIibwKw0qVn1PZMex5/arivA+zFfPNgmxUtKeZNX6LbKtW+9yVs2Z3c?= =?us-ascii?Q?hu44yB+an6bHN8xQFXPpDB01ZG1Oh/IMh7ohkKKTVZzzYEiClywor9rAWOT4?= =?us-ascii?Q?no1iI7ersj0eTYpCvr0XVjvT+F+LY3aYSAGLol5+jtbEZyxccbm9UUQsFrLZ?= =?us-ascii?Q?u/icyMId13k5sQwlsphUieVy7+VaGdabrV2DhQanbAc5jCmw7gsyF8+CCrpw?= =?us-ascii?Q?A6lCv6Z5QY9aWUfhZq8X9GOY31DgBwchFAPadM9AlibsPtqiLr1+xjRyon9r?= =?us-ascii?Q?Cs6kdO2HNbTtyv1Yhy59p1ZoW+66yPwQ8mC0I8E1mkyCMJkgtflTSFDQh0G/?= =?us-ascii?Q?n5/N3cvDeyQ4jpGlV5vDNDbz6aUZTeXFEXY3AiZ4YvhYKF3xJSYvWGskI5os?= =?us-ascii?Q?xHF15GQ+M2WJ6vq8hsvR+S26VIKzEhElhMMWgWShV8wn11StVn4kHI4LzWzK?= =?us-ascii?Q?VCh7ANrUbhk0ib67cRzERch1LbKaNETnC/5uLFnDoaIqW7rtzkOhE+AFq3/Z?= =?us-ascii?Q?jv6rGIfz1wOwTi2fvHG8LShJY8KYbbI35+R3p47ZBXaWAwgW6e0GVc+ZDUTv?= =?us-ascii?Q?GOqc7iL1eWfrd5Fv0psp3O22z5hyHCRpGqfzpA3lCZqXrawJv+QE8dPuu0fG?= =?us-ascii?Q?NJLYAnHm36OUF53dvTw8jd/CaBXOYWh6PDpwTBNWTa1qfUJkp/lj5kLhWq2V?= =?us-ascii?Q?kzrOL7gxUrM4anuHUd3ML2lea/yGJbEne12KFE/7FpIkuXVCQqPyqm+WhMXU?= =?us-ascii?Q?6XwpD250nys+YVF0qTVhF6+dIcKD79/nDmHecUydc3yGKqn6YP3dPp2DR8wa?= =?us-ascii?Q?Xb5jS75eS2dmrmGMn3xgkHCSBYjARnexZaUI1zdGMxvIU3bEsS74AErjkMlf?= =?us-ascii?Q?02obSxcvtY4RYecI2r6xDk9qFqSxkyb5Th2etfDVmevZRj2KXdK4QRXaR5kg?= =?us-ascii?Q?Lp/TMTR/F1FHDt/5m052msOG4OawXvO95mki5twqQ8J/ANr68kPDjLCzybyM?= =?us-ascii?Q?7iWA66+9GDI8d3xktOs=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2025 10:17:56.2591 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9bae0a73-889a-476e-8a2d-08de0653f31d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9111 On Wed, 8 Oct 2025 10:52:14 +0100, Jon Hunter wrote: > On 08/10/2025 10:33, Jon Hunter wrote: >> Hi Akhil, >> >> On 08/10/2025 06:35, Akhil R wrote: >>> Hi Jon, >>> >>> On Tue, 7 Oct 2025 15:50:56 +0100, Jon Hunter wrote: >>>> On 18/08/2025 05:33, Akhil R wrote: >>>>> Add compatible and the hardware struct for Tegra256. Tegra256 >>>>> controllers >>>>> use a different parent clock. Hence the timing parameters are different >>>>> from the previous generations to meet the expected frequencies. >>>>> >>>>> Signed-off-by: Akhil R >>>>> Acked-by: Thierry Reding >>>>> >>>>> --- >>>>> drivers/i2c/busses/i2c-tegra.c | 26 ++++++++++++++++++++++++++ >>>>> 1 file changed, 26 insertions(+) >>>>> >>>>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/ >>>>> i2c-tegra.c >>>>> index 4eb31b913c1a..e533460bccc3 100644 >>>>> --- a/drivers/i2c/busses/i2c-tegra.c >>>>> +++ b/drivers/i2c/busses/i2c-tegra.c >>>>> @@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature >>>>> tegra194_i2c_hw = { >>>>> .has_interface_timing_reg = true, >>>>> }; >>>>> +static const struct tegra_i2c_hw_feature tegra256_i2c_hw = { >>>>> + .has_continue_xfer_support = true, >>>>> + .has_per_pkt_xfer_complete_irq = true, >>>>> + .clk_divisor_hs_mode = 7, >>>>> + .clk_divisor_std_mode = 0x7a, >>>>> + .clk_divisor_fast_mode = 0x40, >>>>> + .clk_divisor_fast_plus_mode = 0x19, >>>> >>>> >>>> Can you check this divisor value? I see we have been using a value of >>>> 0x14 for this which does not align with what we have here. Can you >>>> confirm if this should be 0x19 or 0x14? >>> >>> If you happen to notice, we are using a different tlow, thigh and hold >>> time values as well internally. We are also using separate variables >>> (tlow, thigh) for fast and fastplus modes, whereas this driver currently >>> uses the same variable (and value) for both fast and fastplus mode. With >>> that limitation, these are the closest timing values we can use now to >>> get the required frequency. >> >> Yes I did see that we have been re-working these variables and separated >> some of the variables. However, this parameter itself has not changed >> and now we have a different value in upstream. So regardless of the >> changes being planned, I don't see why we are not using the same value >> for this variable everywhere. > > Or are you saying that this divisor value is correct per the other > settings we have here? And when we push the other changes to separate > the settings for fast mode and fast plus mode, we will then update this > accordingly? If so, then that is fine. Correct. For this tlow/thigh etc values, we have to use 0x19 as the clock divisor to get the required frequency. Regards, Akhil