[PATCH 0/3] PCI: qcom: Binding fix

[PATCH 0/3] PCI: qcom: Binding fix

[Manivannan Sadhasivam]

Hi,

This series fixes the binding issue around the PERST# and PHY properties.
The binding issue was reported in [1], while discussing a DTS fix [2].

The binding fix provided in this series is not sufficient enough to spot all the
shenanigans, especially keeping one property in Controller node and another in
Root Port node. But this series does catch the DTS issue fixed by [2]:

arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: pcie@1c00000 (qcom,pcie-sm8750): 'oneOf' conditional failed, one must be fixed:
	'phys' is a required property
	False schema does not allow [[148, 102, 1]]
	False schema does not allow [[148, 104, 0]]
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: pcie@1c00000 (qcom,pcie-sm8750): pcie@0: 'oneOf' conditional failed, one must be fixed:
	'reset-gpios' is a required property
	'wake-gpios' is a required property
	False schema does not allow [[34]]
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: pcie@1c00000 (qcom,pcie-sm8750): Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'dma-coherent', 'interconnect-names', 'interconnects', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'linux,pci-domain', 'msi-map', 'msi-map-mask', 'num-lanes', 'operating-points-v2', 'opp-table', 'pcie@0', 'perst-gpios', 'power-domains', 'ranges', 'wake-gpios' were unexpected)
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#

Thanks to Dmitry for suggesting the binding fix!

[1] https://lore.kernel.org/linux-pci/8f2e0631-6c59-4298-b36e-060708970ced@oss.qualcomm.com
[2] https://lore.kernel.org/all/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
Manivannan Sadhasivam (3):
      dt-bindings: PCI: Update the email address for Manivannan Sadhasivam
      dt-bindings: PCI: qcom: Enforce check for PHY, PERST# and WAKE# properties
      PCI: qcom: Treat PHY and PERST# as optional for the new binding

 Documentation/devicetree/bindings/pci/pci-ep.yaml  |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-common.yaml  | 22 +++++++++++++++++++++-
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml      |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sa8255p.yaml |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml  |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sc8180x.yaml |  2 +-
 .../bindings/pci/qcom,pcie-sc8280xp.yaml           |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sm8150.yaml  |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sm8250.yaml  |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sm8350.yaml  |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml  |  2 +-
 .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml  |  2 +-
 .../bindings/pci/qcom,pcie-x1e80100.yaml           |  2 +-
 .../devicetree/bindings/pci/qcom,pcie.yaml         |  2 +-
 drivers/pci/controller/dwc/pcie-qcom.c             | 11 +++++++++--
 16 files changed, 44 insertions(+), 17 deletions(-)
---
base-commit: 5472d60c129f75282d94ae5ad072ee6dfb7c7246
change-id: 20251010-pci-binding-7d4d7799c6ed

Best regards,
-- 
Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

[PATCH 1/3] dt-bindings: PCI: Update the email address for Manivannan Sadhasivam

[Manivannan Sadhasivam]

My linaro email id is no longer active. So switch to kernel.org one.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/pci/pci-ep.yaml             | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml   | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml       | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml  | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml  | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml   | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml  | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml   | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml   | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml   | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml   | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml   | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 2 +-
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml          | 2 +-
 15 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml
index 1868a10d5b10dbffcbf14b5737e51353f55b98d8..baeb583e0bcd708f219071c5b66a7e2e967299ac 100644
--- a/Documentation/devicetree/bindings/pci/pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml
@@ -11,7 +11,7 @@ description: |
 
 maintainers:
   - Kishon Vijay Abraham I <kishon@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 properties:
   $nodename:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
index ab2509ec1c4b40ac91a93033d1bab1b12c39362f..77f8faf54737e0fab089a368976290dece4f2e7d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
@@ -8,7 +8,7 @@ title: Qualcomm PCI Express Root Complex Common Properties
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 properties:
   reg:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index ac3414203d383bbd1a520dc11f317a5da9ca33e4..bed9a40b186bcf2cf93bdf354bddaa257d229f16 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm PCIe Endpoint Controller
 
 maintainers:
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
index bdddd4f499d18689db264adf71b41bb43d35cb36..1f2d098b86384014dbd61c6d0e2bd4a596f3c780 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Comp
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index 19afe2a03409b8f638e0f4a3deda304e397ab9f7..dca84580f0da00ed36e34d83bbf8aedf0c180f8b 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SA8775p PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml
index 4d0a915566030f8fbd8bf83a9ccca00fbc7574bd..4238612dd2ce6411f0ec3796682868a556724bd7 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SC7280 PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
index 34a4d7b2c8459aeb615736f54c1971014adb205f..6a7c410c9fc30f0644da19a9002e0d26813731b8 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SC8180x PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
index 15ba2385eb73c4e69d6de7dc09cf639bc800f7f2..a18cba10aceaec42e0b105f76c92a82a926d727a 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SC8280XP PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
index 26b247a41785fa3e001f7ced165747ac256f0c02..b772e7e6a9e3dda04b990e004db446159a766410 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SM8150 PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
index af4dae68d50873bf0e64d47571760b62263594cf..ecc4b971ea490b89894dfd7d334f718dec57576d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SM8250 PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
index dde3079adbb3312f46d9c0e9cee5abbd67bcab1b..6c109b30ccc61e47568fdabfff9a4e8a67946f33 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SM8350 PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
index 6e0a6d8f0ed070a98560d3e343f14e39b3cf9cd5..2725f849121b56953ccdac26ff8134dbae1a39bc 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SM8450 PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
index 38b561e23c1fda677ce2d4257e1084a384648835..f6f7e5330d59c1a20281cc8a86991c8720ceefa2 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
@@ -8,7 +8,7 @@ title: Qualcomm SM8550 PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
index 61581ffbfb2481959344490e54daea001aaa4ca3..2ebf48542911fda6fef91ea43e7b658b6cdc01e1 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
@@ -8,7 +8,7 @@ title: Qualcomm X1E80100 PCI Express Root Complex
 
 maintainers:
   - Bjorn Andersson <andersson@kernel.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description:
   Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 0e1808105a8196b450bacd6fd3d986c67e5e0082..c61930441be09d02c1b83782835061b92331560b 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex
 
 maintainers:
   - Bjorn Andersson <bjorn.andersson@linaro.org>
-  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
 
 description: |
   Qualcomm PCIe root complex controller is based on the Synopsys DesignWare

-- 
2.48.1

[PATCH 2/3] dt-bindings: PCI: qcom: Enforce check for PHY, PERST# and WAKE# properties

[Manivannan Sadhasivam]

Currently, the binding supports specifying the PHY, PERST#, WAKE#
properties in two ways:

1. Controller node (deprecated)
	- phys
	- perst-gpios
	- wake-gpios

2. Root Port node
	- phys
	- reset-gpios
	- wake-gpios

But there is no check to make sure that the both variants are not mixed.
For instance, if the Controller node specifies 'phys', 'reset-gpios',
'wake-gpios' or if the Root Port node specifies 'phys', 'perst-gpios',
'wake-gpios', then the driver will fail as reported. Hence, enforce the
check in the binding to catch these issues.

It is also possible that DTs could have 'phys' property in Controller node
and 'reset-gpios/wake-gpios' properties in the Root Port node. It will also
be a problem, but it is not possible to catch these cross-node issues in
the binding.

Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Closes: https://lore.kernel.org/linux-pci/8f2e0631-6c59-4298-b36e-060708970ced@oss.qualcomm.com
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
 .../devicetree/bindings/pci/qcom,pcie-common.yaml    | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
index 77f8faf54737e0fab089a368976290dece4f2e7d..6eaecf83d6efd37e9acb044049c1ef95611cbf58 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
@@ -111,6 +111,16 @@ patternProperties:
       phys:
         maxItems: 1
 
+    oneOf:
+      - required:
+          - phys
+          - reset-gpios
+          - wake-gpios
+      - properties:
+          phys: false
+          reset-gpios: false
+          wake-gpios: false
+
     unevaluatedProperties: false
 
 required:
@@ -129,6 +139,16 @@ anyOf:
   - required:
       - msi-map
 
+oneOf:
+  - required:
+      - phys
+      - perst-gpios
+      - wake-gpios
+  - properties:
+      phys: false
+      perst-gpios: false
+      wake-gpios: false
+
 allOf:
   - $ref: /schemas/pci/pci-host-bridge.yaml#
 

-- 
2.48.1

[PATCH 3/3] PCI: qcom: Treat PHY and PERST# as optional for the new binding

[Manivannan Sadhasivam]

Even for the new DT binding where the PHY and PERST# properties are
specified in the Root Port, both are optional. Hence, treat them as
optional in the driver too.

If both properties are not specified, then fall back to parsing the legacy
binding for backwards compatibility.

Fixes: a2fbecdbbb9d ("PCI: qcom: Add support for parsing the new Root Port binding")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 805edbbfe7eba496bc99ca82051dee43d240f359..d380981cf3ad78f549de3dc06bd2f626f8f53920 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1720,13 +1720,20 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node
 
 	reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
 				      "reset", GPIOD_OUT_HIGH, "PERST#");
-	if (IS_ERR(reset))
+	if (IS_ERR(reset) && PTR_ERR(reset) != -ENOENT)
 		return PTR_ERR(reset);
 
-	phy = devm_of_phy_get(dev, node, NULL);
+	phy = devm_of_phy_optional_get(dev, node, NULL);
 	if (IS_ERR(phy))
 		return PTR_ERR(phy);
 
+	/*
+	 * If both PHY and PERST# properties are not specified, then try the
+	 * legacy binding.
+	 */
+	if (PTR_ERR(reset) == -ENOENT && !phy)
+		return -ENOENT;
+
 	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
 	if (!port)
 		return -ENOMEM;

-- 
2.48.1

Re: [PATCH 2/3] dt-bindings: PCI: qcom: Enforce check for PHY, PERST# and WAKE# properties

[Konrad Dybcio]

On 10/10/25 8:25 PM, Manivannan Sadhasivam wrote:
> Currently, the binding supports specifying the PHY, PERST#, WAKE#
> properties in two ways:
> 
> 1. Controller node (deprecated)
> 	- phys
> 	- perst-gpios
> 	- wake-gpios
> 
> 2. Root Port node
> 	- phys
> 	- reset-gpios
> 	- wake-gpios
> 
> But there is no check to make sure that the both variants are not mixed.
> For instance, if the Controller node specifies 'phys', 'reset-gpios',
> 'wake-gpios' or if the Root Port node specifies 'phys', 'perst-gpios',
> 'wake-gpios', then the driver will fail as reported. Hence, enforce the
> check in the binding to catch these issues.
> 
> It is also possible that DTs could have 'phys' property in Controller node
> and 'reset-gpios/wake-gpios' properties in the Root Port node. It will also
> be a problem, but it is not possible to catch these cross-node issues in
> the binding.
> 
> Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Closes: https://lore.kernel.org/linux-pci/8f2e0631-6c59-4298-b36e-060708970ced@oss.qualcomm.com
> Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---

I would also like to add

Reported-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

Since he originally made me aware of this issue

Konrad

Re: [PATCH 3/3] PCI: qcom: Treat PHY and PERST# as optional for the new binding

[Konrad Dybcio]

On 10/10/25 8:25 PM, Manivannan Sadhasivam wrote:
> Even for the new DT binding where the PHY and PERST# properties are
> specified in the Root Port, both are optional. Hence, treat them as
> optional in the driver too.

I suppose this makes sense if the PHY is transparent to the OS
or otherwise pre-programmed and PERST# is hardwired or otherwise
unnecessary.. both of which I suppose aren't totally impossible..

> 
> If both properties are not specified, then fall back to parsing the legacy
> binding for backwards compatibility.
> 
> Fixes: a2fbecdbbb9d ("PCI: qcom: Add support for parsing the new Root Port binding")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 805edbbfe7eba496bc99ca82051dee43d240f359..d380981cf3ad78f549de3dc06bd2f626f8f53920 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1720,13 +1720,20 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node
>  
>  	reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
>  				      "reset", GPIOD_OUT_HIGH, "PERST#");
> -	if (IS_ERR(reset))
> +	if (IS_ERR(reset) && PTR_ERR(reset) != -ENOENT)
>  		return PTR_ERR(reset);

Please introduce an _optional variant instead

Konrad

Re: [PATCH 2/3] dt-bindings: PCI: qcom: Enforce check for PHY, PERST# and WAKE# properties

[Rob Herring (Arm)]

On Fri, 10 Oct 2025 11:25:48 -0700, Manivannan Sadhasivam wrote:
> Currently, the binding supports specifying the PHY, PERST#, WAKE#
> properties in two ways:
> 
> 1. Controller node (deprecated)
> 	- phys
> 	- perst-gpios
> 	- wake-gpios
> 
> 2. Root Port node
> 	- phys
> 	- reset-gpios
> 	- wake-gpios
> 
> But there is no check to make sure that the both variants are not mixed.
> For instance, if the Controller node specifies 'phys', 'reset-gpios',
> 'wake-gpios' or if the Root Port node specifies 'phys', 'perst-gpios',
> 'wake-gpios', then the driver will fail as reported. Hence, enforce the
> check in the binding to catch these issues.
> 
> It is also possible that DTs could have 'phys' property in Controller node
> and 'reset-gpios/wake-gpios' properties in the Root Port node. It will also
> be a problem, but it is not possible to catch these cross-node issues in
> the binding.
> 
> Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Closes: https://lore.kernel.org/linux-pci/8f2e0631-6c59-4298-b36e-060708970ced@oss.qualcomm.com
> Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/pci/qcom,pcie-common.yaml    | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.example.dtb: pcie@1c00000 (qcom,pcie-sc8180x): 'oneOf' conditional failed, one must be fixed:
	'perst-gpios' is a required property
	'wake-gpios' is a required property
	False schema does not allow [[4294967295]]
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.example.dtb: pcie@1c00000 (qcom,pcie-sc8180x): Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'dma-coherent', 'interconnect-names', 'interconnects', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'linux,pci-domain', 'num-lanes', 'phy-names', 'phys', 'power-domains', 'ranges' were unexpected)
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.example.dtb: pcie@1c08000 (qcom,pcie-sc7280): pcie@0: 'oneOf' conditional failed, one must be fixed:
	'wake-gpios' is a required property
	False schema does not allow [[4294967295]]
	False schema does not allow [[4294967295, 2, 1]]
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.example.dtb: pcie@1c08000 (qcom,pcie-sc7280): Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'dma-coherent', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'linux,pci-domain', 'num-lanes', 'pcie@0', 'power-domains', 'ranges', 'vddpe-3v3-supply' were unexpected)
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20251010-pci-binding-v1-2-947c004b5699@oss.qualcomm.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 3/3] PCI: qcom: Treat PHY and PERST# as optional for the new binding

[Manivannan Sadhasivam]

+ GPIO folks for the below API query

On Fri, Oct 10, 2025 at 08:32:51PM +0200, Konrad Dybcio wrote:
> On 10/10/25 8:25 PM, Manivannan Sadhasivam wrote:
> > Even for the new DT binding where the PHY and PERST# properties are
> > specified in the Root Port, both are optional. Hence, treat them as
> > optional in the driver too.
> 
> I suppose this makes sense if the PHY is transparent to the OS
> or otherwise pre-programmed and PERST# is hardwired or otherwise
> unnecessary.. both of which I suppose aren't totally impossible..
> 

PERST# is by definition an optional signal, but I'm not sure about why PHY is
not used by the controller driver.

> > 
> > If both properties are not specified, then fall back to parsing the legacy
> > binding for backwards compatibility.
> > 
> > Fixes: a2fbecdbbb9d ("PCI: qcom: Add support for parsing the new Root Port binding")
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++--
> >  1 file changed, 9 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 805edbbfe7eba496bc99ca82051dee43d240f359..d380981cf3ad78f549de3dc06bd2f626f8f53920 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1720,13 +1720,20 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node
> >  
> >  	reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> >  				      "reset", GPIOD_OUT_HIGH, "PERST#");
> > -	if (IS_ERR(reset))
> > +	if (IS_ERR(reset) && PTR_ERR(reset) != -ENOENT)
> >  		return PTR_ERR(reset);
> 
> Please introduce an _optional variant instead
> 

Linus, Bartosz, are you OK with devm_fwnode_gpiod_get_optional() API? Just
wanted to confirm before I go ahead as there are existing users checking for
-ENOENT explicitly. Not sure if they are doing it for a reason other than the
absence of the _optional variant or not.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 2/3] dt-bindings: PCI: qcom: Enforce check for PHY, PERST# and WAKE# properties

[Manivannan Sadhasivam]

On Fri, Oct 10, 2025 at 02:33:23PM -0500, Rob Herring (Arm) wrote:
> 
> On Fri, 10 Oct 2025 11:25:48 -0700, Manivannan Sadhasivam wrote:
> > Currently, the binding supports specifying the PHY, PERST#, WAKE#
> > properties in two ways:
> > 
> > 1. Controller node (deprecated)
> > 	- phys
> > 	- perst-gpios
> > 	- wake-gpios
> > 
> > 2. Root Port node
> > 	- phys
> > 	- reset-gpios
> > 	- wake-gpios
> > 
> > But there is no check to make sure that the both variants are not mixed.
> > For instance, if the Controller node specifies 'phys', 'reset-gpios',
> > 'wake-gpios' or if the Root Port node specifies 'phys', 'perst-gpios',
> > 'wake-gpios', then the driver will fail as reported. Hence, enforce the
> > check in the binding to catch these issues.
> > 
> > It is also possible that DTs could have 'phys' property in Controller node
> > and 'reset-gpios/wake-gpios' properties in the Root Port node. It will also
> > be a problem, but it is not possible to catch these cross-node issues in
> > the binding.
> > 
> > Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > Closes: https://lore.kernel.org/linux-pci/8f2e0631-6c59-4298-b36e-060708970ced@oss.qualcomm.com
> > Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > ---
> >  .../devicetree/bindings/pci/qcom,pcie-common.yaml    | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.example.dtb: pcie@1c00000 (qcom,pcie-sc8180x): 'oneOf' conditional failed, one must be fixed:
> 	'perst-gpios' is a required property
> 	'wake-gpios' is a required property
> 	False schema does not allow [[4294967295]]
> 	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.example.dtb: pcie@1c00000 (qcom,pcie-sc8180x): Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'dma-coherent', 'interconnect-names', 'interconnects', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'linux,pci-domain', 'num-lanes', 'phy-names', 'phys', 'power-domains', 'ranges' were unexpected)
> 	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.example.dtb: pcie@1c08000 (qcom,pcie-sc7280): pcie@0: 'oneOf' conditional failed, one must be fixed:
> 	'wake-gpios' is a required property
> 	False schema does not allow [[4294967295]]
> 	False schema does not allow [[4294967295, 2, 1]]
> 	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.example.dtb: pcie@1c08000 (qcom,pcie-sc7280): Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'dma-coherent', 'interrupt-map', 'interrupt-map-mask', 'iommu-map', 'linux,pci-domain', 'num-lanes', 'pcie@0', 'power-domains', 'ranges', 'vddpe-3v3-supply' were unexpected)
> 	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
> 

I need to add the missing properties to the example nodes in these bindings.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 3/3] PCI: qcom: Treat PHY and PERST# as optional for the new binding

[Bartosz Golaszewski]

On Sat, Oct 11, 2025 at 6:09 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> + GPIO folks for the below API query
>
> On Fri, Oct 10, 2025 at 08:32:51PM +0200, Konrad Dybcio wrote:
> > On 10/10/25 8:25 PM, Manivannan Sadhasivam wrote:
> > > Even for the new DT binding where the PHY and PERST# properties are
> > > specified in the Root Port, both are optional. Hence, treat them as
> > > optional in the driver too.
> >
> > I suppose this makes sense if the PHY is transparent to the OS
> > or otherwise pre-programmed and PERST# is hardwired or otherwise
> > unnecessary.. both of which I suppose aren't totally impossible..
> >
>
> PERST# is by definition an optional signal, but I'm not sure about why PHY is
> not used by the controller driver.
>
> > >
> > > If both properties are not specified, then fall back to parsing the legacy
> > > binding for backwards compatibility.
> > >
> > > Fixes: a2fbecdbbb9d ("PCI: qcom: Add support for parsing the new Root Port binding")
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > ---
> > >  drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++--
> > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 805edbbfe7eba496bc99ca82051dee43d240f359..d380981cf3ad78f549de3dc06bd2f626f8f53920 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -1720,13 +1720,20 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node
> > >
> > >     reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> > >                                   "reset", GPIOD_OUT_HIGH, "PERST#");
> > > -   if (IS_ERR(reset))
> > > +   if (IS_ERR(reset) && PTR_ERR(reset) != -ENOENT)
> > >             return PTR_ERR(reset);
> >
> > Please introduce an _optional variant instead
> >
>
> Linus, Bartosz, are you OK with devm_fwnode_gpiod_get_optional() API? Just
> wanted to confirm before I go ahead as there are existing users checking for
> -ENOENT explicitly. Not sure if they are doing it for a reason other than the
> absence of the _optional variant or not.
>

I'm fine as long as it follows the conventions established by other
GPIOLIB _optional interfaces.

Bart

Re: [PATCH 3/3] PCI: qcom: Treat PHY and PERST# as optional for the new binding

[Krishna Chaitanya Chundru]

On 10/11/2025 9:39 AM, Manivannan Sadhasivam wrote:
> + GPIO folks for the below API query
> 
> On Fri, Oct 10, 2025 at 08:32:51PM +0200, Konrad Dybcio wrote:
>> On 10/10/25 8:25 PM, Manivannan Sadhasivam wrote:
>>> Even for the new DT binding where the PHY and PERST# properties are
>>> specified in the Root Port, both are optional. Hence, treat them as
>>> optional in the driver too.
>>
>> I suppose this makes sense if the PHY is transparent to the OS
>> or otherwise pre-programmed and PERST# is hardwired or otherwise
>> unnecessary.. both of which I suppose aren't totally impossible..
>>
> 
> PERST# is by definition an optional signal, but I'm not sure about why PHY is
> not used by the controller driver.
> 
one case where phy is optional is in pcie tunneling through usb4, there
we don't require any phy.

- Krishna Chaitanya.
>>>
>>> If both properties are not specified, then fall back to parsing the legacy
>>> binding for backwards compatibility.
>>>
>>> Fixes: a2fbecdbbb9d ("PCI: qcom: Add support for parsing the new Root Port binding")
>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>>> ---
>>>   drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++--
>>>   1 file changed, 9 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>>> index 805edbbfe7eba496bc99ca82051dee43d240f359..d380981cf3ad78f549de3dc06bd2f626f8f53920 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>> @@ -1720,13 +1720,20 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node
>>>   
>>>   	reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
>>>   				      "reset", GPIOD_OUT_HIGH, "PERST#");
>>> -	if (IS_ERR(reset))
>>> +	if (IS_ERR(reset) && PTR_ERR(reset) != -ENOENT)
>>>   		return PTR_ERR(reset);
>>
>> Please introduce an _optional variant instead
>>
> 
> Linus, Bartosz, are you OK with devm_fwnode_gpiod_get_optional() API? Just
> wanted to confirm before I go ahead as there are existing users checking for
> -ENOENT explicitly. Not sure if they are doing it for a reason other than the
> absence of the _optional variant or not.
> 
> - Mani
> 

Re: [PATCH 1/3] dt-bindings: PCI: Update the email address for Manivannan Sadhasivam

[Rob Herring (Arm)]

On Fri, 10 Oct 2025 11:25:47 -0700, Manivannan Sadhasivam wrote:
> My linaro email id is no longer active. So switch to kernel.org one.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/pci/pci-ep.yaml             | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml   | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml       | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml  | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml  | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml   | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml  | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml   | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml   | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml   | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml   | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml   | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 2 +-
>  Documentation/devicetree/bindings/pci/qcom,pcie.yaml          | 2 +-
>  15 files changed, 15 insertions(+), 15 deletions(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: (subset) [PATCH 0/3] PCI: qcom: Binding fix

[Manivannan Sadhasivam]

On Fri, 10 Oct 2025 11:25:46 -0700, Manivannan Sadhasivam wrote:
> This series fixes the binding issue around the PERST# and PHY properties.
> The binding issue was reported in [1], while discussing a DTS fix [2].
> 
> The binding fix provided in this series is not sufficient enough to spot all the
> shenanigans, especially keeping one property in Controller node and another in
> Root Port node. But this series does catch the DTS issue fixed by [2]:
> 
> [...]

Applied, thanks!

[1/3] dt-bindings: PCI: Update the email address for Manivannan Sadhasivam
      commit: e3d7fda088c3c75d210b849c3823008f32cd00ce

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>