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Fri, 10 Oct 2025 02:29:19 -0700 From: Kartik Rajput To: , , , , , , , CC: Prathamesh Shete , Nathan Hartman , Kartik Rajput Subject: [PATCH v3 2/2] gpio: tegra186: Add support for Tegra410 Date: Fri, 10 Oct 2025 14:59:13 +0530 Message-ID: <20251010092913.711906-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251010092913.711906-1-kkartik@nvidia.com> References: <20251010092913.711906-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3F:EE_|BL3PR12MB6572:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f22b76a-fe48-49e4-d363-08de07df890e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?n4eT7J1ySMoRZaa/9WLyhZ/WX9n4MynYSEwjh3VTdgtmytffcVj5KhfvwjXb?= =?us-ascii?Q?J+//ml5rmwTsL18a73/x6oQzlRIs0rc94Nxd/n1O2i01GumOUSkmp3dANhZg?= =?us-ascii?Q?h7JdqEw19WZ8wIfZlmTmRmylxhsUg1MYQtI6fhvM9iRJxMVfzGmfFRYZ0vFS?= =?us-ascii?Q?5q9nqAyszSj5ZL9oQr4If+KncvfpogrmIMv/e8+wa7g9JCHwslZJRnpSJtSf?= =?us-ascii?Q?KT3d+0jL/O96Q3dp29Ls7LRHfq8l/1eha37WPwWb+gn7NXNA567ESSy60giE?= =?us-ascii?Q?P7H8fJF2FsDBIBAPaQINcDM419y+zLmMg9BkOFNu+z6K3u/mxnGXZqkLQMgi?= =?us-ascii?Q?hZ+G8wsxvdX/gw1qC+qFm1bSHrWV9Gc89wao2n9zpEmpGUvd0V9LPs836O9l?= =?us-ascii?Q?TX8N25ziaMcuqgN7KQhGjPz7BVLILbXlQRwsErJsrddW1ggAIsSQeP8NXtwH?= =?us-ascii?Q?Z1AH2+As4fS8uZned8eaYczPvRmZoCIoqASBTNBYbQVCZKNtPMHMxPoN9fNx?= =?us-ascii?Q?cpTq/qIigzEfYxoLIHrBG4Y7wHcG+TKWnb/hmVwheuuVsZhMws0PuGF9tdf1?= =?us-ascii?Q?GulijFBeAcPRo/jeUI0KtJ0EO96/N20KAQMZX9ZmilDfGPPTEpDk4Lcokfjp?= =?us-ascii?Q?6zgw2ZBH2WEdvhtiN1N2M7ZF74URBGd5dcOGFmKDaHsKui0TkhlATK2+/M8h?= =?us-ascii?Q?ELznLjW4yluKunlfYLFbpDKokMNYFPRMbDvgWxCyCzAqT+unq+98lp+JetJf?= =?us-ascii?Q?B7cy6KOE14d3aPYUIIjZdLz/YIqhIFFKdFcs+HtfUUzJ3hCxX+coDeWvix3M?= =?us-ascii?Q?ml2kE7jAyD/EIcQ0ydfdK6zFzMsZJfQ6GA0y9lp/4n1vFQCvwS1dkUqXNpya?= =?us-ascii?Q?O4mA1gyx/gfIFgvyQ15G6o4S26UpvsVUv18unItpp9s7yVdz0D+biWr7feNs?= =?us-ascii?Q?8RXMOM1mhPN1GYJcbkV3yS7h6ofq37p4a0dgjaICtxmb2bribaHTM5u0fF5Z?= =?us-ascii?Q?ZrhVjng4gTGto5kwf/xlSY49VSrYbGr3E5YTNGgoX865oCXxl/of8QqpGlJP?= =?us-ascii?Q?/241JhfjzEaCKrz6VfEmUM1TIw+/Ukl4SkRcJPm9ygxCgsyZmH51+UuSmuVY?= =?us-ascii?Q?USwjtmsYNZBP7WwhTih1J1qBezGZ57a7n1incUe/QzcWwGu9Q561qo/fjdxa?= =?us-ascii?Q?ILQxFxkyKLx+DkZoA2izAMDZQ/s4wrhn8wLnhexj1pLWAhrEgWyrRd753AHg?= =?us-ascii?Q?wfj8OqRXRjgXQBUc2hJvn/bvfPwOKernss+c3OWY2fMnDcJtxVUsN2AIvYfx?= =?us-ascii?Q?Oh5Ou2XSdvapnhuDq5OpewL0OZeVadP84XD9xZXoliNam2ThW5SViFs5XfrG?= =?us-ascii?Q?3yO4SBOvGo90PJpUEmV/WmtQFbf/2wj+BRfAFCG3wTVSEuWbzJTD8vbH0Ia4?= =?us-ascii?Q?sPiyoiE9pzeOVBS/aTW6lMNR78QOLLn0A1H3vKzXfdCSZuGHVagemszvNA59?= =?us-ascii?Q?8qeLWpB/SSNQ/8a/obcvdk9l7gLDqt8A1agV/cU3Wx70H5Tvr2T57fOxPGmD?= =?us-ascii?Q?Turrm9yEqmUiU++0a08=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 09:29:39.0246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f22b76a-fe48-49e4-d363-08de07df890e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6572 From: Prathamesh Shete Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra410. Tegra410 supports two GPIO controllers referred to as 'COMPUTE' and 'SYSTEM'. Co-developed-by: Nathan Hartman Signed-off-by: Nathan Hartman Signed-off-by: Prathamesh Shete Signed-off-by: Kartik Rajput --- v2 -> v3: * Add a generic TEGRA_GPIO_PORT macro and use it to define TEGRA410_COMPUTE_GPIO_PORT and TEGRA410_SYSTEM_GPIO_PORT. v1 -> v2: * Move Tegra410 GPIO Ports definition to gpio-tegra186.c * Rename Tegra410 Main GPIO as System GPIO. * Add Compute GPIOs. * Update ACPI IDs. * Set instance ID as 0 for SYSTEM and COMPUTE GPIOs. * Added Nathan as co-author for adding compute GPIO support and renaming MAIN GPIOs as SYSTEM GPIOs. --- drivers/gpio/gpio-tegra186.c | 82 +++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 7ea541d6d537..c6ebe29f9cf1 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2022 NVIDIA Corporation + * Copyright (c) 2016-2025 NVIDIA Corporation * * Author: Thierry Reding * Dipen Patel @@ -69,6 +69,36 @@ #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) +/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */ +#define TEGRA410_COMPUTE_GPIO_PORT_A 0 +#define TEGRA410_COMPUTE_GPIO_PORT_B 1 +#define TEGRA410_COMPUTE_GPIO_PORT_C 2 +#define TEGRA410_COMPUTE_GPIO_PORT_D 3 +#define TEGRA410_COMPUTE_GPIO_PORT_E 4 + +#define TEGRA410_COMPUTE_GPIO(port, offset) \ + ((TEGRA410_COMPUTE_GPIO_PORT_##port * 8) + (offset)) + +/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */ +#define TEGRA410_SYSTEM_GPIO_PORT_A 0 +#define TEGRA410_SYSTEM_GPIO_PORT_B 1 +#define TEGRA410_SYSTEM_GPIO_PORT_C 2 +#define TEGRA410_SYSTEM_GPIO_PORT_D 3 +#define TEGRA410_SYSTEM_GPIO_PORT_E 4 +#define TEGRA410_SYSTEM_GPIO_PORT_I 5 +#define TEGRA410_SYSTEM_GPIO_PORT_J 6 +#define TEGRA410_SYSTEM_GPIO_PORT_K 7 +#define TEGRA410_SYSTEM_GPIO_PORT_L 8 +#define TEGRA410_SYSTEM_GPIO_PORT_M 9 +#define TEGRA410_SYSTEM_GPIO_PORT_N 10 +#define TEGRA410_SYSTEM_GPIO_PORT_P 11 +#define TEGRA410_SYSTEM_GPIO_PORT_Q 12 +#define TEGRA410_SYSTEM_GPIO_PORT_R 13 +#define TEGRA410_SYSTEM_GPIO_PORT_V 14 + +#define TEGRA410_SYSTEM_GPIO(port, offset) \ + ((TEGRA410_SYSTEM_GPIO_PORT_##port * 8) + (offset)) + struct tegra_gpio_port { const char *name; unsigned int bank; @@ -1267,6 +1297,54 @@ static const struct tegra_gpio_soc tegra256_main_soc = { .has_vm_support = true, }; +#define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins) \ + TEGRA_GPIO_PORT(TEGRA410_COMPUTE, _name, _bank, _port, _pins) + +static const struct tegra_gpio_port tegra410_compute_ports[] = { + TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3), + TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8), + TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3), + TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8), + TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8), +}; + +static const struct tegra_gpio_soc tegra410_compute_soc = { + .num_ports = ARRAY_SIZE(tegra410_compute_ports), + .ports = tegra410_compute_ports, + .name = "tegra410-gpio-compute", + .num_irqs_per_bank = 8, + .instance = 0, +}; + +#define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins) \ + TEGRA_GPIO_PORT(TEGRA410_SYSTEM, _name, _bank, _port, _pins) + +static const struct tegra_gpio_port tegra410_system_ports[] = { + TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7), + TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8), + TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8), + TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8), + TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6), + TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8), + TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7), + TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7), + TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7), + TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7), + TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6), + TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8), + TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3), + TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2), + TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2), +}; + +static const struct tegra_gpio_soc tegra410_system_soc = { + .num_ports = ARRAY_SIZE(tegra410_system_ports), + .ports = tegra410_system_ports, + .name = "tegra410-gpio-system", + .num_irqs_per_bank = 8, + .instance = 0, +}; + static const struct of_device_id tegra186_gpio_of_match[] = { { .compatible = "nvidia,tegra186-gpio", @@ -1302,6 +1380,8 @@ static const struct acpi_device_id tegra186_gpio_acpi_match[] = { { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, + { .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc }, + { .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc }, {} }; MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); -- 2.43.0