* [PATCH v2 0/2] ARM: dts: aspeed: ASRock Rack X470D4U BMC support @ 2025-10-11 11:21 Tan Siewert 2025-10-11 11:21 ` [PATCH v2 1/2] dt-bindings: arm: aspeed: add ASRock X470D4U BMC Tan Siewert 2025-10-11 11:21 ` [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc Tan Siewert 0 siblings, 2 replies; 8+ messages in thread From: Tan Siewert @ 2025-10-11 11:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: Tan Siewert, Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel Hi, This series adds support for the BMC of the ASRock Rack X470D4U mainboard, which uses an ASPEED AST2500. The mainboard exists in three known flavors, the "normal" X470D4U, the X470D4U2-2T (with 2x10G RJ45) and the X470D4U2/1N1 (an ODM version with 2x1G RJ45 that is now available in retail). The 1N1 version also has a 64MB BMC SPI by default, but they are all swappable. All flavors will use the 32MB flash layout which should prevent unnecessary complexity of the device tree. Please note that this board has been fully reverse-engineered. Thanks, Tan v2: - fix led node names [robh] - fix missing gfx memory region and other fixable dtbs_check issues [Tan] Tan Siewert (2): dt-bindings: arm: aspeed: add ASRock X470D4U BMC ARM: dts: aspeed: add asrock x470d4u bmc .../bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-asrock-x470d4u.dts | 350 ++++++++++++++++++ 3 files changed, 352 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts -- 2.50.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/2] dt-bindings: arm: aspeed: add ASRock X470D4U BMC 2025-10-11 11:21 [PATCH v2 0/2] ARM: dts: aspeed: ASRock Rack X470D4U BMC support Tan Siewert @ 2025-10-11 11:21 ` Tan Siewert 2025-10-12 3:03 ` Krzysztof Kozlowski 2025-10-11 11:21 ` [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc Tan Siewert 1 sibling, 1 reply; 8+ messages in thread From: Tan Siewert @ 2025-10-11 11:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: Tan Siewert, Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel Document ASRock's X470D4U BMC board compatible. Signed-off-by: Tan Siewert <tan@siewert.io> --- v2: No changes --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index aedefca7cf4a..02ac7c4d92e9 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -38,6 +38,7 @@ properties: - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc - asrock,spc621d8hm3-bmc + - asrock,x470d4u-bmc - asrock,x570d4u-bmc - bytedance,g220a-bmc - facebook,cmm-bmc -- 2.50.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: arm: aspeed: add ASRock X470D4U BMC 2025-10-11 11:21 ` [PATCH v2 1/2] dt-bindings: arm: aspeed: add ASRock X470D4U BMC Tan Siewert @ 2025-10-12 3:03 ` Krzysztof Kozlowski 0 siblings, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-10-12 3:03 UTC (permalink / raw) To: Tan Siewert, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 11/10/2025 13:21, Tan Siewert wrote: > Document ASRock's X470D4U BMC board compatible. > > Signed-off-by: Tan Siewert <tan@siewert.io> > --- > v2: No changes Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> <form letter> This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, just skip it entirely (please do not feel offended by me posting it here - no bad intentions intended, no patronizing, I just want to avoid wasted efforts). If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions of patchset, under or above your Signed-off-by tag, unless patch changed significantly (e.g. new properties added to the DT bindings). Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here ('b4 trailers -u ...'). However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply. Full context and explanation: https://elixir.bootlin.com/linux/v6.15/source/Documentation/process/submitting-patches.rst#L591 </form letter> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc 2025-10-11 11:21 [PATCH v2 0/2] ARM: dts: aspeed: ASRock Rack X470D4U BMC support Tan Siewert 2025-10-11 11:21 ` [PATCH v2 1/2] dt-bindings: arm: aspeed: add ASRock X470D4U BMC Tan Siewert @ 2025-10-11 11:21 ` Tan Siewert 2025-10-17 5:42 ` Andrew Jeffery 2025-10-20 9:40 ` Zev Weiss 1 sibling, 2 replies; 8+ messages in thread From: Tan Siewert @ 2025-10-11 11:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: Tan Siewert, Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX motherboard for Ryzen processors with an AST2500 BMC and either 32MB or 64MB SPI flash. This mainboard exists in three known "flavors" which only differ in the used host NIC, the BMC SPI size and some parts that may be un-populated. To keep the complexity low with the BMC SPI, use the 32MB layout regardless of the used SPI or mainboard flavor. Signed-off-by: Tan Siewert <tan@siewert.io> --- v2: - fix led node names [robh] - fix missing gfx memory region and other offenses [Tan] --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-asrock-x470d4u.dts | 350 ++++++++++++++++++ 2 files changed, 351 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 0f0b5b707654..c601af36915e 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-asrock-e3c256d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ aspeed-bmc-asrock-spc621d8hm3.dtb \ + aspeed-bmc-asrock-x470d4u.dtb \ aspeed-bmc-asrock-x570d4u.dtb \ aspeed-bmc-asus-x4tf.dtb \ aspeed-bmc-bytedance-g220a.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts new file mode 100644 index 000000000000..e9804b0ace9f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Asrock Rack X470D4U-series BMC"; + compatible = "asrock,x470d4u-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, + <&adc 10>, <&adc 11>, <&adc 12>; + }; + + leds { + compatible = "gpio-leds"; + + led-heartbeat { + /* led-heartbeat-n */ + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "timer"; + }; + + led-systemfault { + /* led-fault-n */ + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_FAULT; + panic-indicator; + }; + + led-identify { + /* led-identify-n */ + gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pci_memory: region@9a000000 { + no-map; + reg = <0x9a000000 0x00010000>; /* 64K */ + }; + + video_engine_memory: jpegbuffer { + size = <0x02800000>; /* 40M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default /* 3VSB */ + &pinctrl_adc1_default /* 5VSB */ + &pinctrl_adc2_default /* VCPU */ + &pinctrl_adc3_default /* VSOC */ + &pinctrl_adc4_default /* VCCM */ + &pinctrl_adc5_default /* APU-VDDP */ + &pinctrl_adc6_default /* 1V05-PROM-S5 */ + &pinctrl_adc7_default /* 2V5-PROM */ + &pinctrl_adc8_default /* 1V05-PROM-RUN */ + &pinctrl_adc9_default /* VBAT */ + &pinctrl_adc10_default /* 3V */ + &pinctrl_adc11_default /* 5V */ + &pinctrl_adc12_default>; /* 12V */ +}; + +&ehci1 { + status = "okay"; +}; + +/* + * Although some board flavors have a 64MB SPI, use the + * 32MB SPI layout to be compatible with all boards. + */ +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <10000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "input-locatorled-n", "", "", "", "", "", "", "", + /* B */ "input-bios-post-cmplt-n", "", "", "", "", "", "", "", + /* C */ "", "", "", "", "", "", "", "", + /* D */ "button-power-n", "control-power-n", "button-reset-n", + "control-reset-n", "", "", "", "", + /* E */ "", "", "", "", "", "", "", "", + /* F */ "", "", "", "", "", "", "", "", + /* G */ "output-hwm-vbat-enable", "input-id0-n", "input-id1-n", + "input-id2-n", "input-aux-smb-alert-n", "", + "input-psu-smb-alert-n", "", + /* H */ "", "", "", "", "input-mfg-mode-n", "", + "led-heartbeat-n", "input-case-open-n", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "output-bmc-ready-n", "output-bios-cs-n", "", "", "", "", + "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "", "", "", "", "", "", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "", "", "", "", "", "", "", "", + /* Q */ "", "", "", "", "input-bmc-smb-present-n", "", "", + "input-pcie-wake-n", + /* R */ "", "", "", "", "", "", "", "", + /* S */ "input-bmc-pchhot-n", "", "", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "input-sleep-s3-n", "input-sleep-s5-n", "", "", "", "", + "", "", + /* Z */ "", "", "led-fault-n", "output-bmc-throttle-n", "", "", + "", "", + /* AA */ "input-cpu1-thermtrip-latch-n", "", + "input-cpu1-prochot-n", "", "", "", "", "", + /* AB */ "", "input-power-good", "", "hard-power-off", "", "", "", "", + /* AC */ "", "", "", "", "", "", "", ""; +}; + +&i2c0 { + /* SMBus on auxiliary panel header (AUX_PANEL1) */ + status = "okay"; +}; + +&i2c1 { + /* Hardware monitoring SMBus */ + status = "okay"; + + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c2 { + /* PSU SMBus (PSU_SMB1) */ + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c6 { + /* SMBus on BMC connector (BMC_SMB_1) */ + status = "okay"; +}; + +&i2c7 { + /* FRU EEPROM */ + status = "okay"; + + eeprom@57 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x57>; + pagesize = <16>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; + + eth1_macaddress: macaddress@3f88 { + reg = <0x3f88 6>; + }; + }; + }; +}; + +&i2c8 { + /* SMBus on intelligent platform management bus header (IPMB_1) */ + status = "okay"; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; + + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii2_default &pinctrl_mdio2_default>; + use-ncsi; + + nvmem-cells = <ð1_macaddress>; + nvmem-cell-names = "mac-address"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default>; + + fan@0 { + /* FAN1 (4-pin) */ + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + /* FAN2 (4-pin) */ + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + /* FAN3 (4-pin) */ + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + /* FAN4 (6-pin) */ + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; + }; + + fan@4 { + /* FAN5 (6-pin) */ + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0d>; + }; + + fan@5 { + /* FAN6 (6-pin) */ + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0e>; + }; +}; + +&p2a { + status = "okay"; + memory-region = <&pci_memory>; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + label = "bios"; + m25p,fast-read; + /* Frequency extracted from original ROM */ + spi-max-frequency = <24000000>; /* 24 MHz */ + }; +}; + +&uhci { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x2f8>; + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart5 { + status = "okay"; +}; -- 2.50.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc 2025-10-11 11:21 ` [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc Tan Siewert @ 2025-10-17 5:42 ` Andrew Jeffery 2025-10-17 19:49 ` Tan Siewert 2025-10-20 9:40 ` Zev Weiss 1 sibling, 1 reply; 8+ messages in thread From: Andrew Jeffery @ 2025-10-17 5:42 UTC (permalink / raw) To: Tan Siewert, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley Cc: Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On Sat, 2025-10-11 at 13:21 +0200, Tan Siewert wrote: > The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX > motherboard for Ryzen processors with an AST2500 BMC and either 32MB or > 64MB SPI flash. > > This mainboard exists in three known "flavors" which only differ in the > used host NIC, the BMC SPI size and some parts that may be un-populated. > > To keep the complexity low with the BMC SPI, use the 32MB layout > regardless of the used SPI or mainboard flavor. > > Signed-off-by: Tan Siewert <tan@siewert.io> > --- > v2: > - fix led node names [robh] > - fix missing gfx memory region and other offenses [Tan] > --- > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../dts/aspeed/aspeed-bmc-asrock-x470d4u.dts | 350 ++++++++++++++++++ > 2 files changed, 351 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts > > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile > index 0f0b5b707654..c601af36915e 100644 > --- a/arch/arm/boot/dts/aspeed/Makefile > +++ b/arch/arm/boot/dts/aspeed/Makefile > @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ > aspeed-bmc-asrock-e3c256d4i.dtb \ > aspeed-bmc-asrock-romed8hm3.dtb \ > aspeed-bmc-asrock-spc621d8hm3.dtb \ > + aspeed-bmc-asrock-x470d4u.dtb \ > aspeed-bmc-asrock-x570d4u.dtb \ > aspeed-bmc-asus-x4tf.dtb \ > aspeed-bmc-bytedance-g220a.dtb \ > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts > new file mode 100644 > index 000000000000..e9804b0ace9f > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts > @@ -0,0 +1,350 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/dts-v1/; > + > +#include "aspeed-g5.dtsi" > +#include <dt-bindings/gpio/aspeed-gpio.h> > +#include <dt-bindings/leds/common.h> > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + model = "Asrock Rack X470D4U-series BMC"; > + compatible = "asrock,x470d4u-bmc", "aspeed,ast2500"; > + > + aliases { > + serial4 = &uart5; > + }; > + > + chosen { > + stdout-path = &uart5; > + }; > > *snip* > nvmem-cell-names = "mac-address"; > +}; > + > +&mac1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rmii2_default &pinctrl_mdio2_default>; If you're using NCSI you don't need the MDIO pins here, right? > + use-ncsi; > + > + nvmem-cells = <ð1_macaddress>; > + nvmem-cell-names = "mac-address"; > +}; > + Andrew ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc 2025-10-17 5:42 ` Andrew Jeffery @ 2025-10-17 19:49 ` Tan Siewert 0 siblings, 0 replies; 8+ messages in thread From: Tan Siewert @ 2025-10-17 19:49 UTC (permalink / raw) To: Andrew Jeffery, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley Cc: Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 17.10.25 07:42, Andrew Jeffery wrote: > On Sat, 2025-10-11 at 13:21 +0200, Tan Siewert wrote: >> The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX >> motherboard for Ryzen processors with an AST2500 BMC and either 32MB or >> 64MB SPI flash. >> >> This mainboard exists in three known "flavors" which only differ in the >> used host NIC, the BMC SPI size and some parts that may be un-populated. >> >> To keep the complexity low with the BMC SPI, use the 32MB layout >> regardless of the used SPI or mainboard flavor. >> >> Signed-off-by: Tan Siewert <tan@siewert.io> >> --- >> v2: >> - fix led node names [robh] >> - fix missing gfx memory region and other offenses [Tan] >> --- >> arch/arm/boot/dts/aspeed/Makefile | 1 + >> .../dts/aspeed/aspeed-bmc-asrock-x470d4u.dts | 350 ++++++++++++++++++ >> 2 files changed, 351 insertions(+) >> create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts >> >> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile >> index 0f0b5b707654..c601af36915e 100644 >> --- a/arch/arm/boot/dts/aspeed/Makefile >> +++ b/arch/arm/boot/dts/aspeed/Makefile >> @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ >> aspeed-bmc-asrock-e3c256d4i.dtb \ >> aspeed-bmc-asrock-romed8hm3.dtb \ >> aspeed-bmc-asrock-spc621d8hm3.dtb \ >> + aspeed-bmc-asrock-x470d4u.dtb \ >> aspeed-bmc-asrock-x570d4u.dtb \ >> aspeed-bmc-asus-x4tf.dtb \ >> aspeed-bmc-bytedance-g220a.dtb \ >> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts >> new file mode 100644 >> index 000000000000..e9804b0ace9f >> --- /dev/null >> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts >> @@ -0,0 +1,350 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/dts-v1/; >> + >> +#include "aspeed-g5.dtsi" >> +#include <dt-bindings/gpio/aspeed-gpio.h> >> +#include <dt-bindings/leds/common.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> + >> +/ { >> + model = "Asrock Rack X470D4U-series BMC"; >> + compatible = "asrock,x470d4u-bmc", "aspeed,ast2500"; >> + >> + aliases { >> + serial4 = &uart5; >> + }; >> + >> + chosen { >> + stdout-path = &uart5; >> + }; >> >> > > *snip* > >> nvmem-cell-names = "mac-address"; >> +}; >> + >> +&mac1 { >> + status = "okay"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_rmii2_default &pinctrl_mdio2_default>; > > If you're using NCSI you don't need the MDIO pins here, right? Right. Will be addressed with v3. Thanks! Tan > >> + use-ncsi; >> + >> + nvmem-cells = <ð1_macaddress>; >> + nvmem-cell-names = "mac-address"; >> +}; >> + > > Andrew ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc 2025-10-11 11:21 ` [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc Tan Siewert 2025-10-17 5:42 ` Andrew Jeffery @ 2025-10-20 9:40 ` Zev Weiss 2025-10-24 20:23 ` Tan Siewert 1 sibling, 1 reply; 8+ messages in thread From: Zev Weiss @ 2025-10-20 9:40 UTC (permalink / raw) To: Tan Siewert Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On Sat, Oct 11, 2025 at 04:21:20AM PDT, Tan Siewert wrote: >The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX >motherboard for Ryzen processors with an AST2500 BMC and either 32MB or >64MB SPI flash. > >This mainboard exists in three known "flavors" which only differ in the >used host NIC, the BMC SPI size and some parts that may be un-populated. > >To keep the complexity low with the BMC SPI, use the 32MB layout >regardless of the used SPI or mainboard flavor. > >Signed-off-by: Tan Siewert <tan@siewert.io> >--- >v2: > - fix led node names [robh] > - fix missing gfx memory region and other offenses [Tan] >--- > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../dts/aspeed/aspeed-bmc-asrock-x470d4u.dts | 350 ++++++++++++++++++ > 2 files changed, 351 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts > >diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile >index 0f0b5b707654..c601af36915e 100644 >--- a/arch/arm/boot/dts/aspeed/Makefile >+++ b/arch/arm/boot/dts/aspeed/Makefile >@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ > aspeed-bmc-asrock-e3c256d4i.dtb \ > aspeed-bmc-asrock-romed8hm3.dtb \ > aspeed-bmc-asrock-spc621d8hm3.dtb \ >+ aspeed-bmc-asrock-x470d4u.dtb \ > aspeed-bmc-asrock-x570d4u.dtb \ > aspeed-bmc-asus-x4tf.dtb \ > aspeed-bmc-bytedance-g220a.dtb \ >diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts >new file mode 100644 >index 000000000000..e9804b0ace9f >--- /dev/null >+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts >@@ -0,0 +1,350 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/dts-v1/; >+ >+#include "aspeed-g5.dtsi" >+#include <dt-bindings/gpio/aspeed-gpio.h> >+#include <dt-bindings/leds/common.h> >+#include <dt-bindings/interrupt-controller/irq.h> >+ >+/ { >+ model = "Asrock Rack X470D4U-series BMC"; >+ compatible = "asrock,x470d4u-bmc", "aspeed,ast2500"; >+ >+ aliases { >+ serial4 = &uart5; >+ }; >+ >+ chosen { >+ stdout-path = &uart5; >+ }; >+ >+ iio-hwmon { >+ compatible = "iio-hwmon"; >+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, >+ <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, >+ <&adc 10>, <&adc 11>, <&adc 12>; >+ }; >+ >+ leds { >+ compatible = "gpio-leds"; >+ >+ led-heartbeat { >+ /* led-heartbeat-n */ >+ gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; >+ color = <LED_COLOR_ID_GREEN>; >+ function = LED_FUNCTION_HEARTBEAT; >+ linux,default-trigger = "timer"; >+ }; >+ >+ led-systemfault { >+ /* led-fault-n */ >+ gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; >+ color = <LED_COLOR_ID_AMBER>; >+ function = LED_FUNCTION_FAULT; >+ panic-indicator; >+ }; >+ >+ led-identify { >+ /* led-identify-n */ >+ gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>; >+ }; >+ }; >+ >+ memory@80000000 { >+ reg = <0x80000000 0x20000000>; >+ }; >+ >+ reserved-memory { >+ #address-cells = <1>; >+ #size-cells = <1>; >+ ranges; >+ >+ pci_memory: region@9a000000 { >+ no-map; >+ reg = <0x9a000000 0x00010000>; /* 64K */ >+ }; >+ >+ video_engine_memory: jpegbuffer { >+ size = <0x02800000>; /* 40M */ >+ alignment = <0x01000000>; >+ compatible = "shared-dma-pool"; >+ reusable; >+ }; >+ >+ gfx_memory: framebuffer { >+ size = <0x01000000>; >+ alignment = <0x01000000>; >+ compatible = "shared-dma-pool"; >+ reusable; >+ }; >+ }; >+}; >+ >+&adc { >+ status = "okay"; >+ pinctrl-names = "default"; >+ pinctrl-0 = <&pinctrl_adc0_default /* 3VSB */ >+ &pinctrl_adc1_default /* 5VSB */ >+ &pinctrl_adc2_default /* VCPU */ >+ &pinctrl_adc3_default /* VSOC */ >+ &pinctrl_adc4_default /* VCCM */ >+ &pinctrl_adc5_default /* APU-VDDP */ >+ &pinctrl_adc6_default /* 1V05-PROM-S5 */ >+ &pinctrl_adc7_default /* 2V5-PROM */ >+ &pinctrl_adc8_default /* 1V05-PROM-RUN */ >+ &pinctrl_adc9_default /* VBAT */ >+ &pinctrl_adc10_default /* 3V */ >+ &pinctrl_adc11_default /* 5V */ >+ &pinctrl_adc12_default>; /* 12V */ >+}; >+ >+&ehci1 { >+ status = "okay"; >+}; >+ >+/* >+ * Although some board flavors have a 64MB SPI, use the >+ * 32MB SPI layout to be compatible with all boards. >+ */ >+&fmc { >+ status = "okay"; >+ flash@0 { >+ status = "okay"; >+ label = "bmc"; >+ m25p,fast-read; >+ spi-max-frequency = <10000000>; >+#include "openbmc-flash-layout.dtsi" >+ }; >+}; Hmm -- I can see the simplicity argument, but it seems a bit of a shame to let the other 32MB go to waste on boards with 64MB chips (especially given how tight a fit OpenBMC is getting in 32MB these days). Could we maybe have an aspeed-bmc-asrock-x470d4u-64.dts alongside this one that #includes it and then drops in the 64M layout over the default 32? You could then arrange for a flag in the OpenBMC bitbake recipes to opt in to using that dts if you want to. Zev ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc 2025-10-20 9:40 ` Zev Weiss @ 2025-10-24 20:23 ` Tan Siewert 0 siblings, 0 replies; 8+ messages in thread From: Tan Siewert @ 2025-10-24 20:23 UTC (permalink / raw) To: Zev Weiss Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 20.10.25 11:40, Zev Weiss wrote: > On Sat, Oct 11, 2025 at 04:21:20AM PDT, Tan Siewert wrote: >> The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX >> motherboard for Ryzen processors with an AST2500 BMC and either 32MB or >> 64MB SPI flash. >> >> This mainboard exists in three known "flavors" which only differ in the >> used host NIC, the BMC SPI size and some parts that may be un-populated. >> >> To keep the complexity low with the BMC SPI, use the 32MB layout >> regardless of the used SPI or mainboard flavor. *snip* > Hmm -- I can see the simplicity argument, but it seems a bit of a shame > to let the other 32MB go to waste on boards with 64MB chips (especially > given how tight a fit OpenBMC is getting in 32MB these days). Agreed. > Could we maybe have an aspeed-bmc-asrock-x470d4u-64.dts alongside this > one that #includes it and then drops in the 64M layout over the default > 32? You could then arrange for a flag in the OpenBMC bitbake recipes to > opt in to using that dts if you want to. I implemented this idea in one of my first drafts [1], but there were questions on the OpenBMC Discord if the additional 32MB of space are really needed, given that the 64MB SPI is only available on an ODM variant by default. [1] https://gerrit.openbmc.org/c/openbmc/openbmc/+/82262/4 Cheers, Tan > > > Zev > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-10-24 20:23 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-11 11:21 [PATCH v2 0/2] ARM: dts: aspeed: ASRock Rack X470D4U BMC support Tan Siewert 2025-10-11 11:21 ` [PATCH v2 1/2] dt-bindings: arm: aspeed: add ASRock X470D4U BMC Tan Siewert 2025-10-12 3:03 ` Krzysztof Kozlowski 2025-10-11 11:21 ` [PATCH v2 2/2] ARM: dts: aspeed: add asrock x470d4u bmc Tan Siewert 2025-10-17 5:42 ` Andrew Jeffery 2025-10-17 19:49 ` Tan Siewert 2025-10-20 9:40 ` Zev Weiss 2025-10-24 20:23 ` Tan Siewert
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