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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1760202252; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xPiyri8B7k2bct+4e5c5xnBcOdZcRZjBPgHNHY8UKtw=; b=fpp2uCXHh9XD4JyA5nrRXLCt89JMZD68UW2GptC0MJOAZzUetKaPCyrUniPt6MAQkkeRzF nOP85GjwcWMHFAYxLsSlhe2rrwCwC+KDSsj8hWpP/AGPxqwVhNmo/KCBRYqPcA2UaPRBd4 WEj8An3sdIo22BNhCfL6oe54ng0C0cPNpY/MeWMQseG/NrRtZ+Xqc1nWD5FzxYsg1EU0Hi ko7Gw/vc9o5DaoYkWaPwfW/K8Wzl+Cohn9cVSplZiIvwuGQ+aQy6C/CPxv3exPlM7TXgJp 9MEg+Xsxap9B/jZcP28e4M4SfCf1a0T0gsaC67G7lpipBzv2pXL4EW1rMKgOcQ== To: dri-devel@lists.freedesktop.org Cc: Marek Vasut , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Laurent Pinchart , Liu Ying , Lucas Stach , Peng Fan , Pengutronix Kernel Team , Rob Herring , Shawn Guo , Thomas Zimmermann , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 29/39] dt-bindings: display: bridge: Document Freescale i.MX95 MIPI DSI Date: Sat, 11 Oct 2025 18:51:44 +0200 Message-ID: <20251011170213.128907-30-marek.vasut@mailbox.org> In-Reply-To: <20251011170213.128907-1-marek.vasut@mailbox.org> References: <20251011170213.128907-1-marek.vasut@mailbox.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-MBO-RS-META: 85zz6hyigpakz4rsiia6ykwknitchfqo X-MBO-RS-ID: a8076b6bb914c6c52ba X-Rspamd-Queue-Id: 4ckVML5Ssxz9tH5 Freescale i.MX95 SoC embeds a Synopsys Designware MIPI DSI host controller and a Synopsys Designware MIPI DPHY. Unlike the i.MX93 PHY, the i.MX95 PHY uses more syscon interfaces to configure the PHY. Signed-off-by: Marek Vasut --- Cc: Abel Vesa Cc: Conor Dooley Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Laurent Pinchart Cc: Liu Ying Cc: Lucas Stach Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rob Herring Cc: Shawn Guo Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org --- .../display/bridge/fsl,imx93-mipi-dsi.yaml | 48 +++++++++++++++++-- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml index d6e51d0cf5464..388301c4f95c1 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx93-mipi-dsi.yaml @@ -14,12 +14,11 @@ description: | Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations and extensions to them are controlled by i.MX93 media blk-ctrl. -allOf: - - $ref: snps,dw-mipi-dsi.yaml# - properties: compatible: - const: fsl,imx93-mipi-dsi + enum: + - fsl,imx93-mipi-dsi + - fsl,imx95-mipi-dsi clocks: items: @@ -46,13 +45,52 @@ properties: controller and MIPI DPHY PLL related configurations through PLL SoC interface. + fsl,disp-master-csr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + i.MX95 Display Master CSR is a syscon which includes registers to + control DSI clock settings, clock gating, and pixel link select. + + fsl,disp-stream-csr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + i.MX95 Display Stream CSR is a syscon which includes configuration + and status registers for the DSI host. + + fsl,mipi-combo-phy-csr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + i.MX95 Display Stream CSR is a syscon which configuration and status + registers for the MIPI Tx DPHY module in the Camera domain. + power-domains: maxItems: 1 +allOf: + - $ref: snps,dw-mipi-dsi.yaml# + - if: + properties: + compatible: + contains: + const: fsl,imx93-mipi-dsi + then: + required: + - fsl,media-blk-ctrl + + - if: + properties: + compatible: + contains: + const: fsl,imx95-mipi-dsi + then: + required: + - fsl,disp-master-csr + - fsl,disp-stream-csr + - fsl,mipi-combo-phy-csr + required: - compatible - interrupts - - fsl,media-blk-ctrl - power-domains unevaluatedProperties: false -- 2.51.0