From: Marek Vasut <marek.vasut@mailbox.org>
To: dri-devel@lists.freedesktop.org
Cc: Marek Vasut <marek.vasut@mailbox.org>,
Abel Vesa <abelvesa@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Liu Ying <victor.liu@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>, Peng Fan <peng.fan@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: [PATCH 39/39] arm64: dts: imx95: Describe display pipeline
Date: Sat, 11 Oct 2025 18:51:54 +0200 [thread overview]
Message-ID: <20251011170213.128907-40-marek.vasut@mailbox.org> (raw)
In-Reply-To: <20251011170213.128907-1-marek.vasut@mailbox.org>
Describe the entire i.MX95 display pipeline, which includes the DPU or DC
display controller, MIPI DSI serializer, LVDS serializer and the bridges
between those components.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
---
Cc: Abel Vesa <abelvesa@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Liu Ying <victor.liu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: devicetree@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: imx@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx95.dtsi | 710 +++++++++++++++++++++++
1 file changed, 710 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index ad47b7f0d173a..e26942ab0b28b 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -19,6 +19,87 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ ldb_pll_pixel: ldb_pll_div7 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&scmi_clk IMX95_CLK_LDBPLL>;
+ clock-div = <7>;
+ clock-mult = <1>;
+ clock-output-names = "ldb_pll_div7";
+ };
+
+ display_pixel_link_0: pixel-link-0 {
+ compatible = "fsl,imx95-dc-pixel-link";
+ fsl,dc-stream-id = /bits/ 8 <0>;
+ fsl,syscon = <&dispmix_csr>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ display_pixel_link0_to_pixel_interleaver_disp0: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp0_to_display_pixel_link0>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ display_pixel_link0_to_mipi_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_dsi_to_display_pixel_link0>;
+ };
+
+ display_pixel_link0_to_lvds_ch0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds_ch0_to_display_pixel_link0>;
+ };
+ };
+ };
+ };
+
+ display_pixel_link_1: pixel-link-1 {
+ compatible = "fsl,imx95-dc-pixel-link";
+ fsl,dc-stream-id = /bits/ 8 <1>;
+ fsl,syscon = <&dispmix_csr>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ display_pixel_link1_to_pixel_interleaver_disp1: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp1_to_display_pixel_link1>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ display_pixel_link1_to_mipi_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_dsi_to_display_pixel_link1>;
+ };
+
+ display_pixel_link1_to_lvds_ch1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds_ch1_to_display_pixel_link1>;
+ };
+ };
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -1772,6 +1853,635 @@ smmu: iommu@490d0000 {
};
};
+ mipi_dsi: dsi@4acf0000 {
+ compatible = "fsl,imx95-mipi-dsi";
+ reg = <0x0 0x4acf0000 0x0 0x10000>;
+ interrupt-parent = <&displaymix_irqsteer>;
+ interrupts = <48>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>,
+ <&scmi_clk IMX95_CLK_DISP1PIX>,
+ <&scmi_clk IMX95_CLK_MIPIPHYCFG>,
+ <&scmi_clk IMX95_CLK_MIPIPHYPLLREF>;
+ clock-names = "pclk", "pix", "phy_cfg", "phy_ref";
+ assigned-clocks = <&scmi_clk IMX95_CLK_MIPIPHYCFG>,
+ <&scmi_clk IMX95_CLK_MIPIPHYPLLBYPASS>,
+ <&scmi_clk IMX95_CLK_MIPIPHYPLLREF>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_24M>,
+ <&scmi_clk IMX95_CLK_VIDEOPLL1>,
+ <&scmi_clk IMX95_CLK_24M>;
+ power-domains = <&scmi_devpd IMX95_PD_CAMERA>;
+ fsl,disp-master-csr = <&display_master_csr>;
+ fsl,disp-stream-csr = <&display_stream_csr>;
+ fsl,mipi-combo-phy-csr = <&mipi_tx_phy_csr>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_dsi_to_display_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&display_pixel_link0_to_mipi_dsi>;
+ };
+
+ mipi_dsi_to_display_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&display_pixel_link1_to_mipi_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ display_stream_csr: syscon@4ad00000 {
+ compatible = "nxp,imx95-display-stream-csr", "syscon";
+ reg = <0x0 0x4ad00000 0x0 0x10000>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>;
+ };
+
+ display_master_csr: syscon@4ad10000 {
+ compatible = "nxp,imx95-master-stream-csr", "syscon";
+ reg = <0x0 0x4ad10000 0x0 0x10000>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>;
+ };
+
+ mipi_tx_phy_csr: syscon@4ad20100 {
+ compatible = "nxp,imx95-mipi-tx-phy-csr", "syscon";
+ reg = <0x0 0x4ad20100 0x0 0x14>;
+ clocks = <&scmi_clk IMX95_CLK_CAMAPB>;
+ };
+
+ dispmix_csr: syscon@4b010000 {
+ compatible = "nxp,imx95-display-csr", "syscon";
+ reg = <0x0 0x4b010000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ };
+
+ displaymix_irqsteer: interrupt-controller@4b0b0000 {
+ compatible = "fsl,imx95-irqsteer", "fsl,imx-irqsteer";
+ reg = <0x0 0x4b0b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, /* reserved */
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, /* reserved */
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <512>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ status = "disabled";
+ };
+
+ lvds_csr: syscon@4b0c0000 {
+ compatible = "nxp,imx95-lvds-csr", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x4b0c0000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+
+ lvds: lvds@4 {
+ compatible = "fsl,imx95-lvds";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4 0x4>;
+ clocks = <&lvds_csr IMX95_CLK_DISPMIX_PIX_DI0_GATE>,
+ <&lvds_csr IMX95_CLK_DISPMIX_PIX_DI1_GATE>,
+ <&lvds_csr IMX95_CLK_DISPMIX_LVDS_CH0_GATE>,
+ <&lvds_csr IMX95_CLK_DISPMIX_LVDS_CH1_GATE>;
+ clock-names = "ldb_di0", "ldb_di1", "ldb_ch0", "ldb_ch1";
+ status = "disabled";
+
+ lvds_ch0: channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lvds_ch0_to_display_pixel_link0: endpoint {
+ remote-endpoint = <&display_pixel_link0_to_lvds_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_ch0_to_ldb0: endpoint {
+ remote-endpoint = <&ldb0_to_lvds_ch0>;
+ };
+ };
+ };
+
+ lvds_ch1: channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lvds_ch1_to_display_pixel_link1: endpoint {
+ remote-endpoint = <&display_pixel_link1_to_lvds_ch1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_ch1_to_ldb1: endpoint {
+ remote-endpoint = <&ldb1_to_lvds_ch1>;
+ };
+ };
+ };
+ };
+
+ ldb0: phy@8 {
+ compatible = "fsl,imx95-ldb";
+ reg = <0x8 0x4>, <0x8 0x4>;
+ reg-names = "ldb", "lvds";
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ clock-names = "ldb";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ldb0_to_lvds_ch0: endpoint {
+ remote-endpoint = <&lvds_ch0_to_ldb0>;
+ };
+ };
+
+ ldb0_port1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ ldb1: phy@c {
+ compatible = "fsl,imx95-ldb";
+ reg = <0xc 0x4>, <0xc 0x4>;
+ reg-names = "ldb", "lvds";
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ clock-names = "ldb";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ldb1_to_lvds_ch1: endpoint {
+ remote-endpoint = <&lvds_ch1_to_ldb1>;
+ };
+ };
+
+ ldb1_port1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+
+ pixel_interleaver_0: bridge@4b0d0000 {
+ compatible = "fsl,imx95-pixel-interleaver";
+ reg = <0x0 0x4b0d0000 0x0 0x50>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ fsl,syscon = <&dispmix_csr>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pixel_interleaver_disp0_to_dpu_disp0: endpoint {
+ remote-endpoint = <&dpu_disp0_to_pixel_interleaver_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pixel_interleaver_disp0_to_display_pixel_link0: endpoint {
+ remote-endpoint = <&display_pixel_link0_to_pixel_interleaver_disp0>;
+ };
+ };
+ };
+ };
+
+ pixel_interleaver_1: bridge@4b0e0000 {
+ compatible = "fsl,imx95-pixel-interleaver";
+ reg = <0x0 0x4b0e0000 0x0 0x50>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>;
+ fsl,syscon = <&dispmix_csr>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pixel_interleaver_disp1_to_dpu_disp1: endpoint {
+ remote-endpoint = <&dpu_disp1_to_pixel_interleaver_disp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pixel_interleaver_disp1_to_display_pixel_link1: endpoint {
+ remote-endpoint = <&display_pixel_link1_to_pixel_interleaver_disp1>;
+ };
+ };
+ };
+ };
+
+ dpu: display-controller@4b400000 {
+ compatible = "fsl,imx95-dc";
+ reg = <0 0x4b400000 0 0x400000>;
+ clocks = <&scmi_clk IMX95_CLK_DISP1PIX>,
+ <&scmi_clk IMX95_CLK_DISPAPB>,
+ <&scmi_clk IMX95_CLK_DISPAXI>,
+ <&scmi_clk IMX95_CLK_DISPOCRAM>,
+ <&ldb_pll_pixel>,
+ <&scmi_clk IMX95_CLK_LDBPLL_VCO>;
+ clock-names = "pix", "apb", "axi", "ocram", "ldb", "ldb_vco";
+ fsl,syscon = <&dispmix_csr>;
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ assigned-clocks = <&scmi_clk IMX95_CLK_DISPAXI>,
+ <&scmi_clk IMX95_CLK_DISPOCRAM>,
+ <&scmi_clk IMX95_CLK_DISPAPB>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <400000000>, <400000000>, <133333333>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dc1_intc: interrupt-controller@4b781000 {
+ compatible = "fsl,imx95-dc-intc";
+ reg = <0 0x4b781000 0 0x60>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>,
+ <&scmi_clk IMX95_CLK_DISPAXI>;
+ clock-names = "apb", "axi";
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&displaymix_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <192>, <193>, <194>,
+ <195>, <196>, <197>, <70>,
+ <71>, <72>, <73>, <74>,
+ <75>, <76>, <77>, <78>,
+ <79>, <80>, <81>, <82>,
+ <83>, <84>, <85>, <86>,
+ <87>, <88>, <89>, <90>,
+ <91>, <92>, <198>, <199>,
+ <200>, <201>, <202>, <203>,
+ <204>, <205>, <206>, <207>,
+ <208>, <209>, <210>, <211>,
+ <212>, <451>, <1>, <2>,
+ <3>, <4>, <93>, <94>,
+ <95>, <96>, <97>, <98>,
+ <99>, <100>, <101>, <102>,
+ <103>, <104>, <105>, <106>,
+ <213>, <214>, <215>, <216>,
+ <217>, <218>, <219>, <220>,
+ <221>, <222>, <223>, <224>,
+ <225>, <226>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "domainblend0_shdload",
+ "domainblend0_framecomplete",
+ "domainblend0_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "sig0_cluster_error",
+ "sig0_cluster_match",
+ "sig2_shdload",
+ "sig2_valid",
+ "sig2_error",
+ "sig2_cluster_error",
+ "sig2_cluster_match",
+ "idhash0_shdload",
+ "idhash0_valid",
+ "idhash0_window_error",
+ "domainblend1_shdload",
+ "domainblend1_framecomplete",
+ "domainblend1_seqcomplete",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "sig1_cluster_error",
+ "sig1_cluster_match",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_overflow0_on",
+ "framegen0_overflow0_off",
+ "framegen0_underrun0_on",
+ "framegen0_underrun0_off",
+ "framegen0_threshold0_rise",
+ "framegen0_threshold0_fail",
+ "framegen0_overflow1_on",
+ "framegen0_overflow1_off",
+ "framegen0_underrun1_on",
+ "framegen0_underrun1_off",
+ "framegen0_threshold1_rise",
+ "framegen0_threshold1_fail",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_overflow0_on",
+ "framegen1_overflow0_off",
+ "framegen1_underrun0_on",
+ "framegen1_underrun0_off",
+ "framegen1_threshold0_rise",
+ "framegen1_threshold0_fail",
+ "framegen1_overflow1_on",
+ "framegen1_overflow1_off",
+ "framegen1_underrun1_on",
+ "framegen1_underrun1_off",
+ "framegen1_threshold1_rise",
+ "framegen1_threshold1_fail";
+ };
+
+ pixel-engine@4b4f0000 {
+ compatible = "fsl,imx95-dc-pixel-engine", "fsl,imx8qxp-dc-pixel-engine";
+ reg = <0 0x4b4f0000 0 0x1d0000>;
+ clocks = <&scmi_clk IMX95_CLK_DISPAPB>,
+ <&scmi_clk IMX95_CLK_DISPAXI>;
+ clock-names = "apb", "axi";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ constframe@4b4f0000 {
+ compatible = "fsl,imx95-dc-constframe";
+ reg = <0 0x4b4f1000 0 0xc>, <0 0x4b4f0000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ extdst@4b510000 {
+ compatible = "fsl,imx95-dc-extdst";
+ reg = <0 0x4b511000 0 0x1c>, <0 0x4b510000 0 0x28>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <3>, <4>, <5>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ };
+
+ constframe@4b500000 {
+ compatible = "fsl,imx95-dc-constframe";
+ reg = <0 0x4b501000 0 0xc>, <0 0x4b500000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ extdst@4b520000 {
+ compatible = "fsl,imx95-dc-extdst";
+ reg = <0 0x4b521000 0 0x1c>, <0 0x4b520000 0 0x28>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <9>, <10>, <11>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ };
+
+ constframe@4b530000 {
+ compatible = "fsl,imx95-dc-constframe";
+ reg = <0 0x4b531000 0 0xc>, <0 0x4b530000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ extdst@4b550000 {
+ compatible = "fsl,imx95-dc-extdst";
+ reg = <0 0x4b551000 0 0x1c>, <0 0x4b550000 0 0x28>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <6>, <7>, <8>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ };
+
+ constframe@4b540000 {
+ compatible = "fsl,imx95-dc-constframe";
+ reg = <0 0x4b541000 0 0xc>, <0 0x4b540000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ extdst@4b560000 {
+ compatible = "fsl,imx95-dc-extdst";
+ reg = <0 0x4b561000 0 0x1c>, <0 0x4b560000 0 0x28>;
+ reg-names = "pec", "cfg";
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <12>, <13>, <14>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ };
+
+ fetchlayer@4b5d0000 {
+ compatible = "fsl,imx95-dc-fetchlayer";
+ reg = <0 0x4b5d1000 0 0xc>, <0 0x4b5d0000 0 0x404>;
+ reg-names = "pec", "cfg";
+ };
+
+ fetchlayer@4b5e0000 {
+ compatible = "fsl,imx95-dc-fetchlayer";
+ reg = <0 0x4b5e1000 0 0xc>, <0 0x4b5e0000 0 0x404>;
+ reg-names = "pec", "cfg";
+ };
+
+ layerblend@4b570000 {
+ compatible = "fsl,imx95-dc-layerblend";
+ reg = <0 0x4b571000 0 0x10>, <0 0x4b570000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ layerblend@4b580000 {
+ compatible = "fsl,imx95-dc-layerblend";
+ reg = <0 0x4b581000 0 0x10>, <0 0x4b580000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ layerblend@4b590000 {
+ compatible = "fsl,imx95-dc-layerblend";
+ reg = <0 0x4b591000 0 0x10>, <0 0x4b590000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ layerblend@4b5a0000 {
+ compatible = "fsl,imx95-dc-layerblend";
+ reg = <0 0x4b5a1000 0 0x10>, <0 0x4b5a0000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ layerblend@4b5b0000 {
+ compatible = "fsl,imx95-dc-layerblend";
+ reg = <0 0x4b5b1000 0 0x10>, <0 0x4b5b0000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+
+ layerblend@4b5c0000 {
+ compatible = "fsl,imx95-dc-layerblend";
+ reg = <0 0x4b5c1000 0 0x10>, <0 0x4b5c0000 0 0x20>;
+ reg-names = "pec", "cfg";
+ };
+ };
+
+ display-engine@4b600000 {
+ compatible = "fsl,imx95-dc-display-engine";
+ reg = <0 0x4b711000 0 0x14>, <0 0x4b710000 0 0x1c00>;
+ reg-names = "top", "cfg";
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <18>, <19>, <20>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ domainblend@4b6a0000 {
+ compatible = "fsl,imx95-dc-domainblend";
+ reg = <0 0x4b6a0000 0 0x20>;
+ };
+
+ framegen@4b6b0000 {
+ compatible = "fsl,imx95-dc-framegen";
+ reg = <0 0x4b6b0000 0 0x98>;
+
+ clocks = <&scmi_clk IMX95_CLK_DISP1PIX>,
+ <&scmi_clk IMX95_CLK_DISPAPB>,
+ <&scmi_clk IMX95_CLK_DISPAXI>,
+ <&scmi_clk IMX95_CLK_DISPOCRAM>,
+ <&ldb_pll_pixel>,
+ <&scmi_clk IMX95_CLK_LDBPLL_VCO>;
+ clock-names = "pix", "apb", "axi", "ocram", "ldb", "ldb_vco";
+
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <21>, <22>, <23>, <24>, <58>, <59>;
+ interrupt-names = "int0", "int1", "int2", "int3",
+ "primsync_on", "primsync_off";
+ };
+
+ tcon {
+ compatible = "fsl,imx95-dc-tcon";
+
+ port {
+ dpu_disp0_to_pixel_interleaver_disp0: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp0_to_dpu_disp0>;
+ };
+ };
+ };
+ };
+
+ display-engine@4b700000 {
+ compatible = "fsl,imx95-dc-display-engine";
+ reg = <0 0x4b771000 0 0x14>, <0 0x4b770000 0 0x1c00>;
+ reg-names = "top", "cfg";
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <41>, <42>, <43>;
+ interrupt-names = "shdload", "framecomplete", "seqcomplete";
+ power-domains = <&scmi_devpd IMX95_PD_DISPLAY>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ domainblend@4b720000 {
+ compatible = "fsl,imx95-dc-domainblend";
+ reg = <0 0x4b720000 0 0x20>;
+ };
+
+ framegen@4b730000 {
+ compatible = "fsl,imx95-dc-framegen";
+ reg = <0 0x4b730000 0 0x98>;
+
+ clocks = <&scmi_clk IMX95_CLK_DISP1PIX>,
+ <&scmi_clk IMX95_CLK_DISPAPB>,
+ <&scmi_clk IMX95_CLK_DISPAXI>,
+ <&scmi_clk IMX95_CLK_DISPOCRAM>,
+ <&ldb_pll_pixel>,
+ <&scmi_clk IMX95_CLK_LDBPLL_VCO>;
+ clock-names = "pix", "apb", "axi", "ocram", "ldb", "ldb_vco";
+
+ interrupt-parent = <&dc1_intc>;
+ interrupts = <34>, <35>, <36>, <37>, <72>, <73>;
+ interrupt-names = "int0", "int1", "int2", "int3",
+ "primsync_on", "primsync_off";
+ };
+
+ tcon {
+ compatible = "fsl,imx95-dc-tcon";
+
+ port {
+ dpu_disp1_to_pixel_interleaver_disp1: endpoint {
+ remote-endpoint = <&pixel_interleaver_disp1_to_dpu_disp1>;
+ };
+ };
+ };
+ };
+ };
+
usb3: usb@4c010010 {
compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";
reg = <0x0 0x4c010010 0x0 0x04>,
--
2.51.0
next prev parent reply other threads:[~2025-10-11 17:04 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-11 16:51 [PATCH 00/39] Add i.MX95 DPU/DSI/LVDS support Marek Vasut
2025-10-11 16:51 ` [PATCH 01/39] dt-bindings: display: imx: Document i.MX95 Display Controller DomainBlend Marek Vasut
2025-10-15 13:24 ` Rob Herring
2025-10-16 2:07 ` Liu Ying
2025-10-17 15:15 ` Marek Vasut
2025-10-18 6:09 ` Ying Liu
2025-11-02 16:41 ` Marek Vasut
2025-11-04 3:31 ` Liu Ying
2025-10-21 6:52 ` Krzysztof Kozlowski
2025-10-11 16:51 ` [PATCH 02/39] drm/imx: Add " Marek Vasut
2025-10-13 16:38 ` Frank Li
2025-10-14 11:50 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 03/39] dt-bindings: display: imx: Document i.MX95 Display Controller processing units Marek Vasut
2025-10-13 16:49 ` Frank Li
2025-10-14 11:52 ` Marek Vasut
2025-10-15 8:59 ` Liu Ying
2025-10-15 10:19 ` Marek Vasut
2025-10-16 2:28 ` Liu Ying
2025-10-16 2:58 ` Liu Ying
2025-10-17 15:18 ` Marek Vasut
2025-10-18 5:44 ` Ying Liu
2025-10-11 16:51 ` [PATCH 04/39] drm/imx: dc: Use bulk clock Marek Vasut
2025-10-13 16:54 ` Frank Li
2025-10-14 12:02 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 05/39] drm/imx: dc: Rework dc_subdev_get_id() to drop ARRAY_SIZE() use Marek Vasut
2025-10-13 16:56 ` Frank Li
2025-10-14 14:03 ` Marek Vasut
2025-10-14 15:11 ` Frank Li
2025-10-14 21:11 ` Marek Vasut
2025-10-15 9:14 ` Liu Ying
2025-10-15 14:31 ` Frank Li
2025-10-16 2:50 ` Liu Ying
2025-10-11 16:51 ` [PATCH 06/39] drm/imx: dc: Rename i.MX8QXP specific Link IDs Marek Vasut
2025-10-13 16:58 ` Frank Li
2025-10-11 16:51 ` [PATCH 07/39] drm/imx: dc: cf: Pass struct dc_subdev_info via OF match data Marek Vasut
2025-10-13 17:01 ` Frank Li
2025-10-11 16:51 ` [PATCH 08/39] drm/imx: dc: de: Pass struct dc_de_subdev_match_data " Marek Vasut
2025-10-13 17:05 ` Frank Li
2025-10-11 16:51 ` [PATCH 09/39] drm/imx: dc: ed: Rework dc_ed_pec_src_sel() to drop ARRAY_SIZE() use Marek Vasut
2025-10-13 18:24 ` Frank Li
2025-10-11 16:51 ` [PATCH 10/39] drm/imx: dc: ed: Pass struct dc_ed_subdev_match_data via OF match data Marek Vasut
2025-10-13 18:26 ` Frank Li
2025-10-11 16:51 ` [PATCH 11/39] drm/imx: dc: fg: Parametrize register access Marek Vasut
2025-10-13 18:29 ` Frank Li
2025-10-11 16:51 ` [PATCH 12/39] drm/imx: dc: ed: Pass struct dc_fg_subdev_match_data via OF match data Marek Vasut
2025-10-13 18:31 ` Frank Li
2025-10-11 16:51 ` [PATCH 13/39] drm/imx: dc: fu: Describe remaining register offsets Marek Vasut
2025-10-13 18:34 ` Frank Li
2025-10-11 16:51 ` [PATCH 14/39] drm/imx: dc: fu: Inline FRAC_OFFSET into FetchLayer and FetchWrap Marek Vasut
2025-10-13 18:39 ` Frank Li
2025-10-11 16:51 ` [PATCH 15/39] drm/imx: dc: fu: Pass struct dc_fu_subdev_match_data via OF match data Marek Vasut
2025-10-13 18:43 ` Frank Li
2025-10-11 16:51 ` [PATCH 16/39] drm/imx: dc: lb: Pass struct dc_lb_subdev_match_data " Marek Vasut
2025-10-13 18:45 ` Frank Li
2025-10-11 16:51 ` [PATCH 17/39] drm/imx: dc: tc: Pass struct dc_tc_subdev_match_data " Marek Vasut
2025-10-11 16:51 ` [PATCH 18/39] drm/imx: dc: ic: Pass struct dc_ic_subdev_match_data " Marek Vasut
2025-10-11 16:51 ` [PATCH 19/39] drm/imx: dc: ic: Use DT node as interrupt controller name Marek Vasut
2025-10-11 16:51 ` [PATCH 20/39] drm/imx: dc: Configure display CSR clock feed select Marek Vasut
2025-10-13 18:48 ` Frank Li
2025-10-17 15:20 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 21/39] drm/imx: dc: crtc: Do not check disabled CRTCs Marek Vasut
2025-10-13 18:50 ` Frank Li
2025-10-14 21:41 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 22/39] drm/imx: dc: Keep FU unit running on i.MX95 Marek Vasut
2025-10-13 18:52 ` Frank Li
2025-10-11 16:51 ` [PATCH 23/39] drm/imx: dc: Add OF match data for i.MX95 Marek Vasut
2025-10-13 18:54 ` Frank Li
2025-10-11 16:51 ` [PATCH 24/39] drm/imx: Add more RGB swizzling options Marek Vasut
2025-10-11 16:51 ` [PATCH 25/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel interleaver support Marek Vasut
2025-10-13 18:57 ` Frank Li
2025-10-17 14:55 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 26/39] drm/bridge: imx: Add " Marek Vasut
2025-10-13 19:02 ` Frank Li
2025-10-11 16:51 ` [PATCH 27/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel link support Marek Vasut
2025-10-13 19:08 ` Frank Li
2025-10-17 15:01 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 28/39] drm/bridge: imx: Add " Marek Vasut
2025-10-13 19:10 ` Frank Li
2025-10-11 16:51 ` [PATCH 29/39] dt-bindings: display: bridge: Document Freescale i.MX95 MIPI DSI Marek Vasut
2025-10-13 19:13 ` Frank Li
2025-10-17 15:37 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 30/39] drm/bridge: imx93-mipi-dsi: Add i.MX95 PLL initialization Marek Vasut
2025-10-11 16:51 ` [PATCH 31/39] dt-bindings: clock: Split support for i.MX95 LVDS CSR Marek Vasut
2025-10-13 19:17 ` Frank Li
2025-10-17 15:49 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 32/39] dt-bindings: display: bridge: Document i.MX95 LVDS display bridge binding Marek Vasut
2025-10-13 19:20 ` Frank Li
2025-10-17 15:04 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 33/39] drm: bridge: imx: Add i.MX95 LVDS Display Bridge (LDB) driver Marek Vasut
2025-10-11 16:51 ` [PATCH 34/39] dt-bindings: display: bridge: ldb: Add an i.MX95 entry Marek Vasut
2025-10-13 11:34 ` Rob Herring (Arm)
2025-10-11 16:51 ` [PATCH 35/39] drm/bridge: fsl-ldb: Parse register offsets from DT Marek Vasut
2025-10-13 19:23 ` Frank Li
2025-10-17 15:39 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 36/39] drm/bridge: fsl-ldb: Add i.MX95 support Marek Vasut
2025-10-13 19:24 ` Frank Li
2025-10-11 16:51 ` [PATCH 37/39] dt-bindings: interrupt-controller: fsl,irqsteer: " Marek Vasut
2025-10-13 19:25 ` Frank Li
2025-10-15 13:31 ` Rob Herring (Arm)
2025-10-11 16:51 ` [PATCH 38/39] dt-bindings: clock: support i.MX95 Display Stream CSR module Marek Vasut
2025-10-13 19:26 ` Frank Li
2025-10-17 15:05 ` Marek Vasut
2025-10-15 13:33 ` Rob Herring
2025-10-17 15:08 ` Marek Vasut
2025-10-11 16:51 ` Marek Vasut [this message]
2025-10-14 8:51 ` [PATCH 00/39] Add i.MX95 DPU/DSI/LVDS support Liu Ying
2025-10-14 21:55 ` Marek Vasut
2025-10-15 10:00 ` Liu Ying
2025-10-15 16:18 ` Marek Vasut
2025-10-20 2:15 ` Ying Liu
2025-11-02 16:33 ` Marek Vasut
2025-11-04 7:00 ` Liu Ying
2025-10-14 9:13 ` Liu Ying
2025-10-14 22:09 ` Marek Vasut
2025-10-15 10:09 ` Liu Ying
2025-10-17 15:54 ` Marek Vasut
2025-10-20 2:35 ` Liu Ying
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