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Mon, 13 Oct 2025 13:52:01 -0700 (PDT) From: Peter Griffin Date: Mon, 13 Oct 2025 21:51:38 +0100 Subject: [PATCH 9/9] clk: samsung: gs101: remove CLK_IGNORE_UNUSED and CLK_IS_CRITICAL flags Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251013-automatic-clocks-v1-9-72851ee00300@linaro.org> References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> In-Reply-To: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi Cc: Will McVicker , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Now each CMU is in automatic mode these flags are no longer necessary. All unused clocks are automatically gated & ungated by hardware as required. Signed-off-by: Peter Griffin --- drivers/clk/samsung/clk-gs101.c | 87 +++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 52 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index baf41ae6c9e2480cb83531acf7eae190c6aff819..d01c94994d86bc27d344969c33955da63ed0e4a1 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -1901,13 +1901,13 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = { CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, "gout_apm_uasc_p_apm_pclk", "gout_apm_func", - CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0), + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_APM_WDT_APM_PCLK, "gout_apm_wdt_apm_pclk", "gout_apm_func", CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", - CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0), + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), }; static const unsigned long dcrg_memclk_sysreg[] __initconst = { @@ -2211,11 +2211,10 @@ static const struct samsung_div_clock hsi0_div_clks[] __initconst = { }; static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = { - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_PCLK, "gout_hsi0_hsi0_pclk", "mout_hsi0_bus", CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26, "gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26", "mout_hsi0_usb20_ref", @@ -2252,16 +2251,14 @@ static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = { "gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK, "gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK, "gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK, "gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK, @@ -2286,21 +2283,18 @@ static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = { "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK, "gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK, "gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2, "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK, "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, @@ -2358,21 +2352,18 @@ static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = { "gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK, "gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK, "gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK, "gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus", CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), }; static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = { @@ -2677,22 +2668,19 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK, "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21, - CLK_IGNORE_UNUSED, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ + 0, 0), GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK, "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK, "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK, - 21, CLK_IS_CRITICAL, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK, "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK, "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, @@ -2795,38 +2783,35 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK, "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK, "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK, "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK, "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk", CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, 21, 0, 0), - /* TODO: should have a driver for this */ GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK, "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK, "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2, "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK, "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK, "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, @@ -2862,25 +2847,23 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK, "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO, "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK, "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, - 21, CLK_IS_CRITICAL, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK, "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), - /* TODO: should have a driver for this */ + 21, 0, 0), GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK, "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user", CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), }; static const struct samsung_cmu_info hsi2_cmu_info __initconst = { @@ -3849,7 +3832,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, "gout_peric0_clk_peric0_oscclk_clk", "oscclk", CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, @@ -3865,12 +3848,12 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, @@ -4003,7 +3986,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, @@ -4012,7 +3995,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, @@ -4310,7 +4293,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC1_PCLK, "gout_peric1_peric1_pclk", "mout_peric1_bus_user", CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, @@ -4330,11 +4313,11 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, - 21, CLK_IGNORE_UNUSED, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, -- 2.51.0.760.g7b8bcc2412-goog