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Mon, 13 Oct 2025 04:15:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHUqBMHoqhVV+uP7cey3LAt770FSA4Et8Avsavd59CQxq+OTW7LvyN55HaT1Bq0FyA9hJprYw== X-Received: by 2002:a17:907:25c6:b0:b3b:4e6:46e6 with SMTP id a640c23a62f3a-b50aa393beamr2047102566b.1.1760354154847; Mon, 13 Oct 2025 04:15:54 -0700 (PDT) Received: from holism.Home ([2a06:5900:814a:ab00:c1c7:2e09:633d:e94e]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b55d5cad8adsm917336966b.7.2025.10.13.04.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 04:15:54 -0700 (PDT) From: Lucas Zampieri To: linux-kernel@vger.kernel.org Cc: Lucas Zampieri , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Vivian Wang , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 0/3] Add UltraRISC DP1000 PLIC support Date: Mon, 13 Oct 2025 12:15:35 +0100 Message-ID: <20251013111539.2206477-1-lzampier@redhat.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds support for the PLIC implementation in the UltraRISC DP1000 SoC. The DP1000 PLIC claim register has a hardware bug where reading it while multiple interrupts are pending can return the wrong interrupt ID. The workaround temporarily disables all interrupts except the first pending one before reading the claim register, then restores the previous state. The driver matches on "ultrarisc,cp100-plic" (CPU core compatible), allowing the quirk to apply to all SoCs using UR-CP100 cores (currently DP1000, potentially future SoCs). Charles Mirabile (2): dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC irqchip/plic: add support for UltraRISC DP1000 PLIC Lucas Zampieri (1): dt-bindings: vendor-prefixes: add UltraRISC Changes in v2: - 0002: Changed compatible string pattern to SoC+core: ultrarisc,dp1000-plic with ultrarisc,cp100-plic fallback (suggested by Krzysztof and Vivian) - 0003: Driver now matches on ultrarisc,cp100-plic (core) instead of dp1000 (SoC) - All patches: Added submitter Signed-off-by to complete DCO chain .../devicetree/bindings/vendor-prefixes.yaml | 2 + .../interrupt-controller/sifive,plic-1.0.0.yaml | 3 + drivers/irqchip/irq-sifive-plic.c | 83 ++++++++++++++++++- 3 files changed, 87 insertions(+), 1 deletion(-) -- 2.51.0