From: Richard Genoud <richard.genoud@bootlin.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>
Cc: "Uwe Kleine-König" <u.kleine-koenig@baylibre.com>,
"Wentao Liang" <vulab@iscas.ac.cn>,
"Johan Hovold" <johan@kernel.org>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
"Richard Genoud" <richard.genoud@bootlin.com>
Subject: [PATCH v2 15/15] arm64: dts: allwinner: h616: add NAND controller
Date: Mon, 13 Oct 2025 17:26:45 +0200 [thread overview]
Message-ID: <20251013152645.1119308-16-richard.genoud@bootlin.com> (raw)
In-Reply-To: <20251013152645.1119308-1-richard.genoud@bootlin.com>
The H616 has a NAND controller quite similar to the A10/A23 ones, but
with some register differences, more clocks (for ECC and MBUS), more ECC
strengths, so this requires a new compatible string.
Add the NAND controller node and pins in the device tree.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index ceedae9e399b..bb53c6c63836 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -304,6 +304,42 @@ mmc2_pins: mmc2-pins {
bias-pull-up;
};
+ /omit-if-no-ref/
+ nand_pins: nand-pins {
+ pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9",
+ "PC10", "PC11", "PC12", "PC13", "PC14",
+ "PC15", "PC16";
+ function = "nand0";
+ };
+
+ /omit-if-no-ref/
+ nand_cs0_pin: nand-cs0-pin {
+ pins = "PC4";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ nand_cs1_pin: nand-cs1-pin {
+ pins = "PC3";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ nand_rb0_pin: nand-rb0-pin {
+ pins = "PC6";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ nand_rb1_pin: nand-rb1-pin {
+ pins = "PC7";
+ function = "nand0";
+ bias-pull-up;
+ };
+
/omit-if-no-ref/
spi0_pins: spi0-pins {
pins = "PC0", "PC2", "PC4";
@@ -377,6 +413,21 @@ iommu: iommu@30f0000 {
#iommu-cells = <1>;
};
+ nfc: nand-controller@4011000 {
+ compatible = "allwinner,sun50i-h616-nand-controller";
+ reg = <0x04011000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>,
+ <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>;
+ clock-names = "ahb", "mod", "ecc", "mbus";
+ resets = <&ccu RST_BUS_NAND>;
+ reset-names = "ahb";
+ dmas = <&dma 10>;
+ dma-names = "rxtx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
mmc0: mmc@4020000 {
compatible = "allwinner,sun50i-h616-mmc",
"allwinner,sun50i-a100-mmc";
next prev parent reply other threads:[~2025-10-13 15:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 15:26 [PATCH v2 00/15] Introduce Allwinner H6/H616 NAND controller support Richard Genoud
2025-10-13 15:26 ` [PATCH v2 01/15] mtd: rawnand: sunxi: Remove superfluous register readings Richard Genoud
2025-10-13 15:26 ` [PATCH v2 02/15] mtd: rawnand: sunxi: move ECC strenghts in sunxi_nfc_caps Richard Genoud
2025-10-13 15:54 ` Chen-Yu Tsai
2025-10-13 15:26 ` [PATCH v2 03/15] mtd: rawnand: sunxi: introduce reg_ecc_err_cnt " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 04/15] mtd: rawnand: sunxi: introduce reg_user_data " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 05/15] mtd: rawnand: sunxi: rework pattern found registers Richard Genoud
2025-10-13 15:26 ` [PATCH v2 06/15] mtd: rawnand: sunxi: add has_ecc_block_512 capability Richard Genoud
2025-10-13 15:26 ` [PATCH v2 07/15] mtd: rawnand: sunxi: introduce ecc_mode_mask in sunxi_nfc_caps Richard Genoud
2025-10-13 15:26 ` [PATCH v2 08/15] mtd: rawnand: sunxi: introduce random en/dir " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 09/15] mtd: rawnand: sunxi: introduce reg_pat_id " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 10/15] mtd: rawnand: sunxi: introduce reg_spare_area " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 11/15] mtd: rawnand: sunxi: introduce ecc_err_mask " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 12/15] mtd: rawnand: sunxi: introduce sram_size " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 13/15] mtd: rawnand: sunxi: Add support for H616 nand controller Richard Genoud
2025-10-13 15:26 ` [PATCH v2 14/15] dt-bindings: mtd: sunxi: Add H616 compatible Richard Genoud
2025-10-13 19:44 ` Conor Dooley
2025-10-14 7:13 ` Richard GENOUD
2025-10-13 15:26 ` Richard Genoud [this message]
2025-10-13 15:43 ` [PATCH v2 15/15] arm64: dts: allwinner: h616: add NAND controller Jernej Škrabec
2025-10-13 15:59 ` Richard GENOUD
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251013152645.1119308-16-richard.genoud@bootlin.com \
--to=richard.genoud@bootlin.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jernej.skrabec@gmail.com \
--cc=johan@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-sunxi@lists.linux.dev \
--cc=miquel.raynal@bootlin.com \
--cc=mripard@kernel.org \
--cc=richard@nod.at \
--cc=robh@kernel.org \
--cc=samuel@sholland.org \
--cc=thomas.petazzoni@bootlin.com \
--cc=u.kleine-koenig@baylibre.com \
--cc=vigneshr@ti.com \
--cc=vulab@iscas.ac.cn \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).