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From: Richard Genoud <richard.genoud@bootlin.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>
Cc: "Uwe Kleine-König" <u.kleine-koenig@baylibre.com>,
	"Wentao Liang" <vulab@iscas.ac.cn>,
	"Johan Hovold" <johan@kernel.org>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
	"Richard Genoud" <richard.genoud@bootlin.com>
Subject: [PATCH v2 07/15] mtd: rawnand: sunxi: introduce ecc_mode_mask in sunxi_nfc_caps
Date: Mon, 13 Oct 2025 17:26:37 +0200	[thread overview]
Message-ID: <20251013152645.1119308-8-richard.genoud@bootlin.com> (raw)
In-Reply-To: <20251013152645.1119308-1-richard.genoud@bootlin.com>

The H6/H616 ECC_MODE field is not at the same offset, and has not the
same size.
So move the mask into sunxi_nfc_caps.

No functional change.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
---
 drivers/mtd/nand/raw/sunxi_nand.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index 70c940840dda..4118307cac15 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -29,8 +29,9 @@
 #include <linux/iopoll.h>
 #include <linux/reset.h>
 
-/* non compile-time field get */
+/* non compile-time field get/prep */
 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
 
 #define NFC_REG_CTL		0x0000
 #define NFC_REG_ST		0x0004
@@ -145,8 +146,8 @@
 #define NFC_ECC_BLOCK_512	BIT(5)
 #define NFC_RANDOM_EN		BIT(9)
 #define NFC_RANDOM_DIRECTION	BIT(10)
-#define NFC_ECC_MODE_MSK	GENMASK(15, 12)
-#define NFC_ECC_MODE(x)		((x) << 12)
+#define NFC_ECC_MODE_MSK(nfc)	(nfc->caps->ecc_mode_mask)
+#define NFC_ECC_MODE(nfc, x)	field_prep(NFC_ECC_MODE_MSK(nfc), (x))
 #define NFC_RANDOM_SEED_MSK	GENMASK(30, 16)
 #define NFC_RANDOM_SEED(x)	((x) << 16)
 
@@ -227,6 +228,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
  * @reg_ecc_err_cnt:	ECC error counter register
  * @reg_user_data:	User data register
  * @reg_pat_found:	Data Pattern Status Register
+ * @ecc_mode_mask:	ECC_MODE mask in NFC_ECC_CTL register
  * @pat_found_mask:	ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register
  * @dma_maxburst:	DMA maxburst
  * @ecc_strengths:	Available ECC strengths array
@@ -239,6 +241,7 @@ struct sunxi_nfc_caps {
 	unsigned int reg_ecc_err_cnt;
 	unsigned int reg_user_data;
 	unsigned int reg_pat_found;
+	unsigned int ecc_mode_mask;
 	unsigned int pat_found_mask;
 	unsigned int dma_maxburst;
 	const u8 *ecc_strengths;
@@ -1747,7 +1750,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_chip *nand,
 	ecc->read_oob_raw = nand_read_oob_std;
 	ecc->write_oob_raw = nand_write_oob_std;
 
-	sunxi_nand->ecc.ecc_ctl = NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION |
+	sunxi_nand->ecc.ecc_ctl = NFC_ECC_MODE(nfc, i) | NFC_ECC_EXCEPTION |
 				  NFC_ECC_PIPELINE | NFC_ECC_EN;
 
 	if (ecc->size == 512) {
@@ -2217,6 +2220,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
 	.reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT,
 	.reg_user_data = NFC_REG_A10_USER_DATA,
 	.reg_pat_found = NFC_REG_ECC_ST,
+	.ecc_mode_mask = GENMASK(15, 12),
 	.pat_found_mask = GENMASK(31, 16),
 	.dma_maxburst = 4,
 	.ecc_strengths = sunxi_ecc_strengths_a10,
@@ -2230,6 +2234,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
 	.reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT,
 	.reg_user_data = NFC_REG_A10_USER_DATA,
 	.reg_pat_found = NFC_REG_ECC_ST,
+	.ecc_mode_mask = GENMASK(15, 12),
 	.pat_found_mask = GENMASK(31, 16),
 	.dma_maxburst = 8,
 	.ecc_strengths = sunxi_ecc_strengths_a10,

  parent reply	other threads:[~2025-10-13 15:27 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 15:26 [PATCH v2 00/15] Introduce Allwinner H6/H616 NAND controller support Richard Genoud
2025-10-13 15:26 ` [PATCH v2 01/15] mtd: rawnand: sunxi: Remove superfluous register readings Richard Genoud
2025-10-13 15:26 ` [PATCH v2 02/15] mtd: rawnand: sunxi: move ECC strenghts in sunxi_nfc_caps Richard Genoud
2025-10-13 15:54   ` Chen-Yu Tsai
2025-10-13 15:26 ` [PATCH v2 03/15] mtd: rawnand: sunxi: introduce reg_ecc_err_cnt " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 04/15] mtd: rawnand: sunxi: introduce reg_user_data " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 05/15] mtd: rawnand: sunxi: rework pattern found registers Richard Genoud
2025-10-13 15:26 ` [PATCH v2 06/15] mtd: rawnand: sunxi: add has_ecc_block_512 capability Richard Genoud
2025-10-13 15:26 ` Richard Genoud [this message]
2025-10-13 15:26 ` [PATCH v2 08/15] mtd: rawnand: sunxi: introduce random en/dir in sunxi_nfc_caps Richard Genoud
2025-10-13 15:26 ` [PATCH v2 09/15] mtd: rawnand: sunxi: introduce reg_pat_id " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 10/15] mtd: rawnand: sunxi: introduce reg_spare_area " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 11/15] mtd: rawnand: sunxi: introduce ecc_err_mask " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 12/15] mtd: rawnand: sunxi: introduce sram_size " Richard Genoud
2025-10-13 15:26 ` [PATCH v2 13/15] mtd: rawnand: sunxi: Add support for H616 nand controller Richard Genoud
2025-10-13 15:26 ` [PATCH v2 14/15] dt-bindings: mtd: sunxi: Add H616 compatible Richard Genoud
2025-10-13 19:44   ` Conor Dooley
2025-10-14  7:13     ` Richard GENOUD
2025-10-13 15:26 ` [PATCH v2 15/15] arm64: dts: allwinner: h616: add NAND controller Richard Genoud
2025-10-13 15:43   ` Jernej Škrabec
2025-10-13 15:59     ` Richard GENOUD

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