[PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Marek Vasut]

Document Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
present in Renesas R-Car R8A77960 M3-W and R8A77961 M3-W+ SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: David Airlie <airlied@gmail.com>
Cc: Frank Binns <frank.binns@imgtec.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Matt Coster <matt.coster@imgtec.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: devicetree@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-renesas-soc@vger.kernel.org
---
See https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/13
for related userspace bits.
---
 .../devicetree/bindings/gpu/img,powervr-rogue.yaml          | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
index c87d7bece0ecd..c9680a2560114 100644
--- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
@@ -13,6 +13,12 @@ maintainers:
 properties:
   compatible:
     oneOf:
+      - items:
+          - enum:
+              - renesas,r8a77960-gpu
+              - renesas,r8a77961-gpu
+          - const: img,img-gx6250
+          - const: img,img-rogue
       - items:
           - enum:
               - ti,am62-gpu
-- 
2.51.0

[PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node

[Marek Vasut]

Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
present in Renesas R-Car R8A77960 M3-W SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: David Airlie <airlied@gmail.com>
Cc: Frank Binns <frank.binns@imgtec.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Matt Coster <matt.coster@imgtec.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: devicetree@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index 6d039019905de..4f7b2e838c026 100644
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -2565,6 +2565,18 @@ gic: interrupt-controller@f1010000 {
 			resets = <&cpg 408>;
 		};
 
+		gpu: gpu@fd000000 {
+			compatible = "renesas,r8a77960-gpu",
+				     "img,img-gx6250",
+				     "img,img-rogue";
+			reg = <0 0xfd000000 0 0x40000>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 112>;
+			clock-names = "core";
+			power-domains = <&sysc R8A7796_PD_3DG_B>;
+			resets = <&cpg 112>;
+		};
+
 		pciec0: pcie@fe000000 {
 			compatible = "renesas,pcie-r8a7796",
 				     "renesas,pcie-rcar-gen3";
-- 
2.51.0

[PATCH 3/3] arm64: dts: renesas: r8a77961: Add GX6250 GPU node

[Marek Vasut]

Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
present in Renesas R-Car R8A77961 M3-W+ SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: David Airlie <airlied@gmail.com>
Cc: Frank Binns <frank.binns@imgtec.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Matt Coster <matt.coster@imgtec.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: devicetree@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index 1637b534fc68b..77ed99e8d7b9e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -2445,6 +2445,18 @@ gic: interrupt-controller@f1010000 {
 			resets = <&cpg 408>;
 		};
 
+		gpu: gpu@fd000000 {
+			compatible = "renesas,r8a77961-gpu",
+				     "img,img-gx6250",
+				     "img,img-rogue";
+			reg = <0 0xfd000000 0 0x40000>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 112>;
+			clock-names = "core";
+			power-domains = <&sysc R8A7796_PD_3DG_B>;
+			resets = <&cpg 112>;
+		};
+
 		pciec0: pcie@fe000000 {
 			compatible = "renesas,pcie-r8a77961",
 				     "renesas,pcie-rcar-gen3";
-- 
2.51.0

Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
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Re: [PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node

[Niklas Söderlund]

Hi Marek,

On 2025-10-13 21:01:18 +0200, Marek Vasut wrote:
> Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
> present in Renesas R-Car R8A77960 M3-W SoC.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Really cool seeing this.

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Frank Binns <frank.binns@imgtec.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Matt Coster <matt.coster@imgtec.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Simona Vetter <simona@ffwll.ch>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>  arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> index 6d039019905de..4f7b2e838c026 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> @@ -2565,6 +2565,18 @@ gic: interrupt-controller@f1010000 {
>  			resets = <&cpg 408>;
>  		};
>  
> +		gpu: gpu@fd000000 {
> +			compatible = "renesas,r8a77960-gpu",
> +				     "img,img-gx6250",
> +				     "img,img-rogue";
> +			reg = <0 0xfd000000 0 0x40000>;
> +			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 112>;
> +			clock-names = "core";
> +			power-domains = <&sysc R8A7796_PD_3DG_B>;
> +			resets = <&cpg 112>;
> +		};
> +
>  		pciec0: pcie@fe000000 {
>  			compatible = "renesas,pcie-r8a7796",
>  				     "renesas,pcie-rcar-gen3";
> -- 
> 2.51.0
> 
> 

-- 
Kind Regards,
Niklas Söderlund

Re: [PATCH 3/3] arm64: dts: renesas: r8a77961: Add GX6250 GPU node

[Niklas Söderlund]

Hi Marek,

Thanks for your work.

On 2025-10-13 21:01:19 +0200, Marek Vasut wrote:
> Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
> present in Renesas R-Car R8A77961 M3-W+ SoC.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Frank Binns <frank.binns@imgtec.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Matt Coster <matt.coster@imgtec.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Simona Vetter <simona@ffwll.ch>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>  arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> index 1637b534fc68b..77ed99e8d7b9e 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
> @@ -2445,6 +2445,18 @@ gic: interrupt-controller@f1010000 {
>  			resets = <&cpg 408>;
>  		};
>  
> +		gpu: gpu@fd000000 {
> +			compatible = "renesas,r8a77961-gpu",
> +				     "img,img-gx6250",
> +				     "img,img-rogue";
> +			reg = <0 0xfd000000 0 0x40000>;
> +			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 112>;
> +			clock-names = "core";
> +			power-domains = <&sysc R8A7796_PD_3DG_B>;
> +			resets = <&cpg 112>;
> +		};
> +
>  		pciec0: pcie@fe000000 {
>  			compatible = "renesas,pcie-r8a77961",
>  				     "renesas,pcie-rcar-gen3";
> -- 
> 2.51.0
> 
> 

-- 
Kind Regards,
Niklas Söderlund

Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Matt Coster]

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On 13/10/2025 20:01, Marek Vasut wrote:
> Document Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
> present in Renesas R-Car R8A77960 M3-W and R8A77961 M3-W+ SoC.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Frank Binns <frank.binns@imgtec.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Matt Coster <matt.coster@imgtec.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Simona Vetter <simona@ffwll.ch>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> See https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/13
> for related userspace bits.
> ---
>  .../devicetree/bindings/gpu/img,powervr-rogue.yaml          | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> index c87d7bece0ecd..c9680a2560114 100644
> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> @@ -13,6 +13,12 @@ maintainers:
>  properties:
>    compatible:
>      oneOf:
> +      - items:
> +          - enum:
> +              - renesas,r8a77960-gpu
> +              - renesas,r8a77961-gpu

I think this can just be renesas,r8a7796-gpu; most of the devices in the
dts for these SoCs appear to use the same pattern and the GPU is the
same in both.

> +          - const: img,img-gx6250
> +          - const: img,img-rogue
>        - items:
>            - enum:
>                - ti,am62-gpu

You also need to add img,img-gx6250 to the appropriate conditional
blocks below here for the number of power domains (in this case, 2) and
clocks (that's more complicated).

These older GPUs always require three clocks (core, mem and sys), but
it's not immediately clear from the Renesas TRM how these are hooked up.
I can see three "clocks" connected (fig 23.2 in my copy, clock details
from fig 8.1b):

 - Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would
   make it our "core" clock.
 - Clock S2D1φ: Appears to be a core clock used on the AXI bus, making
   it our "sys" clock.
 - MSTP ST112: Appears to be a whole module on/off control of some
   description, and definitely doesn't align with the missing "mem"
   clock.

Do you have any further insights as to how Renesas have wired things up?

Cheers,
Matt

-- 
Matt Coster
E: matt.coster@imgtec.com

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Re: [PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node

[Matt Coster]

[-- Attachment #1.1: Type: text/plain, Size: 2990 bytes --]

On 13/10/2025 20:01, Marek Vasut wrote:
> Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
> present in Renesas R-Car R8A77960 M3-W SoC.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Frank Binns <frank.binns@imgtec.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Matt Coster <matt.coster@imgtec.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Simona Vetter <simona@ffwll.ch>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
>  arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> index 6d039019905de..4f7b2e838c026 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> @@ -2565,6 +2565,18 @@ gic: interrupt-controller@f1010000 {
>  			resets = <&cpg 408>;
>  		};
>  
> +		gpu: gpu@fd000000 {
> +			compatible = "renesas,r8a77960-gpu",
> +				     "img,img-gx6250",
> +				     "img,img-rogue";
> +			reg = <0 0xfd000000 0 0x40000>;
> +			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 112>;
> +			clock-names = "core";
> +			power-domains = <&sysc R8A7796_PD_3DG_B>;

My comments here apply to the other dts patch (P3/3) as well since the
integration appears to be identical between the two SoCs.

There are two power domains on this GPU and the SoC exposes both of
them; no reason to fall back to the single-domain scheme here.

I know the sysc driver declares the dependency of _B on _A, but the dts
shouldn't rely on that, so can we have:

   power-domains = <&sysc R8A7796_PD_3DG_A>, <&sysc R8A7796_PD_3DG_B>;
   power-domain-names = "a", "b";

> +			resets = <&cpg 112>;

Is this a reset line? Is it a clock? I see this pattern used throughout
the Renesas dts, but I'm just thinking how this will interact with the
powervr driver. The reset line is optional since some hardware
integrations manage it for us during the power-up/down sequences, which
appears to be the case here with the MSTP control (from my brief dig
through the Renesas TRM).

Related, see my comments on the bindings patch (P1/3) about how clocks
are wired up in this SoC.

Cheers,
Matt

> +		};
> +
>  		pciec0: pcie@fe000000 {
>  			compatible = "renesas,pcie-r8a7796",
>  				     "renesas,pcie-rcar-gen3";

-- 
Matt Coster
E: matt.coster@imgtec.com

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Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Rob Herring (Arm)]

On Mon, 13 Oct 2025 21:01:17 +0200, Marek Vasut wrote:
> Document Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
> present in Renesas R-Car R8A77960 M3-W and R8A77961 M3-W+ SoC.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Frank Binns <frank.binns@imgtec.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Matt Coster <matt.coster@imgtec.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Simona Vetter <simona@ffwll.ch>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-renesas-soc@vger.kernel.org
> ---
> See https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/13
> for related userspace bits.
> ---
>  .../devicetree/bindings/gpu/img,powervr-rogue.yaml          | 6 ++++++
>  1 file changed, 6 insertions(+)
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/next-20251013 (exact match)
 Base: tags/next-20251013 (use --merge-base to override)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20251013190210.142436-1-marek.vasut+renesas@mailbox.org:

Lexical error: arch/arm64/boot/dts/renesas/r8a77961.dtsi:2456.27-43 Unexpected 'R8A7796_PD_3DG_B'
FATAL ERROR: Syntax error parsing input tree
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/renesas] Error 2
make[2]: Target 'arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: renesas/r8a77961-ulcb-kf.dtb] Error 2
Lexical error: arch/arm64/boot/dts/renesas/r8a77961.dtsi:2456.27-43 Unexpected 'R8A7796_PD_3DG_B'
FATAL ERROR: Syntax error parsing input tree
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/renesas] Error 2
make[2]: Target 'arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: renesas/r8a779m3-ulcb-kf.dtb] Error 2
Lexical error: arch/arm64/boot/dts/renesas/r8a77961.dtsi:2456.27-43 Unexpected 'R8A7796_PD_3DG_B'
FATAL ERROR: Syntax error parsing input tree
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/renesas] Error 2
make[2]: Target 'arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: renesas/r8a77961-salvator-xs.dtb] Error 2
Lexical error: arch/arm64/boot/dts/renesas/r8a77961.dtsi:2456.27-43 Unexpected 'R8A7796_PD_3DG_B'
FATAL ERROR: Syntax error parsing input tree
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/renesas/r8a77961-ulcb.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/renesas] Error 2
make[2]: Target 'arch/arm64/boot/dts/renesas/r8a77961-ulcb.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: renesas/r8a77961-ulcb.dtb] Error 2
Lexical error: arch/arm64/boot/dts/renesas/r8a77961.dtsi:2456.27-43 Unexpected 'R8A7796_PD_3DG_B'
FATAL ERROR: Syntax error parsing input tree
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/renesas] Error 2
make[2]: Target 'arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: renesas/r8a779m3-ulcb.dtb] Error 2
Lexical error: arch/arm64/boot/dts/renesas/r8a77961.dtsi:2456.27-43 Unexpected 'R8A7796_PD_3DG_B'
FATAL ERROR: Syntax error parsing input tree
make[3]: *** [scripts/Makefile.dtbs:132: arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dtb] Error 1
make[2]: *** [scripts/Makefile.build:556: arch/arm64/boot/dts/renesas] Error 2
make[2]: Target 'arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dtb' not remade because of errors.
make[1]: *** [/home/rob/proj/linux-dt-testing/Makefile:1478: renesas/r8a779m3-salvator-xs.dtb] Error 2
make: *** [Makefile:248: __sub-make] Error 2
make: Target 'renesas/r9a07g044c2-smarc.dtb' not remade because of errors.
make: Target 'renesas/r8a77961-ulcb-kf.dtb' not remade because of errors.
make: Target 'renesas/r8a77965-ulcb.dtb' not remade because of errors.
make: Target 'renesas/r8a77965-ulcb-kf.dtb' not remade because of errors.
make: Target 'renesas/r8a779m1-ulcb.dtb' not remade because of errors.
make: Target 'renesas/r8a774c0-ek874.dtb' not remade because of errors.
make: Target 'renesas/r8a774c0-ek874-idk-2121wr.dtb' not remade because of errors.
make: Target 'renesas/r9a09g077m44-rzt2h-evk.dtb' not remade because of errors.
make: Target 'renesas/r8a77960-ulcb-kf.dtb' not remade because of errors.
make: Target 'renesas/r8a77980a-condor-i.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-hihope-rzg2m-rev2.dtb' not remade because of errors.
make: Target 'renesas/r8a779g0-white-hawk.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-hihope-rzg2n-rev2-ex.dtb' not remade because of errors.
make: Target 'renesas/r8a779g2-white-hawk-single.dtb' not remade because of errors.
make: Target 'renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb' not remade because of errors.
make: Target 'renesas/r9a07g044l2-remi-pi.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb' not remade because of errors.
make: Target 'renesas/r8a774c0-ek874-mipi-2.1.dtb' not remade because of errors.
make: Target 'renesas/r9a07g044l2-smarc.dtb' not remade because of errors.
make: Target 'renesas/r9a09g056n48-rzv2n-evk.dtb' not remade because of errors.
make: Target 'renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb' not remade because of errors.
make: Target 'renesas/r8a779m5-salvator-xs.dtb' not remade because of errors.
make: Target 'renesas/r8a77970-eagle.dtb' not remade because of errors.
make: Target 'renesas/r8a77980-v3hsk.dtb' not remade because of errors.
make: Target 'renesas/r8a77951-salvator-xs.dtb' not remade because of errors.
make: Target 'renesas/r8a77951-ulcb-kf.dtb' not remade because of errors.
make: Target 'renesas/r8a77965-salvator-xs.dtb' not remade because of errors.
make: Target 'renesas/r9a09g057h48-kakip.dtb' not remade because of errors.
make: Target 'renesas/r8a779f4-s4sk.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-hihope-rzg2n-ex.dtb' not remade because of errors.
make: Target 'renesas/r8a779h0-gray-hawk-single.dtb' not remade because of errors.
make: Target 'renesas/r8a774c0-cat874.dtb' not remade because of errors.
make: Target 'renesas/r8a77960-ulcb.dtb' not remade because of errors.
make: Target 'renesas/r8a77951-ulcb.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb' not remade because of errors.
make: Target 'renesas/r8a774e1-beacon-rzg2h-kit.dtb' not remade because of errors.
make: Target 'renesas/r9a09g087m44-rzn2h-evk.dtb' not remade because of errors.
make: Target 'renesas/r8a779m1-ulcb-kf.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-hihope-rzg2n-rev2.dtb' not remade because of errors.
make: Target 'renesas/r8a77970-v3msk.dtb' not remade because of errors.
make: Target 'renesas/r8a779m1-salvator-xs.dtb' not remade because of errors.
make: Target 'renesas/r8a779m3-ulcb-kf.dtb' not remade because of errors.
make: Target 'renesas/r9a09g047e57-smarc.dtb' not remade because of errors.
make: Target 'renesas/r9a08g045s33-smarc.dtb' not remade because of errors.
make: Target 'renesas/r8a77961-salvator-xs.dtb' not remade because of errors.
make: Target 'renesas/r8a77960-salvator-xs.dtb' not remade because of errors.
make: Target 'renesas/r8a77960-salvator-x.dtb' not remade because of errors.
make: Target 'renesas/r8a77990-ebisu.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb' not remade because of errors.
make: Target 'renesas/r8a77980-condor.dtb' not remade because of errors.
make: Target 'renesas/r9a07g054l2-smarc.dtb' not remade because of errors.
make: Target 'renesas/r8a779g3-white-hawk-single.dtb' not remade because of errors.
make: Target 'renesas/r8a779f0-spider.dtb' not remade because of errors.
make: Target 'renesas/r8a774e1-hihope-rzg2h-ex.dtb' not remade because of errors.
make: Target 'renesas/r8a779a0-falcon.dtb' not remade because of errors.
make: Target 'renesas/r8a77965-salvator-x.dtb' not remade because of errors.
make: Target 'renesas/r8a774e1-hihope-rzg2h.dtb' not remade because of errors.
make: Target 'renesas/r8a77951-salvator-x.dtb' not remade because of errors.
make: Target 'renesas/r9a09g011-v2mevk2.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-hihope-rzg2n.dtb' not remade because of errors.
make: Target 'renesas/r8a774b1-beacon-rzg2n-kit.dtb' not remade because of errors.
make: Target 'renesas/r9a09g057h44-rzv2h-evk.dtb' not remade because of errors.
make: Target 'renesas/r8a77961-ulcb.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-hihope-rzg2m.dtb' not remade because of errors.
make: Target 'renesas/r8a779h2-gray-hawk-single.dtb' not remade because of errors.
make: Target 'renesas/r8a77995-draak.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-hihope-rzg2m-ex.dtb' not remade because of errors.
make: Target 'renesas/r8a779m3-ulcb.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb' not remade because of errors.
make: Target 'renesas/r8a779m3-salvator-xs.dtb' not remade because of errors.
make: Target 'renesas/r9a07g043u11-smarc.dtb' not remade because of errors.
make: Target 'renesas/r8a779g3-sparrow-hawk.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-beacon-rzg2m-kit.dtb' not remade because of errors.
make: Target 'renesas/r8a774a1-hihope-rzg2m-rev2-ex.dtb' not remade because of errors.
make: Target 'renesas/r8a779g0-white-hawk-cpu.dtb' not remade because of errors.

Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Marek Vasut]

On 10/14/25 1:52 PM, Matt Coster wrote:

Hello Matt,

>> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>> index c87d7bece0ecd..c9680a2560114 100644
>> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>> @@ -13,6 +13,12 @@ maintainers:
>>   properties:
>>     compatible:
>>       oneOf:
>> +      - items:
>> +          - enum:
>> +              - renesas,r8a77960-gpu
>> +              - renesas,r8a77961-gpu
> 
> I think this can just be renesas,r8a7796-gpu; most of the devices in the
> dts for these SoCs appear to use the same pattern and the GPU is the
> same in both.

Not really, the 77960 and 77961 are different SoCs, that is why they 
each have different specific compatible. Of course, most drivers match 
on fallback compatible, since the IPs are mostly identical, see this:

$ git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77961.dtsi
arch/arm64/boot/dts/renesas/r8a77961.dtsi:      compatible = 
"renesas,r8a77961";
arch/arm64/boot/dts/renesas/r8a77961.dtsi: 
compatible = "renesas,r8a77961-wdt",
arch/arm64/boot/dts/renesas/r8a77961.dtsi: 
compatible = "renesas,gpio-r8a77961",
...

$  git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77960.dtsi
arch/arm64/boot/dts/renesas/r8a77960.dtsi:      compatible = 
"renesas,r8a7796";
arch/arm64/boot/dts/renesas/r8a77960.dtsi: 
compatible = "renesas,r8a7796-wdt",
arch/arm64/boot/dts/renesas/r8a77960.dtsi: 
compatible = "renesas,gpio-r8a7796",
arch/arm64/boot/dts/renesas/r8a77960.dtsi: 
compatible = "renesas,gpio-r8a7796",

I can turn the first entry into renesas,r8a7796-gpu to be consistent 
with the legacy 7796 name for 77960.

Geert ?

>> +          - const: img,img-gx6250
>> +          - const: img,img-rogue
>>         - items:
>>             - enum:
>>                 - ti,am62-gpu
> 
> You also need to add img,img-gx6250 to the appropriate conditional
> blocks below here for the number of power domains (in this case, 2) and
> clocks (that's more complicated).
> 
> These older GPUs always require three clocks (core, mem and sys), but
> it's not immediately clear from the Renesas TRM how these are hooked up.
> I can see three "clocks" connected (fig 23.2 in my copy, clock details
> from fig 8.1b):

Which revision of the RM is that ? There should be some Rev.M.NP at the 
bottom of each page.

>   - Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would
>     make it our "core" clock.

This should be 600-700 MHz clock on M3-W , so that sounds like a GPU 
core clock.

>   - Clock S2D1φ: Appears to be a core clock used on the AXI bus, making
>     it our "sys" clock.

This should be 400 MHz AXI clock, but wouldn't that make it "mem" clock 
? I think this might be the clock which drives the AXI bus, used by the 
GPU to access data in DRAM ?

>   - MSTP ST112: Appears to be a whole module on/off control of some
>     description, and definitely doesn't align with the missing "mem"
>     clock.

Maybe this is the "sys" clock, since it toggles the register interface 
clock on/off ?

> Do you have any further insights as to how Renesas have wired things up?

Please see above, maybe that helps a bit ?

-- 
Best regards,
Marek Vasut

Re: [PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node

[Marek Vasut]

On 10/14/25 1:52 PM, Matt Coster wrote:

Hello Matt,

>> +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
>> @@ -2565,6 +2565,18 @@ gic: interrupt-controller@f1010000 {
>>   			resets = <&cpg 408>;
>>   		};
>>   
>> +		gpu: gpu@fd000000 {
>> +			compatible = "renesas,r8a77960-gpu",
>> +				     "img,img-gx6250",
>> +				     "img,img-rogue";
>> +			reg = <0 0xfd000000 0 0x40000>;
>> +			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&cpg CPG_MOD 112>;
>> +			clock-names = "core";
>> +			power-domains = <&sysc R8A7796_PD_3DG_B>;
> 
> My comments here apply to the other dts patch (P3/3) as well since the
> integration appears to be identical between the two SoCs.
> 
> There are two power domains on this GPU and the SoC exposes both of
> them; no reason to fall back to the single-domain scheme here.
> 
> I know the sysc driver declares the dependency of _B on _A, but the dts
> shouldn't rely on that, so can we have:
> 
>     power-domains = <&sysc R8A7796_PD_3DG_A>, <&sysc R8A7796_PD_3DG_B>;
>     power-domain-names = "a", "b";

Both SoCs fixed in V2 , which I will post in a few days , thanks !

>> +			resets = <&cpg 112>;
> 
> Is this a reset line? Is it a clock?

This is a reset line. The MSTP controls both clocks and resets, but this 
particular phandle describes reset control.

> I see this pattern used throughout
> the Renesas dts, but I'm just thinking how this will interact with the
> powervr driver. The reset line is optional since some hardware
> integrations manage it for us during the power-up/down sequences, which
> appears to be the case here with the MSTP control (from my brief dig
> through the Renesas TRM).

As far as I can tell, the pvr_power.c toggles the IP reset after the IP 
clock were already enabled, so the IP should be correctly reset. What 
kind of problem do you expect ?

> Related, see my comments on the bindings patch (P1/3) about how clocks
> are wired up in this SoC.
I tried to reply to that one, hopefully it makes some sense.

Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Geert Uytterhoeven]

Hi Marek,

On Wed, 15 Oct 2025 at 00:48, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 10/14/25 1:52 PM, Matt Coster wrote:
> >> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> >> index c87d7bece0ecd..c9680a2560114 100644
> >> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> >> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> >> @@ -13,6 +13,12 @@ maintainers:
> >>   properties:
> >>     compatible:
> >>       oneOf:
> >> +      - items:
> >> +          - enum:
> >> +              - renesas,r8a77960-gpu
> >> +              - renesas,r8a77961-gpu
> >
> > I think this can just be renesas,r8a7796-gpu; most of the devices in the
> > dts for these SoCs appear to use the same pattern and the GPU is the
> > same in both.
>
> Not really, the 77960 and 77961 are different SoCs, that is why they
> each have different specific compatible. Of course, most drivers match
> on fallback compatible, since the IPs are mostly identical, see this:
>
> $ git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77961.dtsi
> arch/arm64/boot/dts/renesas/r8a77961.dtsi:      compatible =
> "renesas,r8a77961";
> arch/arm64/boot/dts/renesas/r8a77961.dtsi:
> compatible = "renesas,r8a77961-wdt",
> arch/arm64/boot/dts/renesas/r8a77961.dtsi:
> compatible = "renesas,gpio-r8a77961",
> ...
>
> $  git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77960.dtsi
> arch/arm64/boot/dts/renesas/r8a77960.dtsi:      compatible =
> "renesas,r8a7796";
> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
> compatible = "renesas,r8a7796-wdt",
> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
> compatible = "renesas,gpio-r8a7796",
> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
> compatible = "renesas,gpio-r8a7796",
>
> I can turn the first entry into renesas,r8a7796-gpu to be consistent
> with the legacy 7796 name for 77960.
>
> Geert ?

Please use "renesas,r8a7796-gpu" for R-Car M3-W, and
"renesas,r8a77961-gpu" for R-Car M3-W+.

> >> +          - const: img,img-gx6250
> >> +          - const: img,img-rogue
> >>         - items:
> >>             - enum:
> >>                 - ti,am62-gpu
> >
> > You also need to add img,img-gx6250 to the appropriate conditional
> > blocks below here for the number of power domains (in this case, 2) and
> > clocks (that's more complicated).
> >
> > These older GPUs always require three clocks (core, mem and sys), but
> > it's not immediately clear from the Renesas TRM how these are hooked up.
> > I can see three "clocks" connected (fig 23.2 in my copy, clock details
> > from fig 8.1b):
>
> Which revision of the RM is that ? There should be some Rev.M.NP at the
> bottom of each page.

Rev.2.40.

> >   - Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would
> >     make it our "core" clock.
>
> This should be 600-700 MHz clock on M3-W , so that sounds like a GPU
> core clock.

Agreed.

>
> >   - Clock S2D1φ: Appears to be a core clock used on the AXI bus, making
> >     it our "sys" clock.
>
> This should be 400 MHz AXI clock, but wouldn't that make it "mem" clock
> ? I think this might be the clock which drives the AXI bus, used by the
> GPU to access data in DRAM ?

Agreed.

> >   - MSTP ST112: Appears to be a whole module on/off control of some
> >     description, and definitely doesn't align with the missing "mem"
> >     clock.
>
> Maybe this is the "sys" clock, since it toggles the register interface
> clock on/off ?

Probably.

Note that both ZGφ and S2D1φ are always-on.
MSTP ST112 is the only gateable clock, and it is controlled through
the PM Domain and Runtime PM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Matt Coster]

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Hi Geert, Marek:

On 15/10/2025 10:10, Geert Uytterhoeven wrote:
> Hi Marek,
> 
> On Wed, 15 Oct 2025 at 00:48, Marek Vasut <marek.vasut@mailbox.org> wrote:
>> On 10/14/25 1:52 PM, Matt Coster wrote:
>>>> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> index c87d7bece0ecd..c9680a2560114 100644
>>>> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
>>>> @@ -13,6 +13,12 @@ maintainers:
>>>>   properties:
>>>>     compatible:
>>>>       oneOf:
>>>> +      - items:
>>>> +          - enum:
>>>> +              - renesas,r8a77960-gpu
>>>> +              - renesas,r8a77961-gpu
>>>
>>> I think this can just be renesas,r8a7796-gpu; most of the devices in the
>>> dts for these SoCs appear to use the same pattern and the GPU is the
>>> same in both.
>>
>> Not really, the 77960 and 77961 are different SoCs, that is why they
>> each have different specific compatible. Of course, most drivers match
>> on fallback compatible, since the IPs are mostly identical, see this:
>>
>> $ git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77961.dtsi
>> arch/arm64/boot/dts/renesas/r8a77961.dtsi:      compatible =
>> "renesas,r8a77961";
>> arch/arm64/boot/dts/renesas/r8a77961.dtsi:
>> compatible = "renesas,r8a77961-wdt",
>> arch/arm64/boot/dts/renesas/r8a77961.dtsi:
>> compatible = "renesas,gpio-r8a77961",
>> ...
>>
>> $  git grep compatible.*7796 arch/arm64/boot/dts/renesas/r8a77960.dtsi
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:      compatible =
>> "renesas,r8a7796";
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
>> compatible = "renesas,r8a7796-wdt",
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
>> compatible = "renesas,gpio-r8a7796",
>> arch/arm64/boot/dts/renesas/r8a77960.dtsi:
>> compatible = "renesas,gpio-r8a7796",
>>
>> I can turn the first entry into renesas,r8a7796-gpu to be consistent
>> with the legacy 7796 name for 77960.
>>
>> Geert ?
> 
> Please use "renesas,r8a7796-gpu" for R-Car M3-W, and
> "renesas,r8a77961-gpu" for R-Car M3-W+.

Works for me. I mistook the non-0 version as a generic name for both,
not realising it was just a legacy thing. My bad!

> 
>>>> +          - const: img,img-gx6250
>>>> +          - const: img,img-rogue
>>>>         - items:
>>>>             - enum:
>>>>                 - ti,am62-gpu
>>>
>>> You also need to add img,img-gx6250 to the appropriate conditional
>>> blocks below here for the number of power domains (in this case, 2) and
>>> clocks (that's more complicated).
>>>
>>> These older GPUs always require three clocks (core, mem and sys), but
>>> it's not immediately clear from the Renesas TRM how these are hooked up.
>>> I can see three "clocks" connected (fig 23.2 in my copy, clock details
>>> from fig 8.1b):
>>
>> Which revision of the RM is that ? There should be some Rev.M.NP at the
>> bottom of each page.
> 
> Rev.2.40.

Yes, that's the version I have too.

> 
>>>   - Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would
>>>     make it our "core" clock.
>>
>> This should be 600-700 MHz clock on M3-W , so that sounds like a GPU
>> core clock.
> 
> Agreed.
> 
>>
>>>   - Clock S2D1φ: Appears to be a core clock used on the AXI bus, making
>>>     it our "sys" clock.
>>
>> This should be 400 MHz AXI clock, but wouldn't that make it "mem" clock
>> ? I think this might be the clock which drives the AXI bus, used by the
>> GPU to access data in DRAM ?
> 
> Agreed.
> 
>>>   - MSTP ST112: Appears to be a whole module on/off control of some
>>>     description, and definitely doesn't align with the missing "mem"
>>>     clock.
>>
>> Maybe this is the "sys" clock, since it toggles the register interface
>> clock on/off ?
> 
> Probably.

Yes, this is probably correct. I got my AXI interfaces mixed up – we
have both a manager interface for accessing memory (using the mem clock)
and a subordinate interface to expose to our registers (using the sys
clock). Here's the summary table from our system integration document:

   +-------+-------------------------+------------------------+
   | Clock | Modules Clocked         | Dependencies           |
   +-------+-------------------------+------------------------+
   | mem   | SLC / AXI Manager       | Run for all operations |
   | sys   | SOCIF / AXI Subordinate | Run for all operations |
   | core  | All                     | Run for all operations |
   +-------+-------------------------+------------------------+

Cheers,
Matt

> 
> Note that both ZGφ and S2D1φ are always-on.
> MSTP ST112 is the only gateable clock, and it is controlled through
> the PM Domain and Runtime PM.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

-- 
Matt Coster
E: matt.coster@imgtec.com

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Re: [PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node

[Matt Coster]

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Hi Marek,

On 14/10/2025 23:59, Marek Vasut wrote:
> On 10/14/25 1:52 PM, Matt Coster wrote:
> 
> Hello Matt,
> 
>>> +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
>>> @@ -2565,6 +2565,18 @@ gic: interrupt-controller@f1010000 {
>>>               resets = <&cpg 408>;
>>>           };
>>>   +        gpu: gpu@fd000000 {
>>> +            compatible = "renesas,r8a77960-gpu",
>>> +                     "img,img-gx6250",
>>> +                     "img,img-rogue";
>>> +            reg = <0 0xfd000000 0 0x40000>;
>>> +            interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
>>> +            clocks = <&cpg CPG_MOD 112>;
>>> +            clock-names = "core";
>>> +            power-domains = <&sysc R8A7796_PD_3DG_B>;
>>
>> My comments here apply to the other dts patch (P3/3) as well since the
>> integration appears to be identical between the two SoCs.
>>
>> There are two power domains on this GPU and the SoC exposes both of
>> them; no reason to fall back to the single-domain scheme here.
>>
>> I know the sysc driver declares the dependency of _B on _A, but the dts
>> shouldn't rely on that, so can we have:
>>
>>     power-domains = <&sysc R8A7796_PD_3DG_A>, <&sysc R8A7796_PD_3DG_B>;
>>     power-domain-names = "a", "b";
> 
> Both SoCs fixed in V2 , which I will post in a few days , thanks !
> 
>>> +            resets = <&cpg 112>;
>>
>> Is this a reset line? Is it a clock?
> 
> This is a reset line. The MSTP controls both clocks and resets, but
> this particular phandle describes reset control.

Ack

> 
>> I see this pattern used throughout
>> the Renesas dts, but I'm just thinking how this will interact with the
>> powervr driver. The reset line is optional since some hardware
>> integrations manage it for us during the power-up/down sequences, which
>> appears to be the case here with the MSTP control (from my brief dig
>> through the Renesas TRM).
> 
> As far as I can tell, the pvr_power.c toggles the IP reset after the
> IP clock were already enabled, so the IP should be correctly reset.
> What kind of problem do you expect ?

I think I'm just being paranoid about the weirdness (to me at least) of
having one device be treated as both clock and reset line. Assuming this
is tested as working, I'm okay with it, especially as it seems to be the
norm for Renesas.

> 
>> Related, see my comments on the bindings patch (P1/3) about how clocks
>> are wired up in this SoC.
> I tried to reply to that one, hopefully it makes some sense.

Looks like we've figured it out there, thanks for your comments!

Cheers,
Matt


-- 
Matt Coster
E: matt.coster@imgtec.com

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Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Marek Vasut]

On 10/15/25 11:10 AM, Geert Uytterhoeven wrote:

Hello Geert,

>> I can turn the first entry into renesas,r8a7796-gpu to be consistent
>> with the legacy 7796 name for 77960.
>>
>> Geert ?
> 
> Please use "renesas,r8a7796-gpu" for R-Car M3-W, and
> "renesas,r8a77961-gpu" for R-Car M3-W+.

Will do.

[...]

-- 
Best regards,
Marek Vasut

Re: [PATCH 1/3] dt-bindings: gpu: img,powervr-rogue: Document GX6250 GPU in Renesas R-Car M3-W/M3-W+

[Marek Vasut]

On 10/15/25 12:52 PM, Matt Coster wrote:

Hello Matt,

>>>>    - Clock ZGφ: Appears to be a core clock for the GPU (3DGE). That would
>>>>      make it our "core" clock.
>>>
>>> This should be 600-700 MHz clock on M3-W , so that sounds like a GPU
>>> core clock.
>>
>> Agreed.
>>
>>>
>>>>    - Clock S2D1φ: Appears to be a core clock used on the AXI bus, making
>>>>      it our "sys" clock.
>>>
>>> This should be 400 MHz AXI clock, but wouldn't that make it "mem" clock
>>> ? I think this might be the clock which drives the AXI bus, used by the
>>> GPU to access data in DRAM ?
>>
>> Agreed.
>>
>>>>    - MSTP ST112: Appears to be a whole module on/off control of some
>>>>      description, and definitely doesn't align with the missing "mem"
>>>>      clock.
>>>
>>> Maybe this is the "sys" clock, since it toggles the register interface
>>> clock on/off ?
>>
>> Probably.
> 
> Yes, this is probably correct. I got my AXI interfaces mixed up – we
> have both a manager interface for accessing memory (using the mem clock)
> and a subordinate interface to expose to our registers (using the sys
> clock). Here's the summary table from our system integration document:
> 
>     +-------+-------------------------+------------------------+
>     | Clock | Modules Clocked         | Dependencies           |
>     +-------+-------------------------+------------------------+
>     | mem   | SLC / AXI Manager       | Run for all operations |
>     | sys   | SOCIF / AXI Subordinate | Run for all operations |
>     | core  | All                     | Run for all operations |
>     +-------+-------------------------+------------------------+

Thank you for sharing that. I will send a V2 series shortly.

-- 
Best regards,
Marek Vasut

Re: [PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node

[Marek Vasut]

On 10/15/25 12:55 PM, Matt Coster wrote:

Hello Matt,

>>> I see this pattern used throughout
>>> the Renesas dts, but I'm just thinking how this will interact with the
>>> powervr driver. The reset line is optional since some hardware
>>> integrations manage it for us during the power-up/down sequences, which
>>> appears to be the case here with the MSTP control (from my brief dig
>>> through the Renesas TRM).
>>
>> As far as I can tell, the pvr_power.c toggles the IP reset after the
>> IP clock were already enabled, so the IP should be correctly reset.
>> What kind of problem do you expect ?
> 
> I think I'm just being paranoid about the weirdness (to me at least) of
> having one device be treated as both clock and reset line. Assuming this
> is tested as working, I'm okay with it, especially as it seems to be the
> norm for Renesas.

The combined clock/reset IP is not limited to renesas SoCs, there are 
other SoCs which do the same thing (Allwinner "ccu", Marvell PXA 
"soc_clocks" , nVidia Tegra "car", Qualcomm "gcc", Rockchip "cru", to 
name a few). Usually the registers which control clock and resets are 
shared in the same IP, but they control different (possibly related) 
signals in the SoC.

>>> Related, see my comments on the bindings patch (P1/3) about how clocks
>>> are wired up in this SoC.
>> I tried to reply to that one, hopefully it makes some sense.
> 
> Looks like we've figured it out there, thanks for your comments!

Likewise, thank you for sharing the clocking details.

-- 
Best regards,
Marek Vasut