* [PATCH v3 1/3] dt-bindings: display/msm: Add SM6150 DisplayPort controller
2025-10-14 11:54 [PATCH v3 0/3] Add DisplayPort support to QCS615 devicetree Xiangxu Yin via B4 Relay
@ 2025-10-14 11:54 ` Xiangxu Yin via B4 Relay
2025-10-14 11:54 ` [PATCH v3 2/3] arm64: dts: qcom: Add DisplayPort and QMP USB3DP PHY for SM6150 Xiangxu Yin via B4 Relay
2025-10-14 11:54 ` [PATCH v3 3/3] arm64: dts: qcom: qcs615-ride: Enable DisplayPort Xiangxu Yin via B4 Relay
2 siblings, 0 replies; 6+ messages in thread
From: Xiangxu Yin via B4 Relay @ 2025-10-14 11:54 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
fange.zhang, yongxing.mou, li.liu, Xiangxu Yin
From: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Describe the DisplayPort controller for Qualcomm SM6150 SoC.
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
---
.../devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
index 9ac24f99d3ada1c197c9654dc9babebccae972ed..935eca23ce6b30b81b3ad778e5fcacc817a230c3 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml
@@ -51,6 +51,16 @@ patternProperties:
compatible:
const: qcom,sm6150-dpu
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6150-dp
+ - const: qcom,sm8150-dp
+ - const: qcom,sm8350-dp
+
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
@@ -132,6 +142,7 @@ examples:
port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 2/3] arm64: dts: qcom: Add DisplayPort and QMP USB3DP PHY for SM6150
2025-10-14 11:54 [PATCH v3 0/3] Add DisplayPort support to QCS615 devicetree Xiangxu Yin via B4 Relay
2025-10-14 11:54 ` [PATCH v3 1/3] dt-bindings: display/msm: Add SM6150 DisplayPort controller Xiangxu Yin via B4 Relay
@ 2025-10-14 11:54 ` Xiangxu Yin via B4 Relay
2025-10-14 11:54 ` [PATCH v3 3/3] arm64: dts: qcom: qcs615-ride: Enable DisplayPort Xiangxu Yin via B4 Relay
2 siblings, 0 replies; 6+ messages in thread
From: Xiangxu Yin via B4 Relay @ 2025-10-14 11:54 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
fange.zhang, yongxing.mou, li.liu, Xiangxu Yin
From: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Introduce DisplayPort controller node and associated QMP USB3-DP PHY
for SM6150 SoC. Update clock and endpoint connections to enable DP
integration.
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm6150.dtsi | 113 ++++++++++++++++++++++++++++++++++-
1 file changed, 111 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index 6128d8c48f9c0807ac488ddac3b2377678e8f8c3..36a536cef99a095938f3e18a9b5e7825308ca426 100644
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -17,6 +17,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
/ {
interrupt-parent = <&intc>;
@@ -3717,6 +3718,7 @@ port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
};
};
@@ -3749,6 +3751,87 @@ opp-307200000 {
};
};
+ mdss_dp0: displayport-controller@ae90000 {
+ compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp";
+
+ reg = <0x0 0x0ae90000 0x0 0x200>,
+ <0x0 0x0ae90200 0x0 0x200>,
+ <0x0 0x0ae90400 0x0 0x600>,
+ <0x0 0x0ae90a00 0x0 0x600>,
+ <0x0 0x0ae91000 0x0 0x600>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dp0_out: endpoint {
+ data-lanes = <3 2 0 1>;
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x0ae94000 0x0 0x400>;
@@ -3844,8 +3927,8 @@ dispcc: clock-controller@af00000 {
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<0>,
- <0>,
- <0>;
+ <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -4214,6 +4297,32 @@ usb_qmpphy: phy@88e6000 {
status = "disabled";
};
+ usb_qmpphy_2: phy@88e8000 {
+ compatible = "qcom,qcs615-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e8000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+ <&gcc GCC_AHB2PHY_WEST_CLK>,
+ <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
+ <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
+ reset-names = "phy_phy",
+ "dp_phy";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>;
+
+ status = "disabled";
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
reg = <0x0 0x0a6f8800 0x0 0x400>;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 3/3] arm64: dts: qcom: qcs615-ride: Enable DisplayPort
2025-10-14 11:54 [PATCH v3 0/3] Add DisplayPort support to QCS615 devicetree Xiangxu Yin via B4 Relay
2025-10-14 11:54 ` [PATCH v3 1/3] dt-bindings: display/msm: Add SM6150 DisplayPort controller Xiangxu Yin via B4 Relay
2025-10-14 11:54 ` [PATCH v3 2/3] arm64: dts: qcom: Add DisplayPort and QMP USB3DP PHY for SM6150 Xiangxu Yin via B4 Relay
@ 2025-10-14 11:54 ` Xiangxu Yin via B4 Relay
2025-10-14 22:16 ` Dmitry Baryshkov
2 siblings, 1 reply; 6+ messages in thread
From: Xiangxu Yin via B4 Relay @ 2025-10-14 11:54 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
fange.zhang, yongxing.mou, li.liu, Xiangxu Yin
From: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Add DP connector node and configure MDSS DisplayPort controller for
QCS615 Ride platform. Include lane mapping and PHY supply settings
to support DP output.
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 9ac1dd3483b56f9d1652f8a38f62d759efa92b6a..bb0f4b8265e4807e50d067aed8b21557d97b20dd 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -39,6 +39,20 @@ xo_board_clk: xo-board-clk {
};
};
+ dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "mini";
+
+ hpd-gpios = <&io_expander 8 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
+ };
+ };
+ };
+
dp-dsi0-connector {
compatible = "dp-connector";
label = "DSI0";
@@ -423,6 +437,15 @@ &mdss {
status = "okay";
};
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>;
+ remote-endpoint = <&dp0_connector_in>;
+};
+
&mdss_dsi0 {
vdda-supply = <&vreg_l11a>;
status = "okay";
@@ -623,6 +646,13 @@ &usb_qmpphy {
status = "okay";
};
+&usb_qmpphy_2 {
+ vdda-phy-supply = <&vreg_l5a>;
+ vdda-pll-supply = <&vreg_l12a>;
+
+ status = "okay";
+};
+
&usb_1 {
status = "okay";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread