From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A2952FD7D2; Tue, 14 Oct 2025 15:14:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760454846; cv=pass; b=ICDvZknkE8DVZWvftRHfiZfVhm+9s8dph12frj6SkvhfAAjtSdzFfHLCFRMqJsNx9rJdhTyokZePIEiq/HDbI2G/eOQ4CBufYDiK1zpXu6WlCOT5xQtj2+HPAsSdFIuCibKmPoYlJJCbykUgSvdzIhMc8FkdIYCLIJz4Rq2r64g= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760454846; c=relaxed/simple; bh=f97ySkmH27TQZ5dnuAar65600J4WxMEGon4F5OUmPw0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mrZDAm3Ld8W7O1BLqXGLgd2y0IsmFlutbVg17nMGS9dvXwmkoJjMMGZ0HyOq41rdIlI4im+tku4w6GMJQY4NrRBlgQ1MpYRVNERMLY/T8S8mWQbF7J0EcV+cZpu98NliqAeEvMDZzKjL/O/P81OCuRXomfdD1hjJLRWbs2TtNBM= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=Iku4pBRO; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="Iku4pBRO" ARC-Seal: i=1; a=rsa-sha256; t=1760454646; cv=none; d=zohomail.com; s=zohoarc; b=KMACuvpQzCefnrI3b1YfrnL+lK+MEgP3Cq03wKR81NLcBZQ2ReaMHtGI2NaGGp0C01f9dyP9xs1OlAehWuZ7jSXxoZNBekMxj/NEzHJ8C7aRgYi3Q8yPJX5CCrM+csgd9rWUu60STVPB1yYyJOYtEIiGjIig1dcvDQM3tRSTndM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1760454646; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=ELRxhcckH/K4X4xPLZVCnB+NvfeZkGFUnfudFxrDDVs=; b=JaYWzaYsnpFb47EMfzR91c52eKAPOCgVVzOUXvwkrmOUAfcQAjss4IyTvK4CVR0GQuHNyGvI7nduXteB6efMe7pLSx03lHjI37xnIIu66xn+WLvO5G4YhWSliz4PZDtWLJIrbIo6HF2pKAnBdHx9CfIwElt9tQlHoOSnwxiDiKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1760454646; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=ELRxhcckH/K4X4xPLZVCnB+NvfeZkGFUnfudFxrDDVs=; b=Iku4pBROLwirKXBOAcGAIsS9GZLRz1kRnghtJyFLHXv/OtdZp9+CyhuT5C/LDtog bLrmF1j+3laSyrh7FWo+dAIjF0j2VVM4YrHdgVWCjpcwUN/Hy3JyXcrF0nHlnGaRuMn dpFv8uOGcCvtTrvdr4yP+JhL59lzkvof4Cu64PNc= Received: by mx.zohomail.com with SMTPS id 1760454644892798.4521273218037; Tue, 14 Oct 2025 08:10:44 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 14 Oct 2025 17:10:08 +0200 Subject: [PATCH 4/5] phy: mediatek: ufs: Add support for resets Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251014-mt8196-ufs-v1-4-195dceb83bc8@collabora.com> References: <20251014-mt8196-ufs-v1-0-195dceb83bc8@collabora.com> In-Reply-To: <20251014-mt8196-ufs-v1-0-195dceb83bc8@collabora.com> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Stanley Chu , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Peter Wang , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel Cc: Louis-Alexis Eyraud , kernel@collabora.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The MediaTek UFS PHY supports PHY resets. Until now, they've been implemented in the UFS host driver. Since they were never documented in the UFS HCI node's DT bindings, and no mainline DT uses it, it's fine if it's moved to the correct location, which is the PHY driver. Implement the MPHY reset logic in this driver and expose it through the phy subsystem's reset op. The reset itself is optional, as judging by other mainline devices that use this hardware, it's not required for the device to function. If no reset is present, the reset op returns -EOPNOTSUPP, which means that the ufshci driver can detect it's present and not double sleep in its own reset function, where it will call the phy reset. Signed-off-by: Nicolas Frattaroli --- drivers/phy/mediatek/phy-mtk-ufs.c | 71 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c index 0cb5a25b1b7a..d77ba689ebc8 100644 --- a/drivers/phy/mediatek/phy-mtk-ufs.c +++ b/drivers/phy/mediatek/phy-mtk-ufs.c @@ -4,6 +4,7 @@ * Author: Stanley Chu */ +#include #include #include #include @@ -11,6 +12,8 @@ #include #include #include +#include +#include #include "phy-mtk-io.h" @@ -36,9 +39,17 @@ #define UFSPHY_CLKS_CNT 2 +#define UFS_MTK_SIP_MPHY_CTRL BIT(8) + +enum ufs_mtk_mphy_op { + UFS_MPHY_BACKUP = 0, + UFS_MPHY_RESTORE +}; + struct ufs_mtk_phy { struct device *dev; void __iomem *mmio; + struct reset_control *reset; struct clk_bulk_data clks[UFSPHY_CLKS_CNT]; }; @@ -141,9 +152,59 @@ static int ufs_mtk_phy_power_off(struct phy *generic_phy) return 0; } +static int ufs_mtk_phy_ctrl(struct ufs_mtk_phy *phy, enum ufs_mtk_mphy_op op) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_UFS_CONTROL, UFS_MTK_SIP_MPHY_CTRL, op, + 0, 0, 0, 0, 0, &res); + + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_RET_INVALID_PARAMETER: + return -EINVAL; + default: + return 0; + } +} + +static int ufs_mtk_phy_reset(struct phy *generic_phy) +{ + struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy); + int ret; + + if (!phy->reset) + return -EOPNOTSUPP; + + ret = reset_control_assert(phy->reset); + if (ret) + return ret; + + usleep_range(100, 110); + + ret = reset_control_deassert(phy->reset); + if (ret) + return ret; + + /* + * To avoid double-sleep and other unintended side-effects in the ufshci + * driver, don't return the phy_ctrl retval here, but just return -EPROTO. + */ + ret = ufs_mtk_phy_ctrl(phy, UFS_MPHY_RESTORE); + if (ret) { + dev_err(phy->dev, "UFS_MPHY_RESTORE SMC command failed: %pe\n", + ERR_PTR(ret)); + return -EPROTO; + } + + return 0; +} + static const struct phy_ops ufs_mtk_phy_ops = { .power_on = ufs_mtk_phy_power_on, .power_off = ufs_mtk_phy_power_off, + .reset = ufs_mtk_phy_reset, .owner = THIS_MODULE, }; @@ -163,8 +224,18 @@ static int ufs_mtk_phy_probe(struct platform_device *pdev) if (IS_ERR(phy->mmio)) return PTR_ERR(phy->mmio); + phy->reset = devm_reset_control_get_optional(dev, NULL); + if (IS_ERR(phy->reset)) + return dev_err_probe(dev, PTR_ERR(phy->reset), "Failed to get reset\n"); + phy->dev = dev; + if (phy->reset) { + ret = ufs_mtk_phy_ctrl(phy, UFS_MPHY_BACKUP); + if (ret) + return dev_err_probe(dev, ret, "Failed to back up MPHY\n"); + } + ret = ufs_mtk_phy_clk_init(phy); if (ret) return ret; -- 2.51.0