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Tue, 14 Oct 2025 15:03:03 -0700 (PDT) From: David Lechner Date: Tue, 14 Oct 2025 17:02:11 -0500 Subject: [PATCH 1/6] dt-bindings: spi: Add spi-buses property Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251014-spi-add-multi-bus-support-v1-1-2098c12d6f5f@baylibre.com> References: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> In-Reply-To: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1791; i=dlechner@baylibre.com; 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Signed-off-by: David Lechner --- This patch has been seen before in a different series from Sean [1]. [1]: https://lore.kernel.org/linux-spi/20250616220054.3968946-2-sean.anderson@linux.dev/ Changes: * Added maxItems. (8 is the most I've seen so far on an ADC) * Tweaked the description a bit. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8b6e8fc009dbdc80978f3afef84ddc688ade4348..91c9de3ae10bbad76cd4f57d0789b1161ebc7a18 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -89,6 +89,17 @@ properties: description: Delay, in microseconds, after a write transfer. + spi-buses: + description: + Array of bus numbers that describes which SPI buses of the controller are + connected to the peripheral. This only applies to peripherals connected + to specialized SPI controllers that have multiple SPI buses (each with + its own serializer) on a single controller. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + default: [0] + stacked-memories: description: Several SPI memories can be wired in stacked mode. This basically means that either a device features several chip -- 2.43.0