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Tue, 14 Oct 2025 08:41:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH7MKAgrKXHfanZDhLxk8qbmij1H4ExOUqyMqzBv4euyBsK4QKZM6PUBQShnN55eCek+WQ0jw== X-Received: by 2002:a17:906:ee85:b0:b4e:f7cc:6346 with SMTP id a640c23a62f3a-b50aa08f852mr2493212866b.15.1760456472247; Tue, 14 Oct 2025 08:41:12 -0700 (PDT) Received: from holism.lzampier.com ([148.252.9.235]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b5cba45b3cbsm7897866b.40.2025.10.14.08.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 08:41:11 -0700 (PDT) From: Lucas Zampieri To: linux-kernel@vger.kernel.org Cc: Lucas Zampieri , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Vivian Wang , Charles Mirabile , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 0/3] Add UltraRISC DP1000 PLIC support Date: Tue, 14 Oct 2025 16:40:54 +0100 Message-ID: <20251014154100.168236-1-lzampier@redhat.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds support for the PLIC implementation in the UltraRISC DP1000 SoC. The UR-CP100 cores used in the DP1000 have a hardware bug in their PLIC claim register where reading it while multiple interrupts are pending can return the wrong interrupt ID. The workaround temporarily disables all interrupts except the first pending one before reading the claim register, then restores the previous state. The driver matches on "ultrarisc,cp100-plic" (CPU core compatible), allowing the quirk to apply to all SoCs using UR-CP100 cores (currently DP1000, potentially future SoCs). Charles Mirabile (2): dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC irqchip/plic: add support for UltraRISC DP1000 PLIC Lucas Zampieri (1): dt-bindings: vendor-prefixes: add UltraRISC Changes in v3: - 0002: Updated commit message to clarify that DP1000 is an SoC and CP100 is a core (feedback from Conor Dooley) - 0003: Renamed dp1000_* functions to cp100_* and updated commit message to clarify the hardware bug is in the UR-CP100 core implementation, not specific to the DP1000 SoC - 0003: Moved quirk check out of hot interrupt path by creating separate plic_handle_irq_cp100() function and selecting handler at probe time - 0003: Use existing handler->enable_save[] array instead of stack allocation - 0003: Use readl_relaxed()/writel_relaxed() for better performance Changes in v2: - 0002: Changed compatible string pattern to SoC+core: ultrarisc,dp1000-plic with ultrarisc,cp100-plic fallback (suggested by Krzysztof and Vivian) - 0003: Driver now matches on ultrarisc,cp100-plic (core) instead of dp1000 (SoC) - All patches: Added submitter Signed-off-by to complete DCO chain .../sifive,plic-1.0.0.yaml | 3 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/irqchip/irq-sifive-plic.c | 94 ++++++++++++++++++- 3 files changed, 98 insertions(+), 1 deletion(-) -- 2.51.0