Re: [PATCH v4 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC

Thomas Gleixner
2025-10-15T18:40:50Z

On Wed, Oct 15 2025 at 15:31, Lucas Zampieri wrote:
> +static bool cp100_isolate_pending_irq(int nr_irq_groups, u32 ie[],
> + void __iomem *pending,
> + void __iomem *enable)
> +{
> + u32 pending_irqs = 0;
> + int i, j;
> +
> + /* Look for first pending interrupt */
> + for (i = 0; i < nr_irq_groups; i++) {
> + pending_irqs = ie[i] & readl_relaxed(pending + i * sizeof(u32));
> + if (pending_irqs)
> + break;
> + }
> +
> + if (!pending_irqs)
> + return false;
> +
> + /* Disable all interrupts but the first pending one */
> + for (j = 0; j < nr_irq_groups; j++) {
> + u32 new_mask = 0;
> +
> + if (j == i)
> + /* Extract mask with lowest set bit */
> + new_mask = (pending_irqs & -pending_irqs);

Please add brackets around the conditional as it's not a true single
line.

> +static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler,
> + void __iomem *claim)
> +{
> + void __iomem *enable = handler->enable_base;
> + void __iomem *pending = handler->priv->regs + PENDING_BASE;
> + int nr_irqs = handler->priv->nr_irqs;
> + int nr_irq_groups = DIV_ROUND_UP(nr_irqs, 32);
> + int i;
> + irq_hw_number_t hwirq = 0;

Please use reverse fir tree ordering:

https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-declarations

> +
> + raw_spin_lock(&handler->enable_lock);

Please use

guard(raw_spinlock)(&handler->....);

which gets rid of the goto and you can just return instead.

> + /* Save current interrupt enable state */
> + for (i = 0; i < nr_irq_groups; i++)
> + handler->enable_save[i] = readl_relaxed(enable + i * sizeof(u32));
> +
> + if (!cp100_isolate_pending_irq(nr_irq_groups, handler->enable_save, pending, enable))
> + goto out;
> +
> + hwirq = readl(claim);
> +
> + /* Restore previous state */
> + for (i = 0; i < nr_irq_groups; i++)
> + writel_relaxed(handler->enable_save[i], enable + i * sizeof(u32));
> +out:
> + raw_spin_unlock(&handler->enable_lock);
> + return hwirq;
> +}
> +
> +static void plic_handle_irq_cp100(struct irq_desc *desc)
> +{
> + struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
> + irq_hw_number_t hwirq;
> +
> + WARN_ON_ONCE(!handler->present);
> +
> + chained_irq_enter(chip, desc);
> +
> + while ((hwirq = cp100_get_hwirq(handler, claim))) {
> + int err = generic_handle_domain_irq(handler->priv->irqdomain,
> + hwirq);

Let it stick out, you have 100 characters

> + if (unlikely(err)) {
> + pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n",
> + handler->priv->fwnode, hwirq);
> + }
> + }
> +
> + chained_irq_exit(chip, desc);
> +}
> +
> static void plic_set_threshold(struct plic_handler *handler, u32 threshold)
> {
> /* priority must be > threshold to trigger an interrupt */
> @@ -430,6 +516,8 @@ static const struct of_device_id plic_match[] = {
> .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
> { .compatible = "thead,c900-plic",
> .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
> + { .compatible = "ultrarisc,cp100-plic",
> + .data = (const void *)BIT(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM) },
> {}
> };
>
> @@ -664,12 +752,16 @@ static int plic_probe(struct fwnode_handle *fwnode)
> }
>
> if (global_setup) {
> + void (*handler_fn)(struct irq_desc *) = plic_handle_irq;

Lacks a newline between variable declaration and code.

> + if (test_bit(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM, &handler->priv->plic_quirks))
> + handler_fn = plic_handle_irq_cp100;
> +
> /* Find parent domain and register chained handler */
> domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
> if (domain)
> plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
> if (plic_parent_irq)
> - irq_set_chained_handler(plic_parent_irq, plic_handle_irq);
> + irq_set_chained_handler(plic_parent_irq, handler_fn);
>
> cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
> "irqchip/sifive/plic:starting",

Thanks,

tglx