[PATCH v2 0/3] Add edp reference clock for lemans

[PATCH v2 0/3] Add edp reference clock for lemans

[Ritesh Kumar]

On lemans chipset, edp reference clock is being voted by ufs mem phy
(ufs_mem_phy: phy@1d87000). But after commit 77d2fa54a9457
("scsi: ufs: qcom : Refactor phy_power_on/off calls") edp reference
clock is getting turned off, leading to below phy poweron failure on
lemans edp phy.

[   19.830220] phy phy-aec2a00.phy.10: phy poweron failed --> -110
[   19.842112] mdss_0_disp_cc_mdss_dptx0_link_clk status stuck at 'off'
[   19.842131] WARNING: CPU: 2 PID: 371 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x174/0x18c
[   19.984356] Hardware name: Qualcomm QCS9100 Ride (DT)
[   19.989548] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[   19.996697] pc : clk_branch_toggle+0x174/0x18c
[   20.001267] lr : clk_branch_toggle+0x174/0x18c
[   20.005833] sp : ffff8000863ebbc0
[   20.009251] x29: ffff8000863ebbd0 x28: 0000000000000000 x27: 0000000000000000
[   20.016579] x26: 0000000000000000 x25: 0000000000000000 x24: 0000000000000001
[   20.023915] x23: ffff0000c53de980 x22: 0000000000000001 x21: ffffb4b57fd8d710
[   20.031245] x20: ffffb4b5bb238b88 x19: 0000000000000000 x18: ffffffffffff7198
[   20.038584] x17: 0000000000000014 x16: ffffb4b5bb1e2330 x15: 0000000000000048
[   20.045926] x14: 0000000000000000 x13: ffffb4b5bd386a48 x12: 0000000000000dfb
[   20.053263] x11: 00000000000004a9 x10: ffffb4b5bd3e5a20 x9 : ffffb4b5bd386a48
[   20.060600] x8 : 00000000ffffefff x7 : ffffb4b5bd3dea48 x6 : 00000000000004a9
[   20.067934] x5 : ffff000eb7d38408 x4 : 40000000fffff4a9 x3 : ffff4b58fb2b7000
[   20.075269] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000ec4fc3480
[   20.082601] Call trace:
[   20.085127]  clk_branch_toggle+0x174/0x18c (P)
[   20.089705]  clk_branch2_enable+0x1c/0x28
[   20.093829]  clk_core_enable+0x6c/0xac
[   20.097687]  clk_enable+0x2c/0x4c
[   20.101104]  clk_bulk_enable+0x4c/0xd8
[   20.104964]  msm_dp_ctrl_enable_mainlink_clocks+0x184/0x24c [msm]
[   20.111294]  msm_dp_ctrl_on_link+0xb0/0x400 [msm]
[   20.116178]  msm_dp_display_process_hpd_high+0x110/0x190 [msm]
[   20.122209]  msm_dp_hpd_plug_handle.isra.0+0xac/0x1c4 [msm]
[   20.127983]  hpd_event_thread+0x320/0x5cc [msm]
[   20.132680]  kthread+0x12c/0x204
[   20.136011]  ret_from_fork+0x10/0x20
[   20.139699] ---[ end trace 0000000000000000 ]---
[   20.144489] Failed to enable clk 'ctrl_link': -16
[   20.149340] [drm:msm_dp_ctrl_enable_mainlink_clocks [msm]] *ERROR* Unable to start link clocks. ret=-16

This series adds support for voting the clock from lemans edp phy driver.

---
This series is dependent on below series:
https://lore.kernel.org/all/20250909-phy-qcom-edp-add-missing-refclk-v3-0-4ec55a0512ab@linaro.org/

Change in v2:
- Rebase on top of above series. [Krzysztof]
- Remove duplicate patches and make changes limited to lemans.
- Link to v1: https://lore.kernel.org/all/20251009071127.26026-1-quic_riteshk@quicinc.com/

---
Ritesh Kumar (3):
  dt-bindings: phy: qcom-edp: Add missing clock for sa8775p
  dt-bindings: display/msm: qcom,sa8775p-mdss: update edp phy example
  arm64: dts: qcom: lemans: Add edp reference clock for edp phy

 .../bindings/display/msm/qcom,sa8775p-mdss.yaml      |  6 ++++--
 .../devicetree/bindings/phy/qcom,edp-phy.yaml        |  1 +
 arch/arm64/boot/dts/qcom/lemans.dtsi                 | 12 ++++++++----
 3 files changed, 13 insertions(+), 6 deletions(-)

-- 
2.17.1

[PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Ritesh Kumar]

Add edp reference clock for sa8775p edp phy.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
index bfc4d75f50ff..b0e4015596de 100644
--- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
@@ -73,6 +73,7 @@ allOf:
         compatible:
           enum:
             - qcom,x1e80100-dp-phy
+            - qcom,sa8775p-edp-phy
     then:
       properties:
         clocks:
-- 
2.17.1

[PATCH v2 2/3] dt-bindings: display/msm: qcom,sa8775p-mdss: update edp phy example

[Ritesh Kumar]

Update clock entry in edp phy example node to add support for edp
reference clock.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml  | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
index e2730a2f25cf..16bb3f7043c8 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -200,9 +200,11 @@ examples:
                   <0x0aec2000 0x1c8>;
 
             clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
-                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+                     <&gcc GCC_EDP_REF_CLKREF_EN>;
             clock-names = "aux",
-                          "cfg_ahb";
+                          "cfg_ahb",
+                          "ref";
 
             #clock-cells = <1>;
             #phy-cells = <0>;
-- 
2.17.1

[PATCH v2 3/3] arm64: dts: qcom: lemans: Add edp reference clock for edp phy

[Ritesh Kumar]

Add edp reference clock for edp phy on lemans chipset.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index cf685cb186ed..1bcf1edd9382 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5034,9 +5034,11 @@
 				      <0x0 0x0aec2000 0x0 0x1c8>;
 
 				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
-					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_EDP_REF_CLKREF_EN>;
 				clock-names = "aux",
-					      "cfg_ahb";
+					      "cfg_ahb",
+					      "ref";
 
 				#clock-cells = <1>;
 				#phy-cells = <0>;
@@ -5053,9 +5055,11 @@
 				      <0x0 0x0aec5000 0x0 0x1c8>;
 
 				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
-					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_EDP_REF_CLKREF_EN>;
 				clock-names = "aux",
-					      "cfg_ahb";
+					      "cfg_ahb",
+					      "ref";
 
 				#clock-cells = <1>;
 				#phy-cells = <0>;
-- 
2.17.1

Re: [PATCH v2 0/3] Add edp reference clock for lemans

[Dmitry Baryshkov]

On Mon, Oct 13, 2025 at 04:18:03PM +0530, Ritesh Kumar wrote:
> On lemans chipset, edp reference clock is being voted by ufs mem phy
> (ufs_mem_phy: phy@1d87000). But after commit 77d2fa54a9457
> ("scsi: ufs: qcom : Refactor phy_power_on/off calls") edp reference
> clock is getting turned off, leading to below phy poweron failure on
> lemans edp phy.

How does UFS turn on eDP reference clock?


-- 
With best wishes
Dmitry

Re: [PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Dmitry Baryshkov]

On Mon, Oct 13, 2025 at 04:18:04PM +0530, Ritesh Kumar wrote:
> Add edp reference clock for sa8775p edp phy.
> 
> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
> ---
>  Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> index bfc4d75f50ff..b0e4015596de 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> @@ -73,6 +73,7 @@ allOf:
>          compatible:
>            enum:
>              - qcom,x1e80100-dp-phy
> +            - qcom,sa8775p-edp-phy

Usually such lists are sorted.

>      then:
>        properties:
>          clocks:
> -- 
> 2.17.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 2/3] dt-bindings: display/msm: qcom, sa8775p-mdss: update edp phy example

[Dmitry Baryshkov]

On Mon, Oct 13, 2025 at 04:18:05PM +0530, Ritesh Kumar wrote:
> Update clock entry in edp phy example node to add support for edp
> reference clock.

eDP, PHY.

> 
> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
> ---
>  .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml  | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 


-- 
With best wishes
Dmitry

Re: [PATCH v2 3/3] arm64: dts: qcom: lemans: Add edp reference clock for edp phy

[Dmitry Baryshkov]

On Mon, Oct 13, 2025 at 04:18:06PM +0530, Ritesh Kumar wrote:
> Add edp reference clock for edp phy on lemans chipset.

eDP, PHY, Fixes:foo bar baz

> 
> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index cf685cb186ed..1bcf1edd9382 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -5034,9 +5034,11 @@
>  				      <0x0 0x0aec2000 0x0 0x1c8>;
>  
>  				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> -					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> +					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> +					 <&gcc GCC_EDP_REF_CLKREF_EN>;
>  				clock-names = "aux",
> -					      "cfg_ahb";
> +					      "cfg_ahb",
> +					      "ref";
>  
>  				#clock-cells = <1>;
>  				#phy-cells = <0>;
> @@ -5053,9 +5055,11 @@
>  				      <0x0 0x0aec5000 0x0 0x1c8>;
>  
>  				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> -					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> +					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> +					 <&gcc GCC_EDP_REF_CLKREF_EN>;
>  				clock-names = "aux",
> -					      "cfg_ahb";
> +					      "cfg_ahb",
> +					      "ref";
>  
>  				#clock-cells = <1>;
>  				#phy-cells = <0>;
> -- 
> 2.17.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Dmitry Baryshkov]

On Mon, Oct 13, 2025 at 04:18:04PM +0530, Ritesh Kumar wrote:
> Add edp reference clock for sa8775p edp phy.

eDP, PHY.

I'd probably ask to squash both DT binding patches together, but this
might cause cross-subsystem merge issues. I'll leave this to DT
maintainers discretion, whether to require a non-warning-adding patch or
two patches with warnings in the middle of the series.

> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
> ---
>  Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> index bfc4d75f50ff..b0e4015596de 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> @@ -73,6 +73,7 @@ allOf:
>          compatible:
>            enum:
>              - qcom,x1e80100-dp-phy
> +            - qcom,sa8775p-edp-phy
>      then:
>        properties:
>          clocks:
> -- 
> 2.17.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 0/3] Add edp reference clock for lemans

[Ritesh Kumar]

On 10/13/2025 6:04 PM, Dmitry Baryshkov wrote:
> On Mon, Oct 13, 2025 at 04:18:03PM +0530, Ritesh Kumar wrote:
> > On lemans chipset, edp reference clock is being voted by ufs mem phy
> > (ufs_mem_phy: phy@1d87000). But after commit 77d2fa54a9457
> > ("scsi: ufs: qcom : Refactor phy_power_on/off calls") edp reference
> > clock is getting turned off, leading to below phy poweron failure on
> > lemans edp phy.
>
> How does UFS turn on eDP reference clock?

In lemans, GCC_EDP_REF_CLKREF_EN is voted as qref clock in ufs_mem_phy.


ufs_mem_phy: phy@1d87000 {
     compatible = "qcom,sa8775p-qmp-ufs-phy";
     reg = <0x0 0x01d87000 0x0 0xe10>;
     /*
      * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
      * enables the CXO clock to eDP *and* UFS PHY.
      */
     clocks = <&rpmhcc RPMH_CXO_CLK>,
              <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
              <&gcc GCC_EDP_REF_CLKREF_EN>;
     clock-names = "ref", "ref_aux", "qref";

>
>

Re: [PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Rob Herring]

On Mon, Oct 13, 2025 at 03:37:47PM +0300, Dmitry Baryshkov wrote:
> On Mon, Oct 13, 2025 at 04:18:04PM +0530, Ritesh Kumar wrote:
> > Add edp reference clock for sa8775p edp phy.
> 
> eDP, PHY.
> 
> I'd probably ask to squash both DT binding patches together, but this
> might cause cross-subsystem merge issues. I'll leave this to DT
> maintainers discretion, whether to require a non-warning-adding patch or
> two patches with warnings in the middle of the series.

One patch.

Rob

Re: [PATCH v2 0/3] Add edp reference clock for lemans

[Dmitry Baryshkov]

On Wed, Oct 15, 2025 at 02:49:08PM +0530, Ritesh Kumar wrote:
> 
> On 10/13/2025 6:04 PM, Dmitry Baryshkov wrote:
> > On Mon, Oct 13, 2025 at 04:18:03PM +0530, Ritesh Kumar wrote:
> > > On lemans chipset, edp reference clock is being voted by ufs mem phy
> > > (ufs_mem_phy: phy@1d87000). But after commit 77d2fa54a9457
> > > ("scsi: ufs: qcom : Refactor phy_power_on/off calls") edp reference
> > > clock is getting turned off, leading to below phy poweron failure on
> > > lemans edp phy.
> > 
> > How does UFS turn on eDP reference clock?
> 
> In lemans, GCC_EDP_REF_CLKREF_EN is voted as qref clock in ufs_mem_phy.
> 

Ack, please fix other comments.

> 
> ufs_mem_phy: phy@1d87000 {
>     compatible = "qcom,sa8775p-qmp-ufs-phy";
>     reg = <0x0 0x01d87000 0x0 0xe10>;
>     /*
>      * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
>      * enables the CXO clock to eDP *and* UFS PHY.
>      */
>     clocks = <&rpmhcc RPMH_CXO_CLK>,
>              <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>              <&gcc GCC_EDP_REF_CLKREF_EN>;
>     clock-names = "ref", "ref_aux", "qref";
> 
> > 
> > 

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Bjorn Andersson]

On Mon, Oct 13, 2025 at 04:18:04PM +0530, Ritesh Kumar wrote:
> Add edp reference clock for sa8775p edp phy.

Perhaps the eDP ref clock was missed in the initial contribution,
perhaps it wasn't supposed to be described at the time, perhaps the
hardware changed...we can only speculate on the purpose of this patch...

You could change this however, by following
https://docs.kernel.org/process/submitting-patches.html#describe-your-changes
and start your commit message with an explanation of the problem you're
trying to solve...

> 
> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>

Please start using your oss.qualcomm.com 

Regards,
Bjorn

> ---
>  Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> index bfc4d75f50ff..b0e4015596de 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> @@ -73,6 +73,7 @@ allOf:
>          compatible:
>            enum:
>              - qcom,x1e80100-dp-phy
> +            - qcom,sa8775p-edp-phy
>      then:
>        properties:
>          clocks:
> -- 
> 2.17.1
> 

Re: [PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Ritesh Kumar]

On 10/13/2025 6:04 PM, Dmitry Baryshkov wrote:
> On Mon, Oct 13, 2025 at 04:18:04PM +0530, Ritesh Kumar wrote:
> > Add edp reference clock for sa8775p edp phy.
> > 
> > Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
> > ---
> >  Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > index bfc4d75f50ff..b0e4015596de 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > @@ -73,6 +73,7 @@ allOf:
> >          compatible:
> >            enum:
> >              - qcom,x1e80100-dp-phy
> > +            - qcom,sa8775p-edp-phy
>
> Usually such lists are sorted.

Sure, will update in next version.

>
> >      then:
> >        properties:
> >          clocks:
> > -- 
> > 2.17.1
> > 
>

Re: [PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Ritesh Kumar]

On 10/15/2025 8:13 PM, Rob Herring wrote:
> On Mon, Oct 13, 2025 at 03:37:47PM +0300, Dmitry Baryshkov wrote:
> > On Mon, Oct 13, 2025 at 04:18:04PM +0530, Ritesh Kumar wrote:
> > > Add edp reference clock for sa8775p edp phy.
> > 
> > eDP, PHY.
> > 
> > I'd probably ask to squash both DT binding patches together, but this
> > might cause cross-subsystem merge issues. I'll leave this to DT
> > maintainers discretion, whether to require a non-warning-adding patch or
> > two patches with warnings in the middle of the series.
>
> One patch.

Sure, will update a single patch for DT bindings.

> Rob
>

Re: [PATCH v2 1/3] dt-bindings: phy: qcom-edp: Add edp ref clk for sa8775p

[Ritesh Kumar]

On 10/27/2025 10:35 PM, Bjorn Andersson wrote:
> On Mon, Oct 13, 2025 at 04:18:04PM +0530, Ritesh Kumar wrote:
> > Add edp reference clock for sa8775p edp phy.
>
> Perhaps the eDP ref clock was missed in the initial contribution,
> perhaps it wasn't supposed to be described at the time, perhaps the
> hardware changed...we can only speculate on the purpose of this patch...
>
> You could change this however, by following
> https://docs.kernel.org/process/submitting-patches.html#describe-your-changes
> and start your commit message with an explanation of the problem you're
> trying to solve...

Sure, will update the commit message giving details of the problem.

> > 
> > Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
>
> Please start using your oss.qualcomm.com

Took a note of it.

> Regards,
> Bjorn
>
> > ---
> >  Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > index bfc4d75f50ff..b0e4015596de 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > @@ -73,6 +73,7 @@ allOf:
> >          compatible:
> >            enum:
> >              - qcom,x1e80100-dp-phy
> > +            - qcom,sa8775p-edp-phy
> >      then:
> >        properties:
> >          clocks:
> > -- 
> > 2.17.1
> > 

Re: [PATCH v2 3/3] arm64: dts: qcom: lemans: Add edp reference clock for edp phy

[Ritesh Kumar]

On 10/13/2025 6:05 PM, Dmitry Baryshkov wrote:
> On Mon, Oct 13, 2025 at 04:18:06PM +0530, Ritesh Kumar wrote:
> > Add edp reference clock for edp phy on lemans chipset.
>
> eDP, PHY, Fixes:foo bar baz

Sure, will update in next version.

>
> > 
> > Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
> > ---
> >  arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++----
> >  1 file changed, 8 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > index cf685cb186ed..1bcf1edd9382 100644
> > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > @@ -5034,9 +5034,11 @@
> >  				      <0x0 0x0aec2000 0x0 0x1c8>;
> >  
> >  				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > -					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> > +					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> > +					 <&gcc GCC_EDP_REF_CLKREF_EN>;
> >  				clock-names = "aux",
> > -					      "cfg_ahb";
> > +					      "cfg_ahb",
> > +					      "ref";
> >  
> >  				#clock-cells = <1>;
> >  				#phy-cells = <0>;
> > @@ -5053,9 +5055,11 @@
> >  				      <0x0 0x0aec5000 0x0 0x1c8>;
> >  
> >  				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> > -					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> > +					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> > +					 <&gcc GCC_EDP_REF_CLKREF_EN>;
> >  				clock-names = "aux",
> > -					      "cfg_ahb";
> > +					      "cfg_ahb",
> > +					      "ref";
> >  
> >  				#clock-cells = <1>;
> >  				#phy-cells = <0>;
> > -- 
> > 2.17.1
> > 
>