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From: Lothar Rubusch <l.rubusch@gmail.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	dinguyen@kernel.org, martin.petersen@oracle.com,
	pabeni@redhat.com, rostedt@goodmis.org, bhelgaas@google.com,
	l.rubusch@gmail.com
Cc: arnd@arndb.de, matthew.gerlach@altera.com,
	tien.fong.chee@altera.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v6 02/11] ARM: dts: socfpga: add Enclustra base-board dtsi
Date: Wed, 15 Oct 2025 19:44:07 +0000	[thread overview]
Message-ID: <20251015194416.33502-3-l.rubusch@gmail.com> (raw)
In-Reply-To: <20251015194416.33502-1-l.rubusch@gmail.com>

Add generic Enclustra base-board support for the Mercury+ PE1, the
Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be
freely combined with the SoMs Mercury+ AA1, Mercury SA1 and
Mercury+ SA2.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 .../socfpga_enclustra_mercury_pe1.dtsi        | 33 +++++++++++
 .../socfpga_enclustra_mercury_pe3.dtsi        | 55 +++++++++++++++++++
 .../socfpga_enclustra_mercury_st1.dtsi        | 15 +++++
 3 files changed, 103 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi

diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
new file mode 100644
index 000000000000..abc4bfb7fccf
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+	status = "okay";
+
+	eeprom@57 {
+		status = "okay";
+		compatible = "microchip,24c128";
+		reg = <0x57>;
+		pagesize = <64>;
+		label = "user eeprom";
+		address-width = <16>;
+	};
+
+	lm96080: temperature-sensor@2f {
+		status = "okay";
+		compatible = "national,lm80";
+		reg = <0x2f>;
+	};
+
+	si5338: clock-controller@70 {
+		compatible = "silabs,si5338";
+		reg = <0x70>;
+	};
+
+};
+
+&i2c_encl_fpga {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
new file mode 100644
index 000000000000..bc57b0680878
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+	i2c-mux@74 {
+		status = "okay";
+		compatible = "nxp,pca9547";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@56 {
+				status = "okay";
+				compatible = "microchip,24c128";
+				reg = <0x56>;
+				pagesize = <64>;
+				label = "user eeprom";
+				address-width = <16>;
+			};
+
+			lm96080: temperature-sensor@2f {
+				status = "okay";
+				compatible = "national,lm80";
+				reg = <0x2f>;
+			};
+
+			pcal6416: gpio@20 {
+				status = "okay";
+				compatible = "nxp,pcal6416";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+	};
+};
+
+&i2c_encl_fpga {
+	status = "okay";
+
+	i2c-mux@75 {
+		status = "okay";
+		compatible = "nxp,pca9547";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+	};
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
new file mode 100644
index 000000000000..4c00475f4303
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+	si5338: clock-controller@70 {
+		compatible = "silabs,si5338";
+		reg = <0x70>;
+	};
+};
+
+&i2c_encl_fpga {
+	status = "okay";
+};
-- 
2.39.5


  parent reply	other threads:[~2025-10-15 19:44 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-15 19:44 [PATCH v6 00/11] Add Enclustra Arria10 and Cyclone5 SoMs Lothar Rubusch
2025-10-15 19:44 ` [PATCH v6 01/11] ARM: dts: socfpga: add Enclustra boot-mode dtsi Lothar Rubusch
2025-10-15 19:44 ` Lothar Rubusch [this message]
2025-10-15 19:44 ` [PATCH v6 03/11] ARM: dts: socfpga: add Enclustra Mercury SA1 Lothar Rubusch
2025-10-15 19:44 ` [PATCH v6 04/11] dt-bindings: altera: " Lothar Rubusch
2025-10-15 19:44 ` [PATCH v6 05/11] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Lothar Rubusch
2025-10-15 19:44 ` [PATCH v6 06/11] dt-bindings: altera: add binding for " Lothar Rubusch
2025-10-15 19:44 ` [PATCH v6 07/11] ARM: dts: socfpga: add Mercury AA1 variants Lothar Rubusch
2025-10-15 19:44 ` [PATCH v6 08/11] dt-bindings: altera: " Lothar Rubusch
2025-10-16 16:32   ` Rob Herring
2025-10-15 19:44 ` [PATCH v6 09/11] ARM: dts: socfpga: removal of generic PE1 dts Lothar Rubusch
2025-10-15 19:44 ` [PATCH v6 10/11] dt-bindings: altera: " Lothar Rubusch
2025-10-16 16:33   ` Rob Herring
2025-10-15 19:44 ` [PATCH v6 11/11] ARM: dts: socfpga: add Enclustra SoM dts files Lothar Rubusch
2025-10-16  2:21 ` [PATCH v6 00/11] Add Enclustra Arria10 and Cyclone5 SoMs Rob Herring (Arm)

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