From: Conor Dooley <conor@kernel.org>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Hal Feng <hal.feng@starfivetech.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
E Shattow <e@freeshell.de>, Paul Walmsley <pjw@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v1 2/7] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
Date: Thu, 16 Oct 2025 16:51:33 +0100 [thread overview]
Message-ID: <20251016-countable-probing-062cd0504baf@spud> (raw)
In-Reply-To: <a4c5e7fd-a37d-4729-ad58-81523f813fb3@canonical.com>
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On Thu, Oct 16, 2025 at 10:58:41AM +0200, Heinrich Schuchardt wrote:
> On 10/16/25 10:00, Hal Feng wrote:
> > Add enable-gpios property for controlling the PCI bus device power.
> > This property had been supported in the driver but not added in the
> > dt-bindings.
> >
> > Fixes: 22fe32239770 ("dt-bindings: PCI: Add StarFive JH7110 PCIe controller")
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > .../devicetree/bindings/pci/starfive,jh7110-pcie.yaml | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > index 5f432452c815..f254c7111837 100644
> > --- a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > @@ -60,6 +60,10 @@ properties:
> > description:
> > The phandle to System Register Controller syscon node.
> > + enable-gpios:
> > + description: GPIO used to enable the PCI bus device power
> > + maxItems: 1
> > +
>
> Shouldn't we try to keep the entries alphabetically ordered?
Grouping the two gpios together also has some value. I don't think it's
particularly important which way it is done.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
>
> Otherwise looks good.
>
> Best regards
>
> Heinrich
>
> > perst-gpios:
> > description: GPIO controlled connection to PERST# signal
> > maxItems: 1
>
>
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next prev parent reply other threads:[~2025-10-16 15:51 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 8:00 [PATCH v1 0/7] Add support for StarFive VisionFive 2 Lite board Hal Feng
2025-10-16 8:00 ` [PATCH v1 1/7] cpufreq: dt-platdev: Add JH7110S SOC to the allowlist Hal Feng
2025-10-16 9:20 ` Heinrich Schuchardt
2025-10-17 5:09 ` Viresh Kumar
2025-10-16 8:00 ` [PATCH v1 2/7] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property Hal Feng
2025-10-16 8:58 ` Heinrich Schuchardt
2025-10-16 15:51 ` Conor Dooley [this message]
2025-10-16 8:00 ` [PATCH v1 3/7] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board Hal Feng
2025-10-16 9:24 ` Heinrich Schuchardt
2025-10-16 15:55 ` Conor Dooley
2025-10-16 8:00 ` [PATCH v1 4/7] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts Hal Feng
2025-10-16 15:54 ` Conor Dooley
2025-10-16 22:55 ` E Shattow
2025-11-03 5:43 ` Hal Feng
2025-10-16 8:00 ` [PATCH v1 5/7] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants Hal Feng
2025-10-16 8:00 ` [PATCH v1 6/7] riscv: dts: starfive: Add VisionFive 2 Lite board device tree Hal Feng
2025-10-16 8:00 ` [PATCH v1 7/7] riscv: dts: starfive: Add VisionFive 2 Lite eMMC " Hal Feng
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