Re: [PATCH] dt-bindings: usb: Add ESWIN EIC7700 USB controller

[Conor Dooley <conor@kernel.org>]

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On Thu, Oct 16, 2025 at 05:47:48PM +0800, caohang@eswincomputing.com wrote:
> From: Hang Cao <caohang@eswincomputing.com>
> 
> Add Device Tree binding documentation for the ESWIN EIC7700
> usb controller module.
> 
> Signed-off-by: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
> Signed-off-by: Hang Cao <caohang@eswincomputing.com>
> ---
>  .../bindings/usb/eswin,eic7700-usb.yaml       | 99 +++++++++++++++++++
>  1 file changed, 99 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml
> new file mode 100644
> index 000000000000..589a3ab6c644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml
> @@ -0,0 +1,99 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/eswin,eic7700-usb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ESWIN EIC7700 SoC Usb Controller
> +
> +maintainers:
> +  - Wei Yang <yangwei1@eswincomputing.com>
> +  - Senchuan Zhang <zhangsenchuan@eswincomputing.com>
> +  - Hang Cao <caohang@eswincomputing.com>
> +
> +description:
> +  The Usb controller on EIC7700 SoC.
> +
> +allOf:
> +  - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: eswin,eic7700-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-names:
> +    items:
> +      - const: peripheral
> +
> +  clocks:
> +    maxItems: 3
> +
> +  clock-names:
> +    items:
> +      - const: aclk
> +      - const: cfg
> +      - const: usb_en
> +
> +  resets:
> +    maxItems: 2
> +
> +  reset-names:
> +    items:
> +      - const: vaux
> +      - const: usb_rst

Drop the _rst here, since this can't be anything other than a reset.

> +  eswin,hsp-sp-csr:
> +    description:
> +      HSP CSR is to control and get status of different high-speed peripherals
> +      (such as Ethernet, USB, SATA, etc.) via register, which can tune
> +      board-level's parameters of PHY, etc.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to HSP Register Controller hsp_sp_csr node.
> +          - description: USB bus register offset.
> +          - description: AXI low power register offset.

This looks better than before, thanks.

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - interrupt-names
> +  - resets
> +  - reset-names
> +  - eswin,hsp-sp-csr
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    usb@50480000 {
> +        compatible = "eswin,eic7700-dwc3";
> +        reg = <0x50480000 0x10000>;
> +        clocks = <&clock 135>,
> +                 <&clock 136>,
> +                 <&hspcrg 18>;
> +        clock-names = "aclk", "cfg", "usb_en";
> +        interrupt-parent = <&plic>;
> +        interrupts = <85>;
> +        interrupt-names = "peripheral";
> +        resets = <&reset 84>, <&hspcrg 2>;
> +        reset-names = "vaux", "usb_rst";
> +        dr_mode = "peripheral";
> +        maximum-speed = "high-speed";
> +        phy_type = "utmi";

> +        snps,dis_enblslpm_quirk;
> +        snps,dis-u2-freeclk-exists-quirk;
> +        snps,dis_u2_susphy_quirk;
> +        snps,dis-del-phy-power-chg-quirk;
> +        snps,parkmode-disable-ss-quirk;

If any of these "quirks" are required for the device to function
properly, please mark them as required so that they don't ever get left
out. If it is board dependant, that's fine. I'm only interested in what
is set on the SoC level.
If most properties from the common snps binding are not possible, please
use additionalProperties: false and only permit those that are.

pw-bot: changes-requested

> +        eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>;
> +    };
> -- 
> 2.34.1
> 

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