From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1687D1A23A4; Mon, 20 Oct 2025 01:37:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760924234; cv=none; b=T0tZv/wCuJwiK8T668OXXYsoK/4ClWfunBj4/oF04C6PBjMaiULrtNQ1ID7kDNtWMHGSZLLaNrIbj11XzNGsfYbdWeFWsn8VPush2Jehleih+C3d+Gy+QZTMLdYX2hoQwHz7hr2pNn761LgFmc6OkvgD01sZ3hbcz0vAQpK12+A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760924234; c=relaxed/simple; bh=29pBD+5qA1J3YztVcKSw6k9PtF1vgwveOwUoZjuFi7w=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f3qFpdLJhIYCn9CJjnr1kZm0t0tH/NvOnaYqTr1ZEvI4MUTyGrqdujzdOuiQYQJcAvtuZA/lHdSJlej0HNUMiP6Lf2mNu+YBJeoT2K/d4cWGyQIDhukrakjD3g+1J+UVL2mf3hnvm7UbCzSIpnbkgRCKb7bQS1SzVxGiDjhjR3E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 20 Oct 2025 09:32:01 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 20 Oct 2025 09:32:01 +0800 From: Ryan Chen To: , , , , , , , , , , , , , , , , Subject: [PATCH v19 1/4] dt-bindings: i2c: Split AST2600 binding into a new YAML Date: Mon, 20 Oct 2025 09:31:57 +0800 Message-ID: <20251020013200.1858325-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251020013200.1858325-1-ryan_chen@aspeedtech.com> References: <20251020013200.1858325-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The AST2600 I2C controller is a new hardware design compared to the I2C controllers in previous ASPEED SoCs (e.g., AST2400, AST2500). It introduces new features such as: - A redesigned register layout - Separation between controller and target mode registers - Transfer mode selection (byte, buffer, DMA) - Support for a shared global register block for configuration Due to these fundamental differences, maintaining a separate devicetree binding file for AST2600 helps to clearly distinguish the hardware capabilities and configuration options from the older controllers. Signed-off-by: Ryan Chen --- .../devicetree/bindings/i2c/aspeed,i2c.yaml | 3 +- .../devicetree/bindings/i2c/ast2600-i2c.yaml | 67 +++++++++++++++++++ 2 files changed, 68 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml index 5b9bd2feda3b..d4e4f412feba 100644 --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs +title: ASPEED I2C on the AST24XX, AST25XX SoCs maintainers: - Rayn Chen @@ -17,7 +17,6 @@ properties: enum: - aspeed,ast2400-i2c-bus - aspeed,ast2500-i2c-bus - - aspeed,ast2600-i2c-bus reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml b/Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml new file mode 100644 index 000000000000..2dcddb0ecc2e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED I2C on the AST26XX SoCs + +maintainers: + - Ryan Chen + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - aspeed,ast2600-i2c-bus + + reg: + minItems: 1 + maxItems: 2 + items: + - description: address offset and range of bus + - description: address offset and range of bus buffer + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + root clock of bus, should reference the APB + clock in the second cell + + resets: + maxItems: 1 + + bus-frequency: + minimum: 500 + maximum: 4000000 + default: 100000 + description: frequency of the bus clock in Hz defaults to 100 kHz when not + specified + +required: + - reg + - compatible + - clocks + - resets + +unevaluatedProperties: false + +examples: + - | + #include + i2c@40 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-i2c-bus"; + reg = <0x40 0x40>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + }; -- 2.34.1