From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED8491E1A05; Mon, 20 Oct 2025 01:37:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760924236; cv=none; b=rS4+5lBG+g71gVBcQiZllNotwbEiGez3IVWwl7yWWKu87LuJku+QdBtAs7MjOm0kcw14kyFLORgIT2UfpZqFpf4R333g4p4XSNFXKw/CbdXIXZpGkzpsZQFQKhT6Sp61WFM4NhL08nnxzxRlwG4r8CR+f+DNzgLebq11JBQhdTw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760924236; c=relaxed/simple; bh=rZLE3w+x3F/d/lj1DCnHufPNm7UEIFSigj1F8SUs1nQ=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l42Xr3k7vJphPvjHRx82t/DydEzpyEuBs7df/zT6bK/DCk71h0QddXVa90SR/JdmzBgWmUlV8RJa8SrCIHIY+OdQiHhFYJ88opu3QHD4n27SHLwZ2Iv6rWHEM/fFvxd4wL13eIULmTzFUOZEKUVcJvtiU0mMXzzm33RqQDla+iU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 20 Oct 2025 09:32:01 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 20 Oct 2025 09:32:01 +0800 From: Ryan Chen To: , , , , , , , , , , , , , , , , Subject: [PATCH v19 2/4] dt-bindings: i2c: ast2600-i2c.yaml: Add global-regs and transfer-mode properties Date: Mon, 20 Oct 2025 09:31:58 +0800 Message-ID: <20251020013200.1858325-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251020013200.1858325-1-ryan_chen@aspeedtech.com> References: <20251020013200.1858325-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The AST2600 I2C controller supports three transfer modes: byte, buffer, and DMA. To allow board designers and firmware to explicitly select the preferred transfer mode for each controller instance. "aspeed,transfer-mode" to allow device tree to specify the desired transfer method used by each I2C controller instance. And AST2600 i2c controller have two register mode, one is legacy register layout which is mix controller/target register control together, another is new mode which is separate controller/target register control. Signed-off-by: Ryan Chen --- .../devicetree/bindings/i2c/ast2600-i2c.yaml | 32 ++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml b/Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml index 2dcddb0ecc2e..7fab9281d7b1 100644 --- a/Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/ast2600-i2c.yaml @@ -43,11 +43,39 @@ properties: description: frequency of the bus clock in Hz defaults to 100 kHz when not specified + aspeed,transfer-mode: + description: | + ASPEED ast2600 platform equipped with 16 I2C controllers each i2c controller + have 1 byte transfer buffer(byte mode), 32 bytes buffer(buffer mode), and + share a DMA engine. + Select I2C transfer mode for this controller. Supported values are: + - "byte": Use 1 byte for i2c transmit (1-byte buffer). + - "buffer": Use buffer (32-byte buffer) for i2c transmit. (default) + Better performance then byte mode. + - "dma": Each controller DMA mode is shared DMA engine. The AST2600 SoC + provides a single DMA engine shared for 16 I2C controllers, + so only a limited number of controllers can use DMA simultaneously. + Therefore, the DTS must explicitly assign which controllers are + configured to use DMA. + On AST2600, each controller supports all three modes. + If not specified, buffer mode is used by default. + enum: + - byte + - buffer + - dma + + aspeed,global-regs: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle reference to the i2c global syscon node, containing the + SoC-common i2c register set. + required: - reg - compatible - clocks - resets + - aspeed,global-regs unevaluatedProperties: false @@ -58,10 +86,12 @@ examples: #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-i2c-bus"; - reg = <0x40 0x40>; + reg = <0x80 0x80>, <0xc00 0x20>; + aspeed,global-regs = <&i2c_global>; clocks = <&syscon ASPEED_CLK_APB>; resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <0>; interrupt-parent = <&i2c_ic>; + aspeed,transfer-mode = "buffer"; }; -- 2.34.1