[PATCH v1 00/13] Add MediaTek SoC DRM support for MT8189

[PATCH v1 00/13] Add MediaTek SoC DRM support for MT8189

[Xiandong Wang]

base on mt8196 disp driver V4 https://patchwork.kernel.org/project/linux-mediatek/list/?series=996375

Xiandong Wang (13):
  dt-bindings: soc: mediatek: add aal yaml for MT8189
  dt-bindings: soc: mediatek: add ccorr yaml for MT8189
  dt-bindings: soc: mediatek: add color yaml for MT8189
  dt-bindings: soc: mediatek: add dither yaml for MT8189
  dt-bindings: soc: mediatek: add gamma yaml for MT8189
  dt-bindings: arm: mediatek: mmsys: add compatible for MT8189
  dt-bindings: soc: mediatek: add ovl yaml for MT8189
  dt-bindings: soc: mediatek: add rdma yaml for MT8189
  dt-bindings: soc: mediatek: add mutex yaml for MT8189
  dt-bindings: soc: mediatek: add dsi yaml for MT8189
  soc: mediatek: add mmsys support for MT8189
  drm/mediatek: Add support for mt8189 mmsys driver probe
  soc: mediatek: mutex: add mutex support for MT8189

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |   1 +
 .../display/mediatek/mediatek,aal.yaml        |   1 +
 .../display/mediatek/mediatek,ccorr.yaml      |   1 +
 .../display/mediatek/mediatek,color.yaml      |   1 +
 .../display/mediatek/mediatek,dither.yaml     |   1 +
 .../display/mediatek/mediatek,dsi.yaml        |   1 +
 .../display/mediatek/mediatek,gamma.yaml      |   1 +
 .../display/mediatek/mediatek,ovl.yaml        |   2 +
 .../display/mediatek/mediatek,rdma.yaml       |   1 +
 .../bindings/soc/mediatek/mediatek,mutex.yaml |   1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c       |   2 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c       |  40 +++
 drivers/gpu/drm/mediatek/mtk_disp_ovl.h       |   2 +
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   8 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  39 +++
 drivers/soc/mediatek/mt8189-mmsys.h           | 300 ++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  12 +
 drivers/soc/mediatek/mtk-mutex.c              |  88 +++++
 include/linux/soc/mediatek/mtk-mmsys.h        |   5 +
 19 files changed, 507 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8189-mmsys.h

-- 
2.46.0

[PATCH v1 01/13] dt-bindings: soc: mediatek: add aal yaml for MT8189

[Xiandong Wang]

Add compatible string to support aal for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,aal.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index daf90ebb39bf..f575835c091d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -38,6 +38,7 @@ properties:
           - enum:
               - mediatek,mt8186-disp-aal
               - mediatek,mt8188-disp-aal
+              - mediatek,mt8189-disp-aal
               - mediatek,mt8192-disp-aal
               - mediatek,mt8195-disp-aal
               - mediatek,mt8365-disp-aal
-- 
2.46.0

[PATCH v1 02/13] dt-bindings: soc: mediatek: add ccorr yaml for MT8189

[Xiandong Wang]

Add compatible string to support ccorr for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index fca8e7bb0cbc..5fe58ebdd47b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -31,6 +31,7 @@ properties:
           - enum:
               - mediatek,mt8186-disp-ccorr
               - mediatek,mt8188-disp-ccorr
+              - mediatek,mt8189-disp-ccorr
               - mediatek,mt8195-disp-ccorr
           - const: mediatek,mt8192-disp-ccorr
 
-- 
2.46.0

[PATCH v1 03/13] dt-bindings: soc: mediatek: add color yaml for MT8189

[Xiandong Wang]

Add compatible string to support color for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,color.yaml     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index 5564f4063317..8fcdefa6eb9a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -42,6 +42,7 @@ properties:
               - mediatek,mt8183-disp-color
               - mediatek,mt8186-disp-color
               - mediatek,mt8188-disp-color
+              - mediatek,mt8189-disp-color
               - mediatek,mt8192-disp-color
               - mediatek,mt8195-disp-color
               - mediatek,mt8365-disp-color
-- 
2.46.0

[PATCH v1 04/13] dt-bindings: soc: mediatek: add dither yaml for MT8189

[Xiandong Wang]

Add compatible string to support dither for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,dither.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index abaf27916d13..be4be0e20de8 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -28,6 +28,7 @@ properties:
           - enum:
               - mediatek,mt8186-disp-dither
               - mediatek,mt8188-disp-dither
+              - mediatek,mt8189-disp-dither
               - mediatek,mt8192-disp-dither
               - mediatek,mt8195-disp-dither
               - mediatek,mt8365-disp-dither
-- 
2.46.0

[PATCH v1 05/13] dt-bindings: soc: mediatek: add gamma yaml for MT8189

[Xiandong Wang]

Add compatible string to support gamma for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index 48542dc7e784..6dd35d9e1144 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -33,6 +33,7 @@ properties:
           - enum:
               - mediatek,mt8186-disp-gamma
               - mediatek,mt8188-disp-gamma
+              - mediatek,mt8189-disp-gamma
               - mediatek,mt8192-disp-gamma
               - mediatek,mt8195-disp-gamma
               - mediatek,mt8365-disp-gamma
-- 
2.46.0

[PATCH v1 06/13] dt-bindings: arm: mediatek: mmsys: add compatible for MT8189

[Xiandong Wang]

In MT8189, a single HW pipeline was an independent mmsys,
which included the OVL module, PQ module, and display interface
module.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 3f4262e93c78..f1889b9788ab 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -35,6 +35,7 @@ properties:
               - mediatek,mt8188-vdosys1
               - mediatek,mt8188-vppsys0
               - mediatek,mt8188-vppsys1
+              - mediatek,mt8189-mmsys
               - mediatek,mt8192-mmsys
               - mediatek,mt8195-vdosys1
               - mediatek,mt8195-vppsys0
-- 
2.46.0

Re: [PATCH v1 06/13] dt-bindings: arm: mediatek: mmsys: add compatible for MT8189

[AngeloGioacchino Del Regno]

Il 20/10/25 09:40, Xiandong Wang ha scritto:
> In MT8189, a single HW pipeline was an independent mmsys,
> which included the OVL module, PQ module, and display interface
> module.
> 
> Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v1 07/13] dt-bindings: soc: mediatek: add ovl yaml for MT8189

[Xiandong Wang]

Add compatible string to support ovl for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml      | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 4f110635afb6..578e90d0e3b9 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -25,6 +25,7 @@ properties:
           - mediatek,mt2701-disp-ovl
           - mediatek,mt8173-disp-ovl
           - mediatek,mt8183-disp-ovl
+          - mediatek,mt8189-disp-ovl
           - mediatek,mt8192-disp-ovl
           - mediatek,mt8195-disp-ovl
           - mediatek,mt8195-mdp3-ovl
@@ -44,6 +45,7 @@ properties:
           - const: mediatek,mt8192-disp-ovl
       - items:
           - const: mediatek,mt8188-disp-ovl
+          - const: mediatek,mt8189-disp-ovl
           - const: mediatek,mt8195-disp-ovl
       - items:
           - const: mediatek,mt8188-mdp3-ovl
-- 
2.46.0

Re: [PATCH v1 07/13] dt-bindings: soc: mediatek: add ovl yaml for MT8189

[AngeloGioacchino Del Regno]

Il 20/10/25 09:40, Xiandong Wang ha scritto:
> Add compatible string to support ovl for MT8189.
> 
> Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>

Please change the title and write a .. descriptive .. commit description.

dt-bindings: display: mediatek: ovl: Add compatible string for MT8189

Add a OVL compatible for the MT8189 SoC. This SoC's OVL IP is fully compatible
with the one found in MT819.. 5? 6? Which one?

Also do the same for all (well, most of, actually) of your bindings commits.

Cheers,
Angelo

> ---
>   .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml      | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> index 4f110635afb6..578e90d0e3b9 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> @@ -25,6 +25,7 @@ properties:
>             - mediatek,mt2701-disp-ovl
>             - mediatek,mt8173-disp-ovl
>             - mediatek,mt8183-disp-ovl
> +          - mediatek,mt8189-disp-ovl
>             - mediatek,mt8192-disp-ovl
>             - mediatek,mt8195-disp-ovl
>             - mediatek,mt8195-mdp3-ovl
> @@ -44,6 +45,7 @@ properties:
>             - const: mediatek,mt8192-disp-ovl
>         - items:
>             - const: mediatek,mt8188-disp-ovl
> +          - const: mediatek,mt8189-disp-ovl
>             - const: mediatek,mt8195-disp-ovl
>         - items:
>             - const: mediatek,mt8188-mdp3-ovl

[PATCH v1 08/13] dt-bindings: soc: mediatek: add rdma yaml for MT8189

[Xiandong Wang]

Add compatible string to support rdma for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index 878f676b581f..4d29a1385104 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -44,6 +44,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8186-disp-rdma
+              - mediatek,mt8189-disp-rdma
               - mediatek,mt8192-disp-rdma
               - mediatek,mt8365-disp-rdma
           - const: mediatek,mt8183-disp-rdma
-- 
2.46.0

[PATCH v1 09/13] dt-bindings: soc: mediatek: add mutex yaml for MT8189

[Xiandong Wang]

Add compatible string to support mutex for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index a10326a9683d..c0c565acdc64 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -85,6 +85,7 @@ allOf:
               - mediatek,mt8173-disp-mutex
               - mediatek,mt8186-disp-mutex
               - mediatek,mt8186-mdp3-mutex
+              - mediatek,mt8189-disp-mutex
               - mediatek,mt8192-disp-mutex
               - mediatek,mt8195-disp-mutex
     then:
-- 
2.46.0

Re: [PATCH v1 09/13] dt-bindings: soc: mediatek: add mutex yaml for MT8189

[AngeloGioacchino Del Regno]

Il 20/10/25 09:40, Xiandong Wang ha scritto:
> Add compatible string to support mutex for MT8189.
> 
> Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH v1 10/13] dt-bindings: soc: mediatek: add dsi yaml for MT8189

[Xiandong Wang]

Add compatible string to support dsi for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index 27ffbccc2a08..ae23f192e1e0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -36,6 +36,7 @@ properties:
           - const: mediatek,mt8173-dsi
       - items:
           - enum:
+              - mediatek,mt8189-dsi
               - mediatek,mt8195-dsi
               - mediatek,mt8365-dsi
           - const: mediatek,mt8183-dsi
-- 
2.46.0

[PATCH v1 11/13] soc: mediatek: add mmsys support for MT8189

[Xiandong Wang]

Add driver data for MT8189 and add the routing table for each mmsys.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 drivers/soc/mediatek/mt8189-mmsys.h    | 300 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       |  12 +
 include/linux/soc/mediatek/mtk-mmsys.h |   5 +
 3 files changed, 317 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8189-mmsys.h

diff --git a/drivers/soc/mediatek/mt8189-mmsys.h b/drivers/soc/mediatek/mt8189-mmsys.h
new file mode 100644
index 000000000000..31378b6ee100
--- /dev/null
+++ b/drivers/soc/mediatek/mt8189-mmsys.h
@@ -0,0 +1,300 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 MediaTek Inc.
+ */
+
+#ifndef __SOC_MEDIATEK_MT8189_MMSYS_H
+#define __SOC_MEDIATEK_MT8189_MMSYS_H
+
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MT8189_MMSYS_SW0_RST_B				0x190
+
+#define MT8189_MMSYS_GCE_EVENT_SEL			0x308
+#define MT8189_EVENT_GCE_EN					(BIT(0) | BIT(1))
+
+#define MT8189_DISP_OVL0_OUT0_MOUT_EN 0xc10
+	#define MT8189_MOUT_DISP_OVL0_TO_DISP_RSZ0 BIT(0)
+	#define MT8189_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(1)
+	#define MT8189_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(2)
+
+#define MT8189_DISP_OVL1_OUT0_MOUT_EN 0xc14
+	#define MT8189_MOUT_DISP_OVL1_TO_DISP_RSZ1 BIT(0)
+	#define MT8189_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(1)
+	#define MT8189_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(2)
+#define MT8189_DISP_OVL_OUT0_MOUT_MASK 0x7
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR0_MOUT_EN 0xc74
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_DISP_DSC_WRAP0_0 BIT(0)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_DISP_DSC_WRAP0_1 BIT(1)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_VPP_MERGE0_0 BIT(2)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_VPP_MERGE0_1  BIT(3)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_COMP_OUT_CROSSBAR4 BIT(4)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR0_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR1_MOUT_EN 0xc78
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_DISP_DSC_WRAP0_0 BIT(0)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_DISP_DSC_WRAP0_1 BIT(1)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_VPP_MERGE0_0 BIT(2)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_VPP_MERGE0_1  BIT(3)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR4 BIT(4)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR2_MOUT_EN 0xc7c
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_DISP_DSC_WRAP0_0 BIT(0)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_DISP_DSC_WRAP0_1 BIT(1)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_VPP_MERGE0_0 BIT(2)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_VPP_MERGE0_1  BIT(3)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_COMP_OUT_CROSSBAR4 BIT(4)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR2_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR3_MOUT_EN 0xc80
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_0 BIT(0)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_1 BIT(1)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_0 BIT(2)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_1  BIT(3)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR4 BIT(4)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR4_MOUT_EN 0xc84
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_DISP_DSC_WRAP0_0 BIT(0)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_DISP_DSC_WRAP0_1 BIT(1)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_VPP_MERGE0_0 BIT(2)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_VPP_MERGE0_1  BIT(3)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR4 BIT(4)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR5 BIT(5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR5_MOUT_EN 0xc88
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_DISP_DSC_WRAP0_0 BIT(0)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_DISP_DSC_WRAP0_1 BIT(1)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_VPP_MERGE0_0 BIT(2)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_VPP_MERGE0_1  BIT(3)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_COMP_OUT_CROSSBAR4 BIT(4)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR5_TO_COMP_OUT_CROSSBAR5 BIT(5)
+#define MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK 0x3f
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR0_SEL_IN 0xc8c
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER0 (0)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL0_OUT0_MOUT (2)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER1 (3)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR1_SEL_IN 0xc90
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_DITER0 (0)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_OVL0_OUT0_MOUT (2)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_DITER1 (3)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR1_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR2_SEL_IN 0xc94
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_DITER0 (0)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_OVL0_OUT0_MOUT (2)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_DITER1 (3)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR2_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR3_SEL_IN 0xc98
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_DITER0 (0)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_FROM_DISP_OVL0_OUT0_MOUT (2)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_DITER1 (3)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR3_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR4_SEL_IN 0xc9c
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_DITER0 (0)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_OVL0_OUT0_MOUT (2)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_DITER1 (3)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR4_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_OVL_PQ_OUT_CROSSBAR5_SEL_IN 0xca0
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_DITER0 (0)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_RDMA0_RSZ0_SOUT (1)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_OVL0_OUT0_MOUT (2)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_DITER1 (3)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_RDMA1_RSZ1_SOUT (4)
+	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR5_FROM_DISP_OVL1_OUT0_MOUT (5)
+
+#define MT8189_COMP_OUT_CROSSBAR0_MOUT_EN 0xd70
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DSI0 BIT(0)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DVO0 BIT(1)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_DVO1 BIT(2)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DPI0 BIT(3)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_WDMA0 BIT(4)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR0_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR1_MOUT_EN 0xd74
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DSI0 BIT(0)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DVO0 BIT(1)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_DVO1 BIT(2)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DPI0 BIT(3)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_WDMA0 BIT(4)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR1_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR2_MOUT_EN 0xd78
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DSI0 BIT(0)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DVO0 BIT(1)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_DVO1 BIT(2)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DPI0 BIT(3)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_WDMA0 BIT(4)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR2_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR3_MOUT_EN 0xd7c
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DSI0 BIT(0)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DVO0 BIT(1)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_DVO1 BIT(2)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DPI0 BIT(3)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_WDMA0 BIT(4)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR3_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR4_MOUT_EN 0xd80
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DSI0 BIT(0)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO0 BIT(1)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO1 BIT(2)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DPI0 BIT(3)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_WDMA0 BIT(4)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_WDMA1 BIT(5)
+
+#define MT8189_COMP_OUT_CROSSBAR5_MOUT_EN 0xd84
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DSI0 BIT(0)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO0 BIT(1)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO1 BIT(2)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DPI0 BIT(3)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_WDMA0 BIT(4)
+	#define MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_WDMA1 BIT(5)
+
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_0 BIT(0)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_DISP_DSC_WRAP0_1 BIT(1)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_0 BIT(2)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_VPP_MERGE0_1  BIT(3)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR4 BIT(4)
+	#define MT8189_MOUT_OVL_PQ_OUT_CROSSBAR3_TO_COMP_OUT_CROSSBAR5 BIT(5)
+#define MT8189_COMP_OUT_CROSSBAR_MOUT_MASK 0x3f
+
+#define MT8189_COMP_OUT_CROSSBAR0_SEL_IN 0xd88
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_DISP_DSC_WRAP0_0 (0)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_DISP_DSC_WRAP0_1 (1)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_VPP_MERGE0_0 (2)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_VPP_MERGE0_1 (3)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR0_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR1_SEL_IN 0xd8c
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_DISP_DSC_WRAP0_0 (0)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_DISP_DSC_WRAP0_1 (1)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_VPP_MERGE0_0 (2)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_VPP_MERGE0_1 (3)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR1_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR2_SEL_IN 0xd90
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_DISP_DSC_WRAP0_0 (0)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_DISP_DSC_WRAP0_1 (1)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_VPP_MERGE0_0 (2)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_VPP_MERGE0_1 (3)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR2_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR3_SEL_IN 0xd94
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_DISP_DSC_WRAP0_0 (0)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_DISP_DSC_WRAP0_1 (1)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_VPP_MERGE0_0 (2)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_VPP_MERGE0_1 (3)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR3_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR4_SEL_IN 0xd98
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_DISP_DSC_WRAP0_0 (0)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_DISP_DSC_WRAP0_1 (1)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_VPP_MERGE0_0 (2)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_VPP_MERGE0_1 (3)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR4_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_COMP_OUT_CROSSBAR5_SEL_IN 0xd9c
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_DISP_DSC_WRAP0_0 (0)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_DISP_DSC_WRAP0_1 (1)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_VPP_MERGE0_0 (2)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_VPP_MERGE0_1 (3)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_OVL_PQ_OUT_CROSSBAR4 (4)
+	#define MT8189_SEL_IN_COMP_OUT_CROSSBAR5_FROM_OVL_PQ_OUT_CROSSBAR5 (5)
+
+#define MT8189_DISP_RDMA0_RSZ0_SOUT_SEL 0xe00
+	#define MT8189_SOUT_DISP_RDMA0_RSZ0_TO_OVL_PQ_OUT_CROSSBAR1 (0)
+	#define MT8189_SOUT_DISP_RDMA0_RSZ0_TO_DISP_COLOR0 (1)
+
+#define MT8189_DISP_RDMA0_SEL_IN 0xe04
+	#define MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0_MOUT (0)
+	#define MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0_OUT0_MOUT (1)
+#define MT8189_DISP_RDMA_SEL_IN_MASK 0x1
+
+#define MT8189_DISP_RDMA1_RSZ1_SOUT_SEL 0xe08
+	#define MT8189_SOUT_DISP_RDMA1_RSZ1_TO_OVL_PQ_OUT_CROSSBAR4 (0)
+	#define MT8189_SOUT_DISP_RDMA1_RSZ1_TO_DISP_COLOR1 (1)
+
+#define MT8189_DISP_RDMA1_SEL_IN 0xe0c
+	#define MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_RSZ1_MOUT (0)
+	#define MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_OVL1_OUT0_MOUT (1)
+
+#define MT8189_DISP_OVL0_BGCLR_MOUT_EN 0xe24
+	#define MT8189_MOUT_OVL_TO_BLENDOUT BIT(0)
+	#define MT8189_MOUT_OVL_TO_BG BIT(1)
+
+#define MT8189_DISP_OVL1_BGCLR_MOUT_EN 0xe28
+#define MT8189_DISP_OVL_BGCLR_MOUT_MASK 0x3
+
+static const struct mtk_mmsys_routes mmsys_mt8189_routing_table[] = {
+	/* main path */
+	MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		    MT8189_DISP_OVL0_BGCLR_MOUT_EN, MT8189_DISP_OVL_BGCLR_MOUT_MASK,
+		    MT8189_MOUT_OVL_TO_BLENDOUT),
+	MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		    MT8189_DISP_OVL0_OUT0_MOUT_EN, MT8189_DISP_OVL_OUT0_MOUT_MASK,
+		    MT8189_MOUT_DISP_OVL0_TO_DISP_RDMA0),
+	MMSYS_ROUTE(DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		    MT8189_DISP_RDMA0_SEL_IN, MT8189_DISP_RDMA_SEL_IN_MASK,
+		    MT8189_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0_OUT0_MOUT),
+	MMSYS_ROUTE(DDP_COMPONENT_RDMA0, DDP_COMPONENT_COMP0_OUT_CB4,
+		    MT8189_DISP_RDMA0_RSZ0_SOUT_SEL, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+		    MT8189_SOUT_DISP_RDMA0_RSZ0_TO_OVL_PQ_OUT_CROSSBAR1),
+	MMSYS_ROUTE(DDP_COMPONENT_RDMA0, DDP_COMPONENT_COMP0_OUT_CB4,
+		    MT8189_OVL_PQ_OUT_CROSSBAR1_MOUT_EN, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+		    MT8189_MOUT_OVL_PQ_OUT_CROSSBAR1_TO_COMP_OUT_CROSSBAR4),
+	MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB4, DDP_COMPONENT_DVO0,
+		    MT8189_COMP_OUT_CROSSBAR4_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MASK,
+		    MT8189_MOUT_COMP_OUT_CROSSBAR4_TO_DISP_DVO0),
+	/* ext path */
+	MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		    MT8189_DISP_OVL1_BGCLR_MOUT_EN, MT8189_DISP_OVL_BGCLR_MOUT_MASK,
+		    MT8189_MOUT_OVL_TO_BLENDOUT),
+	MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		    MT8189_DISP_OVL1_OUT0_MOUT_EN, MT8189_DISP_OVL_OUT0_MOUT_MASK,
+		    MT8189_MOUT_DISP_OVL1_TO_DISP_RDMA1),
+	MMSYS_ROUTE(DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		    MT8189_DISP_RDMA1_SEL_IN, MT8189_DISP_RDMA_SEL_IN_MASK,
+		    MT8189_SEL_IN_DISP_RDMA1_FROM_DISP_OVL1_OUT0_MOUT),
+	MMSYS_ROUTE(DDP_COMPONENT_RDMA1, DDP_COMPONENT_COMP0_OUT_CB5,
+		    MT8189_DISP_RDMA1_RSZ1_SOUT_SEL, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+		    MT8189_SOUT_DISP_RDMA1_RSZ1_TO_OVL_PQ_OUT_CROSSBAR4),
+	MMSYS_ROUTE(DDP_COMPONENT_RDMA1, DDP_COMPONENT_COMP0_OUT_CB5,
+		    MT8189_OVL_PQ_OUT_CROSSBAR4_MOUT_EN, MT8189_OVL_PQ_OUT_CROSSBAR_MOUT_MASK,
+		    MT8189_MOUT_OVL_PQ_OUT_CROSSBAR4_TO_COMP_OUT_CROSSBAR5),
+	MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB5, DDP_COMPONENT_DVO1,
+		    MT8189_COMP_OUT_CROSSBAR5_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MASK,
+		    MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DVO1),
+	MMSYS_ROUTE(DDP_COMPONENT_COMP0_OUT_CB5, DDP_COMPONENT_DSI0,
+		    MT8189_COMP_OUT_CROSSBAR5_MOUT_EN, MT8189_COMP_OUT_CROSSBAR_MOUT_MASK,
+		    MT8189_MOUT_COMP_OUT_CROSSBAR5_TO_DISP_DSI0),
+};
+
+static const struct mtk_mmsys_default mmsys_mt8189_disp0_default_table[] = {
+	{MT8189_MMSYS_GCE_EVENT_SEL, MT8189_EVENT_GCE_EN, GENMASK(1, 0)},
+};
+
+#endif /* __SOC_MEDIATEK_MT8189_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 3b490b993549..da5de4061007 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -22,6 +22,7 @@
 #include "mt8183-mmsys.h"
 #include "mt8186-mmsys.h"
 #include "mt8188-mmsys.h"
+#include "mt8189-mmsys.h"
 #include "mt8192-mmsys.h"
 #include "mt8195-mmsys.h"
 #include "mt8196-mmsys.h"
@@ -116,6 +117,16 @@ static const struct mtk_mmsys_driver_data mt8188_vppsys1_driver_data = {
 	.is_vppsys = true,
 };
 
+static const struct mtk_mmsys_driver_data mt8189_mmsys_driver_data = {
+	.clk_driver = "clk-mt8189-mmsys",
+	.routes = mmsys_mt8189_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8189_routing_table),
+	.def_config = mmsys_mt8189_disp0_default_table,
+	.num_def_config = ARRAY_SIZE(mmsys_mt8189_disp0_default_table),
+	.sw0_rst_offset = MT8189_MMSYS_SW0_RST_B,
+	.num_resets = 32,
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
@@ -668,6 +679,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 	{ .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
 	{ .compatible = "mediatek,mt8188-vppsys0", .data = &mt8188_vppsys0_driver_data },
 	{ .compatible = "mediatek,mt8188-vppsys1", .data = &mt8188_vppsys1_driver_data },
+	{ .compatible = "mediatek,mt8189-mmsys", .data = &mt8189_mmsys_driver_data },
 	{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
 	/* "mediatek,mt8195-mmsys" compatible is deprecated */
 	{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4a0b10567581..7d63b9f0899f 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_DSI2,
 	DDP_COMPONENT_DSI3,
 	DDP_COMPONENT_DVO0,
+	DDP_COMPONENT_DVO1,
 	DDP_COMPONENT_ETHDR_MIXER,
 	DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_MDP_RDMA0,
@@ -133,6 +134,10 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
+	DDP_COMPONENT_RSZ0,
+	DDP_COMPONENT_RSZ1,
+	DDP_COMPONENT_COMP0_OUT_CB4,
+	DDP_COMPONENT_COMP0_OUT_CB5,
 	DDP_COMPONENT_ID_MAX,
 };
 
-- 
2.46.0

Re: [PATCH v1 11/13] soc: mediatek: add mmsys support for MT8189

[AngeloGioacchino Del Regno]

Il 20/10/25 09:40, Xiandong Wang ha scritto:
> Add driver data for MT8189 and add the routing table for each mmsys.
> 
> Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
> ---
>   drivers/soc/mediatek/mt8189-mmsys.h    | 300 +++++++++++++++++++++++++
>   drivers/soc/mediatek/mtk-mmsys.c       |  12 +
>   include/linux/soc/mediatek/mtk-mmsys.h |   5 +
>   3 files changed, 317 insertions(+)
>   create mode 100644 drivers/soc/mediatek/mt8189-mmsys.h
> 
> diff --git a/drivers/soc/mediatek/mt8189-mmsys.h b/drivers/soc/mediatek/mt8189-mmsys.h
> new file mode 100644
> index 000000000000..31378b6ee100
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8189-mmsys.h
> @@ -0,0 +1,300 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2024 MediaTek Inc.
> + */
> +
> +#ifndef __SOC_MEDIATEK_MT8189_MMSYS_H
> +#define __SOC_MEDIATEK_MT8189_MMSYS_H
> +
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define MT8189_MMSYS_SW0_RST_B				0x190
> +
> +#define MT8189_MMSYS_GCE_EVENT_SEL			0x308
> +#define MT8189_EVENT_GCE_EN					(BIT(0) | BIT(1))
> +
> +#define MT8189_DISP_OVL0_OUT0_MOUT_EN 0xc10
> +	#define MT8189_MOUT_DISP_OVL0_TO_DISP_RSZ0 BIT(0)

two spaces are fine instead of a tab, makes things (just a little) more readable.

#define MT8189_DISP_OVL0_OUT0_MOUT_EN				0xc10
   #define MT8189_MOUT_DISP_OVL0_TO_DISP_RSZ0			BIT(0)

> +	#define MT8189_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(1)
> +	#define MT8189_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(2)
> +
> +#define MT8189_DISP_OVL1_OUT0_MOUT_EN 0xc14
> +	#define MT8189_MOUT_DISP_OVL1_TO_DISP_RSZ1 BIT(0)
> +	#define MT8189_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(1)
> +	#define MT8189_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(2)
> +#define MT8189_DISP_OVL_OUT0_MOUT_MASK 0x7
> +

..snip..

> +
> +#define MT8189_OVL_PQ_OUT_CROSSBAR0_SEL_IN 0xc8c
> +	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER0 (0)

Parenthesis are not needed on those numbers. Please drop ( ).

> +	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA0_RSZ0_SOUT (1)
> +	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL0_OUT0_MOUT (2)
> +	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_DITER1 (3)
> +	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_RDMA1_RSZ1_SOUT (4)
> +	#define MT8189_SEL_IN_OVL_PQ_OUT_CROSSBAR0_FROM_DISP_OVL1_OUT0_MOUT (5)
> +

Regards,
Angelo

[PATCH v1 12/13] drm/mediatek: Add support for mt8189 mmsys driver probe

[Xiandong Wang]

mmsys probe for mt8189

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c  |  2 ++
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c  | 40 ++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_ovl.h  |  2 ++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  8 +++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 39 +++++++++++++++++++++++
 5 files changed, 91 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index ac6620e10262..b83ecd5404c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -498,6 +498,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_UFOE]		= { MTK_DISP_UFOE,		0, &ddp_ufoe },
 	[DDP_COMPONENT_WDMA0]		= { MTK_DISP_WDMA,		0, NULL },
 	[DDP_COMPONENT_WDMA1]		= { MTK_DISP_WDMA,		1, NULL },
+	[DDP_COMPONENT_COMP0_OUT_CB4]	= { MTK_DISP_VIRTUAL,		-1, NULL },
+	[DDP_COMPONENT_COMP0_OUT_CB5]	= { MTK_DISP_VIRTUAL,		-1, NULL },
 };
 
 static bool mtk_ddp_comp_find(struct device *dev,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 7cd3978beb98..f1fa1f1c3ff0 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -110,6 +110,32 @@ const u32 mt8173_ovl_formats[] = {
 
 const size_t mt8173_ovl_formats_len = ARRAY_SIZE(mt8173_ovl_formats);
 
+const u32 mt8189_ovl_formats[] = {
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_BGRX8888,
+	DRM_FORMAT_BGRA8888,
+	DRM_FORMAT_BGRX1010102,
+	DRM_FORMAT_BGRA1010102,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_RGBA8888,
+	DRM_FORMAT_RGBX1010102,
+	DRM_FORMAT_RGBA1010102,
+	DRM_FORMAT_RGB888,
+	DRM_FORMAT_BGR888,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_YUYV,
+};
+
+const size_t mt8189_ovl_formats_len = ARRAY_SIZE(mt8189_ovl_formats);
+
 const u32 mt8195_ovl_formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
@@ -779,6 +805,18 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
 	.num_formats = mt8173_ovl_formats_len,
 };
 
+static const struct mtk_disp_ovl_data mt8189_ovl_driver_data = {
+	.addr = DISP_REG_OVL_ADDR_MT8173,
+	.gmc_bits = 10,
+	.layer_nr = 4,
+	.fmt_rgb565_is_0 = true,
+	.smi_id_en = true,
+	.supports_afbc = true,
+	.formats = mt8189_formats,
+	.num_formats = ARRAY_SIZE(mt8189_formats),
+	.supports_clrfmt_ext = true,
+};
+
 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
 	.addr = DISP_REG_OVL_ADDR_MT8173,
 	.gmc_bits = 10,
@@ -823,6 +861,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
 	  .data = &mt8183_ovl_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
 	  .data = &mt8183_ovl_2l_driver_data},
+	{ .compatible = "mediatek,mt8189-disp-ovl",
+	  .data = &mt8189_ovl_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-ovl",
 	  .data = &mt8192_ovl_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
index 431567538eb5..675254e786d4 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
@@ -16,6 +16,8 @@
 
 extern const u32 mt8173_ovl_formats[];
 extern const size_t mt8173_ovl_formats_len;
+extern const u32 mt8189_ovl_formats[];
+extern const size_t mt8189_ovl_formats_len;
 extern const u32 mt8195_ovl_formats[];
 extern const size_t mt8195_ovl_formats_len;
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index c9d41d75e7f2..593d9d144218 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -394,6 +394,12 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
 
+static const struct mtk_disp_rdma_data mt8189_rdma_driver_data = {
+	.fifo_size = 1920,
+	.formats = mt8173_formats,
+	.num_formats = ARRAY_SIZE(mt8173_formats),
+};
+
 static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
 	.fifo_size = 1920,
 	.formats = mt8173_formats,
@@ -407,6 +413,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
+	{ .compatible = "mediatek,mt8189-disp-rdma",
+	  .data = &mt8189_rdma_driver_data},
 	{ .compatible = "mediatek,mt8195-disp-rdma",
 	  .data = &mt8195_rdma_driver_data},
 	{},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 4c19cffafd0f..9e6d949e5d17 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -187,11 +187,27 @@ static const unsigned int mt8188_mtk_ddp_main[] = {
 	DDP_COMPONENT_DITHER0,
 };
 
+static const unsigned int mt8189_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COMP0_OUT_CB4,
+};
+
+static const unsigned int mt8189_mtk_ddp_ext[] = {
+	DDP_COMPONENT_OVL1,
+	DDP_COMPONENT_RDMA1,
+	DDP_COMPONENT_COMP0_OUT_CB5,
+};
+
 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
 	{0, DDP_COMPONENT_DP_INTF0},
 	{0, DDP_COMPONENT_DSI0},
 };
 
+static const struct mtk_drm_route mt8189_mtk_ddp_ext_routes[] = {
+	{1, DDP_COMPONENT_DSI0},
+};
+
 static const struct mtk_drm_route mt8196_mtk_ddp_routes[] = {
 	{2, DDP_COMPONENT_DSI0},
 };
@@ -347,6 +363,19 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.min_height = 1,
 };
 
+static const struct mtk_mmsys_driver_data mt8189_mmsys_driver_data = {
+	.main_path = mt8189_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8189_mtk_ddp_main),
+	.mmsys_dev_num = 1,
+	.ext_path = mt8189_mtk_ddp_ext,
+	.ext_len = ARRAY_SIZE(mt8189_mtk_ddp_ext),
+	.conn_routes = mt8189_mtk_ddp_ext_routes,
+	.num_conn_routes = ARRAY_SIZE(mt8189_mtk_ddp_ext_routes),
+	.max_width = 8191,
+	.min_width = 1,
+	.min_height = 1,
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.main_path = mt8192_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -454,6 +483,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8188_vdosys0_driver_data},
 	{ .compatible = "mediatek,mt8188-vdosys1",
 	  .data = &mt8195_vdosys1_driver_data},
+	{ .compatible = "mediatek,mt8189-mmsys",
+	  .data = &mt8189_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8195-mmsys",
@@ -883,6 +914,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8188-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8189-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX},
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8195-disp-mutex",
@@ -899,6 +932,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_OVL },
 	{ .compatible = "mediatek,mt8183-disp-ovl",
 	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8189-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL},
 	{ .compatible = "mediatek,mt8192-disp-ovl",
 	  .data = (void *)MTK_DISP_OVL },
 	{ .compatible = "mediatek,mt8195-disp-ovl",
@@ -923,6 +958,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8189-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8195-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
@@ -957,6 +994,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DSI },
 	{ .compatible = "mediatek,mt8188-dsi",
 	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8189-dsi",
+	  .data = (void *)MTK_DSI },
 	{ }
 };
 
-- 
2.46.0

Re: [PATCH v1 12/13] drm/mediatek: Add support for mt8189 mmsys driver probe

[AngeloGioacchino Del Regno]

Il 20/10/25 09:40, Xiandong Wang ha scritto:
> mmsys probe for mt8189
> 
> Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
> ---
>   drivers/gpu/drm/mediatek/mtk_ddp_comp.c  |  2 ++
>   drivers/gpu/drm/mediatek/mtk_disp_ovl.c  | 40 ++++++++++++++++++++++++
>   drivers/gpu/drm/mediatek/mtk_disp_ovl.h  |  2 ++
>   drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  8 +++++
>   drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 39 +++++++++++++++++++++++
>   5 files changed, 91 insertions(+)
> 

..snip..

> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 4c19cffafd0f..9e6d949e5d17 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -187,11 +187,27 @@ static const unsigned int mt8188_mtk_ddp_main[] = {
>   	DDP_COMPONENT_DITHER0,
>   };
>   
> +static const unsigned int mt8189_mtk_ddp_main[] = {
> +	DDP_COMPONENT_OVL0,
> +	DDP_COMPONENT_RDMA0,
> +	DDP_COMPONENT_COMP0_OUT_CB4,
> +};
> +
> +static const unsigned int mt8189_mtk_ddp_ext[] = {
> +	DDP_COMPONENT_OVL1,
> +	DDP_COMPONENT_RDMA1,
> +	DDP_COMPONENT_COMP0_OUT_CB5,
> +};

NACK. Please use OF Graph only. Stop hardcoding paths in mediatek-drm.

Regards,
Angelo

[PATCH v1 13/13] soc: mediatek: mutex: add mutex support for MT8189

[Xiandong Wang]

Add mutex support for the main and external displays in MT8189:
- Introduce a new DVO1 output component for the new mutex
  settings of MT8189.
- Add a need_sof_mof flag to configure both SOF and MOD settings
  for the output component.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 88 ++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c48983d8a6cd..743c4b93a39e 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -177,6 +177,48 @@
 #define MT8188_MUTEX_MOD_DISP1_DPI1		38
 #define MT8188_MUTEX_MOD_DISP1_DP_INTF1		39
 
+#define MT8189_DISP_MUTEX0_MOD0			0x30
+#define MT8189_DISP_MUTEX0_MOD1			0x34
+#define MT8189_DISP_MUTEX0_SOF			0x2C
+#define MT8189_MUTEX_MOD_DISP_OVL0		0
+#define MT8189_MUTEX_MOD_DISP_OVL1		1
+#define MT8189_MUTEX_MOD_DISP_RSZ0		2
+#define MT8189_MUTEX_MOD_DISP_RSZ1		3
+#define MT8189_MUTEX_MOD_DISP_RDMA0		4
+#define MT8189_MUTEX_MOD_DISP_RDMA1		5
+#define MT8189_MUTEX_MOD_DISP_COLOR0		6
+#define MT8189_MUTEX_MOD_DISP_COLOR1		4
+#define MT8189_MUTEX_MOD_DISP_CCORR0		8
+#define MT8189_MUTEX_MOD_DISP_CCORR1		9
+#define MT8189_MUTEX_MOD_DISP_CCORR2		10
+#define MT8189_MUTEX_MOD_DISP_CCORR3		11
+#define MT8189_MUTEX_MOD_DISP_AAL0		12
+#define MT8189_MUTEX_MOD_DISP_AAL1		13
+#define MT8189_MUTEX_MOD_DISP_GAMMA0		14
+#define MT8189_MUTEX_MOD_DISP_GAMMA1		15
+#define MT8189_MUTEX_MOD_DISP_DITHER0		16
+#define MT8189_MUTEX_MOD_DISP_DITHER1		17
+#define MT8189_MUTEX_MOD_DISP_VPP_MERGE0	18
+#define MT8189_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	19
+#define MT8189_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	20
+#define MT8189_MUTEX_MOD_DISP_DVO0		21
+#define MT8189_MUTEX_MOD_DISP_DSI0		22
+#define MT8189_MUTEX_MOD_DISP_DVO1		23
+#define MT8189_MUTEX_MOD_DISP_DPI0		24
+#define MT8189_MUTEX_MOD_DISP_WDMA0		25
+#define MT8189_MUTEX_MOD_DISP_WDMA1		26
+#define MT8189_MUTEX_MOD_DISP_PWM0		27
+#define MT8189_MUTEX_MOD_DISP_PWM1		28
+#define MT8189_MUTEX_MOD_ALL			0xff
+
+#define MT8189_MUTEX_SOF_SINGLE_MODE		0
+#define MT8189_MUTEX_SOF_DSI0			1
+#define MT8189_MUTEX_EOF_DSI0			(MT8189_MUTEX_SOF_DSI0 << 7)
+#define MT8189_MUTEX_SOF_DVO			5
+#define MT8189_MUTEX_EOF_DVO			(MT8189_MUTEX_SOF_DVO << 7)
+#define MT8189_MUTEX_SOF_DPTX			6
+#define MT8189_MUTEX_EOF_DPTX			(MT8189_MUTEX_SOF_DPTX << 7)
+
 #define MT8195_MUTEX_MOD_DISP_OVL0		0
 #define MT8195_MUTEX_MOD_DISP_WDMA0		1
 #define MT8195_MUTEX_MOD_DISP_RDMA0		2
@@ -554,6 +596,34 @@ static const u8 mt8188_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
 	[MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
 };
 
+static const unsigned int mt8189_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8189_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_OVL1] = MT8189_MUTEX_MOD_DISP_OVL1,
+	[DDP_COMPONENT_RSZ0] = MT8189_MUTEX_MOD_DISP_RSZ0,
+	[DDP_COMPONENT_RSZ1] = MT8189_MUTEX_MOD_DISP_RSZ1,
+	[DDP_COMPONENT_RDMA0] = MT8189_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_RDMA1] = MT8189_MUTEX_MOD_DISP_RDMA1,
+	[DDP_COMPONENT_COLOR0] = MT8189_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_COLOR1] = MT8189_MUTEX_MOD_DISP_COLOR1,
+	[DDP_COMPONENT_CCORR0] = MT8189_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_CCORR1] = MT8189_MUTEX_MOD_DISP_CCORR1,
+	[DDP_COMPONENT_AAL0] = MT8189_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_AAL1] = MT8189_MUTEX_MOD_DISP_AAL1,
+	[DDP_COMPONENT_GAMMA] = MT8189_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER0] = MT8189_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER1] = MT8189_MUTEX_MOD_DISP_DITHER1,
+	[DDP_COMPONENT_MERGE0] = MT8189_MUTEX_MOD_DISP_VPP_MERGE0,
+	[DDP_COMPONENT_DSC0] = MT8189_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DVO0] = MT8189_MUTEX_MOD_DISP_DVO0,
+	[DDP_COMPONENT_DVO1] = MT8189_MUTEX_MOD_DISP_DVO1,
+	[DDP_COMPONENT_DSI0] = MT8189_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_WDMA0] = MT8189_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_PWM0] = MT8189_MUTEX_MOD_DISP_PWM0,
+	[DDP_COMPONENT_COMP0_OUT_CB4] = MT8189_MUTEX_MOD_ALL,
+	[DDP_COMPONENT_COMP0_OUT_CB5] = MT8189_MUTEX_MOD_ALL,
+	[MT8189_MUTEX_MOD_DISP_PWM1] = MT8189_MUTEX_MOD_DISP_PWM1,
+};
+
 static const u8 mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
@@ -718,6 +788,14 @@ static const u16 mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 		MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
 };
 
+static const unsigned int mt8189_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MT8189_MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] =
+		MT8189_MUTEX_SOF_DSI0 | MT8189_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8189_MUTEX_SOF_DPTX | MT8189_MUTEX_EOF_DPTX,
+};
+
 static const u16 mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
@@ -812,6 +890,14 @@ static const struct mtk_mutex_data mt8188_vpp_mutex_driver_data = {
 	.mutex_table_mod = mt8188_mdp_mutex_table_mod,
 };
 
+static const struct mtk_mutex_data mt8189_mutex_driver_data = {
+	.mutex_mod = mt8189_mutex_mod,
+	.mutex_sof = mt8189_mutex_sof,
+	.mutex_mod_reg = MT8189_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8189_DISP_MUTEX0_SOF,
+	.need_sof_mod = true,
+};
+
 static const struct mtk_mutex_data mt8192_mutex_driver_data = {
 	.mutex_mod = mt8192_mutex_mod,
 	.mutex_sof = mt8183_mutex_sof,
@@ -903,6 +989,7 @@ static int mtk_mutex_get_output_comp_sof(enum mtk_ddp_comp_id id)
 	case DDP_COMPONENT_DPI1:
 		return MUTEX_SOF_DPI1;
 	case DDP_COMPONENT_DP_INTF0:
+	case DDP_COMPONENT_DVO1:
 		return MUTEX_SOF_DP_INTF0;
 	case DDP_COMPONENT_DP_INTF1:
 		return MUTEX_SOF_DP_INTF1;
@@ -1182,6 +1269,7 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data },
 	{ .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data },
 	{ .compatible = "mediatek,mt8188-vpp-mutex",  .data = &mt8188_vpp_mutex_driver_data },
+	{ .compatible = "mediatek,mt8189-disp-mutex", .data = &mt8189_mutex_driver_data },
 	{ .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data },
 	{ .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data },
 	{ .compatible = "mediatek,mt8195-vpp-mutex",  .data = &mt8195_vpp_mutex_driver_data },
-- 
2.46.0

Re: [PATCH v1 13/13] soc: mediatek: mutex: add mutex support for MT8189

[AngeloGioacchino Del Regno]

Il 20/10/25 09:40, Xiandong Wang ha scritto:
> Add mutex support for the main and external displays in MT8189:
> - Introduce a new DVO1 output component for the new mutex
>    settings of MT8189.
> - Add a need_sof_mof flag to configure both SOF and MOD settings
>    for the output component.
> 
> Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>