From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B72D25A2B5 for ; Mon, 20 Oct 2025 11:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760958706; cv=none; b=lSNu2gXedWKleL+joJbE6JyPt8ENqUvxbngOkx4WNcXDXn3MKUyix3O3Wu3ts8CHNdMoOOH8Dii5GdSTjPLTF2vp3pC6Al+c12/r+RXAmkJBiHyOgBjx7T4gpUsSrmDjKVXuCcT+4v4BtY/8V6Zt+BqRsmWaty1wm1ucoYez+no= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760958706; c=relaxed/simple; bh=crtsan/85sYEtw+IXIdIx1+xhGDC/R5MM3pBFiVg8CU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=To9q+BoTMKB88K4hbr4dVtFlSUfcrxsLdexD9fQWBTiFOMlNFFWxkj6RmtDjYjS945AeHdg3b/oTZIHziJ255Godk4+v3z5Dmo45DIjtiNx2TrjTCRP06QYrd2KxjTK5f9rvQ93jUan+tiiGfgbD2L+U+MAh44kkQJmTuyrkjLM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eBLBrUou; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eBLBrUou" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-3f99ac9acc4so3871374f8f.3 for ; Mon, 20 Oct 2025 04:11:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760958701; x=1761563501; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ET/WdgCX7blN4pSkYOyw5+NcHdAYpJFzGJ0hMhYQ6fk=; b=eBLBrUou5ESVx0C5jUOarV6hMOLQNpstgEby4j08LQkas9V6rSK3sAC8rFAU56Czco oLFAl01/GO09rqu2eyXkundb6kGDTbFXGC4Z3Pevylx8ONoDijxtVvoXnCufXoNRnpJh xlYDZo6hkOIrHvrkdVM/PLtGer8nNJoSmGOoZVtLSwm3xoCbffywppQtsre8Eizb+MF1 Ub1qoxaT9dX4WW2F7abx9ZG0sJsYaRQOkvCC7v+SDMN1V58OpzapZwm6EoQd+rk/POS4 qdmC1Tu+xOXPOKXs75dqKBJUbHCAHLqykd2D4xT2RKmEKK3gZCOJ8SCyknKcsPuiv3p5 ZcfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760958701; x=1761563501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ET/WdgCX7blN4pSkYOyw5+NcHdAYpJFzGJ0hMhYQ6fk=; b=AKmYYJ4Cysv+HCYSzqf+Iof6X5ThsZWJnWpoTlW4ozCHY+9By0RshpD1AnFRxu0i7s WJVCi40Qf0GiqXa8zLfpA6Fx9SnhM4Ikdo68rsiDVz7tTAmBx7A+Ekn9COo1U/YlrxGP VjVLCLPeWzS4xkyULKodeec5OhRGvV8iuKJ71gJPTbyHiBONE3TMU2kRP3TIyybej98o 3Z4+V5TT+zKcgPPNYI4wd5BfUhmvGja/MDGypWoSD+/vpQVtQi+vNfV+giob3PV3g457 qTQl2j47nerpJp4a2oCiGM/UguUuudXU0koIF/Fhm+XWAsB1mLWku0/xz2qcQgH1oMxj q7pA== X-Forwarded-Encrypted: i=1; AJvYcCU4O9RHkvBqqC5gJp6ORsldft67HhzcnahVYZ6GuqKGOTKC5XFOSTotAtGZodBvdjK3vo/F0YtLrA2G@vger.kernel.org X-Gm-Message-State: AOJu0YyEDk4JG+0uzi9LQ+XxTbh8kUfVj9XcXjcSnVnLEQ0PiCThp+tt cIiCd6NO9hxC7te3Oi7+f5MsCyD6Ngdv9bc/vdiN0HuBhegTxQvf/fdN X-Gm-Gg: ASbGnctX/NPhjnzql6w21eD+ZCMkvydc7wJc4c9OHQeJT7kimEjFpiogd2xBHRzo3kz FktLD1irI5mhf+VJQwoPANvdDJA95vmiCf6YbCxssfH6GgLKrueibSYj9su1xaYDuC6J37WEnQi NhB3bJDj6Vq6nXK/uZPQikbyydSBJn7GBqijGV476IuSbyAV6ZUe7Tz73dYEVfPuII4SVmM6eLC GJN/nqRNVwI6DTSGiqMpCj2PxX0HeUU6a0FWciW/OO3NfwgY0Ne+0xBetRFXMVWtvGZEzcrKfqa uPnjXRDSc7FcHr4F6HqEyqUb/epnLx9GR910TPpxvV9shvFnC7i75E0rNig/7u4cQ1YIzbTiPLa BlxISPTSt6sW8GQ7TXL+BTcuJuS+JBHest1JnAoB5SmfPcPhB2IwlLAxYVS7NOwIjYfoNhvlKQx 2809c/Ng10RLd4tkIZ31+qlYH1IxjOfPdgcO1lYZfBEZg= X-Google-Smtp-Source: AGHT+IGsJGvpzKiDD8jBDErgrAbR7/9scZteiyrQ3aNod93FKhU/9cKG3+ipZMkoOjySRQFgqGSHww== X-Received: by 2002:a05:6000:2389:b0:427:151:3db6 with SMTP id ffacd0b85a97d-42704d8e226mr8837205f8f.24.1760958701102; Mon, 20 Oct 2025 04:11:41 -0700 (PDT) Received: from Ansuel-XPS24 (93-34-92-177.ip49.fastwebnet.it. [93.34.92.177]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-4283e7804f4sm12692219f8f.10.2025.10.20.04.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 04:11:40 -0700 (PDT) From: Christian Marangi To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: [PATCH v6 2/5] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Date: Mon, 20 Oct 2025 13:11:06 +0200 Message-ID: <20251020111121.31779-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251020111121.31779-1-ansuelsmth@gmail.com> References: <20251020111121.31779-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/mediatek-pcie.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml index fca6cb20d18b..0b8c78ec4f91 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - airoha,an7583-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -40,6 +41,12 @@ properties: - enum: [ obff_ck0, obff_ck1 ] - enum: [ pipe_ck0, pipe_ck1 ] + resets: + maxItems: 1 + + reset-names: + const: pcie-rst1 + interrupts: maxItems: 1 @@ -55,6 +62,17 @@ properties: power-domains: maxItems: 1 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 @@ -90,6 +108,33 @@ required: allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + compatible: + const: airoha,an7583-pcie + then: + properties: + reg-names: + const: port1 + + clocks: + maxItems: 1 + + clock-names: + const: sys_ck1 + + phy-names: + const: pcie-phy1 + + power-domain: false + + required: + - resets + - reset-names + - phys + - phy-names + - mediatek,pbus-csr + - if: properties: compatible: @@ -104,8 +149,14 @@ allOf: minItems: 2 maxItems: 2 + reset: false + + reset-names: false + power-domains: false + mediatek,pbus-csr: false + required: - phys - phy-names @@ -119,10 +170,16 @@ allOf: clocks: minItems: 6 + reset: false + + reset-names: false + phys: false phy-names: false + mediatek,pbus-csr: false + required: - power-domains @@ -135,6 +192,12 @@ allOf: clocks: minItems: 6 + reset: false + + reset-names: false + + mediatek,pbus-csr: false + required: - power-domains @@ -151,12 +214,18 @@ allOf: clock-names: maxItems: 1 + reset: false + + reset-names: false + phys: false phy-names: false power-domain: false + mediatek,pbus-csr: false + unevaluatedProperties: false examples: @@ -316,3 +385,54 @@ examples: }; }; }; + + # AN7583 + - | + #include + #include + #include + + soc_3 { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1fa92000 { + compatible = "airoha,an7583-pcie"; + device_type = "pci"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + + reg = <0x0 0x1fa92000 0x0 0x1670>; + reg-names = "port1"; + + clocks = <&scuclk EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + + phys = <&pciephy>; + phy-names = "pcie-phy1"; + + ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>; + + resets = <&scuclk>; /* AN7583_PCIE1_RST */ + reset-names = "pcie-rst1"; + + mediatek,pbus-csr = <&pbus_csr 0x8 0xc>; + + interrupts = ; + interrupt-names = "pcie_irq"; + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1_4: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; -- 2.51.0