* [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90
@ 2025-10-21 9:41 Junhui Liu
2025-10-21 9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
` (13 more replies)
0 siblings, 14 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Krzysztof Kozlowski, Conor Dooley
This introduces initial support for the Anlogic DR1V90 SoC [1] and the
Milianke MLKPAI-FS01 [2] board.
The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
the first platforms based on this SoC, with UART1 routed to a Type-C
interface for console access.
Tested on the Milianke MLKPAI-FS01 board with both the vendor's OpenSBI
and the not-yet-upstreamed mainline OpenSBI [4], as well as the vendor’s
U-Boot. Because the vendor’s OpenSBI is loaded at 0x1f300000, we have
to additionally reserve the DRAM region 0x1fe00000–0x1fffffff to prevent
overlap if using vendor's OpenSBI.
Link: https://www.anlogic.com/product/fpga/saldragon/dr1 [1]
Link: https://www.milianke.com/product-item-104.html [2]
Link: https://nucleisys.com/product/900.php [3]
Link: https://github.com/pigmoral/opensbi/tree/dr1v90 [4]
---
Changes in v3:
- Update DT binding to use ACLINT instead of CLINT
- Drop MAINTAINERS patch
- Rebase on v6.18-rc1
- Link to v2: https://lore.kernel.org/r/20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech
Changes in v2:
- Add MAINTAINERS entry for the DR1V90 platform
- Remove the riscv,isa property of cpu and reorder propertyies
- Fix clint base address in the dtsi
- Change the memory node to cover the full 512MB RAM in board dts
- Link to v1: https://lore.kernel.org/r/20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech
---
Junhui Liu (13):
dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
dt-bindings: riscv: Add Nuclei UX900 compatibles
dt-bindings: riscv: Add Anlogic DR1V90
dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
irqchip/aclint-sswi: Add Nuclei UX900 support
riscv: Add Anlogic SoC famly Kconfig support
riscv: dts: Add initial Anlogic DR1V90 SoC device tree
riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
riscv: defconfig: Enable Anlogic SoC
.../interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
.../thead,c900-aclint-mswi.yaml | 17 ++--
.../thead,c900-aclint-sswi.yaml | 4 +
.../devicetree/bindings/riscv/anlogic.yaml | 27 ++++++
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
.../bindings/serial/snps-dw-apb-uart.yaml | 1 +
.../bindings/timer/thead,c900-aclint-mtimer.yaml | 17 ++--
.../devicetree/bindings/vendor-prefixes.yaml | 6 ++
arch/riscv/Kconfig.socs | 5 ++
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/anlogic/Makefile | 2 +
arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++
arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 100 +++++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
drivers/irqchip/irq-aclint-sswi.c | 3 +-
15 files changed, 201 insertions(+), 13 deletions(-)
---
base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
change-id: 20250710-dr1v90-basic-dt-352e9ae5acb8
Best regards,
--
Junhui Liu <junhui.liu@pigmoral.tech>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
` (12 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Krzysztof Kozlowski
Add vendor prefixes for "anlogic", "milianke" and "nuclei". These are
required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC
from Anlogic, which uses a processor core designed by Nuclei.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index f1d1882009ba9e80127bae0151af157879fe3070..23e74b96bfb78cff5cf5fc7e48de81092b81b9da 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -132,6 +132,8 @@ patternProperties:
description: Anbernic
"^andestech,.*":
description: Andes Technology Corporation
+ "^anlogic,.*":
+ description: Shanghai Anlogic Infotech Co., Ltd.
"^anvo,.*":
description: Anvo-Systems Dresden GmbH
"^aoly,.*":
@@ -1023,6 +1025,8 @@ patternProperties:
description: MikroElektronika d.o.o.
"^mikrotik,.*":
description: MikroTik
+ "^milianke,.*":
+ description: Changzhou Milianke Electronic Technology Co., Ltd
"^milkv,.*":
description: MilkV Technology Co., Ltd
"^miniand,.*":
@@ -1140,6 +1144,8 @@ patternProperties:
description: Novatek
"^novtech,.*":
description: NovTech, Inc.
+ "^nuclei,.*":
+ description: Nuclei System Technology
"^numonyx,.*":
description: Numonyx (deprecated, use micron)
deprecated: true
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-10-21 9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 03/13] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
` (11 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Conor Dooley
The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC.
It features a 64-bit architecture and dual-issue, 9-stage pipeline, with
lots of optional extensions including V, K, Zc, and more.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 153d0dac57fb39d39219e138792f4cb831cb88dc..20b7c834559cb11d17dd4e4119787b88b85e19b0 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -48,6 +48,7 @@ properties:
- amd,mbv64
- andestech,ax45mp
- canaan,k210
+ - nuclei,ux900
- sifive,bullet0
- sifive,e5
- sifive,e7
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 03/13] dt-bindings: riscv: Add Anlogic DR1V90
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-10-21 9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-10-21 9:41 ` [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 04/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
` (10 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Krzysztof Kozlowski
Add Anlogic DR1V90 FPSoC, featuring a UX900 RISC-V core as the
processing system (PS) and 94,464 LUTs programmable logic (PL). It is
used by the Milianke MLKPAI-FS01 board, a SBC equipped with 512MB DDR3
memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot,
and 256Mbit Quad-SPI flash.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
.../devicetree/bindings/riscv/anlogic.yaml | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/anlogic.yaml b/Documentation/devicetree/bindings/riscv/anlogic.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..91b1526c99aa3ca9cc7b0e7978861408bd017049
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/anlogic.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/anlogic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Anlogic SoC-based boards
+
+maintainers:
+ - Junhui Liu <junhui.liu@pigmoral.tech>
+
+description:
+ Anlogic SoC-based boards
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - milianke,mlkpai-fs01
+ - const: anlogic,dr1v90
+
+additionalProperties: true
+
+...
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 04/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (2 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 03/13] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI Junhui Liu
` (9 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Conor Dooley
Add PLIC support for Anlogic DR1V90.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
.../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index f683d696909b9da302c53a64f6332f6251705c0d..9ebc483a05abcfcb162d9a8e4ad181ffe4c8732a 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -58,6 +58,7 @@ properties:
- const: andestech,nceplic100
- items:
- enum:
+ - anlogic,dr1v90-plic
- canaan,k210-plic
- eswin,eic7700-plic
- sifive,fu540-c000-plic
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (3 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 04/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-26 21:40 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI Junhui Liu
` (8 subsequent siblings)
13 siblings, 1 reply; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial
Add MSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
TIMER unit compliant with the ACLINT specification.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
.../interrupt-controller/thead,c900-aclint-mswi.yaml | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
index d6fb08a54167f21d454e33a1992e19b358d42dbd..62fd220e126e650e3800d8eee2a749fdbbde6108 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
@@ -4,18 +4,23 @@
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
+title: ACLINT Machine-level Software Interrupt Device
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
- items:
- - enum:
- - sophgo,sg2042-aclint-mswi
- - sophgo,sg2044-aclint-mswi
- - const: thead,c900-aclint-mswi
+ oneOf:
+ - items:
+ - enum:
+ - sophgo,sg2042-aclint-mswi
+ - sophgo,sg2044-aclint-mswi
+ - const: thead,c900-aclint-mswi
+ - items:
+ - enum:
+ - anlogic,dr1v90-aclint-mswi
+ - const: nuclei,ux900-aclint-mswi
reg:
maxItems: 1
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (4 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-26 21:42 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Junhui Liu
` (7 subsequent siblings)
13 siblings, 1 reply; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial
Add SSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
TIMER unit compliant with the ACLINT specification.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
.../bindings/interrupt-controller/thead,c900-aclint-sswi.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
index c1ab865fcd64f1347e7eda7f538c7669f55ff906..d02c6886283af790d75357f77a714558f68bb7d1 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
@@ -30,6 +30,10 @@ properties:
- const: thead,c900-aclint-sswi
- items:
- const: mips,p8700-aclint-sswi
+ - items:
+ - enum:
+ - anlogic,dr1v90-aclint-sswi
+ - const: nuclei,ux900-aclint-sswi
reg:
maxItems: 1
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (5 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-26 21:43 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 08/13] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
` (6 subsequent siblings)
13 siblings, 1 reply; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial
Add MTIMER support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with
a TIMER unit compliant with the ACLINT specification.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
.../bindings/timer/thead,c900-aclint-mtimer.yaml | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
index 4ed30efe40525f9e70b7f1b1dda1c833b0c3a40c..cf7c82e980f674afcf59fc726742dc4f49c1a820 100644
--- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
+++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
@@ -4,18 +4,23 @@
$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Sophgo CLINT Timer
+title: ACLINT Machine-level Timer Device
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
- items:
- - enum:
- - sophgo,sg2042-aclint-mtimer
- - sophgo,sg2044-aclint-mtimer
- - const: thead,c900-aclint-mtimer
+ oneOf:
+ - items:
+ - enum:
+ - sophgo,sg2042-aclint-mtimer
+ - sophgo,sg2044-aclint-mtimer
+ - const: thead,c900-aclint-mtimer
+ - items:
+ - enum:
+ - anlogic,dr1v90-aclint-mtimer
+ - const: nuclei,ux900-aclint-mtimer
reg:
items:
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 08/13] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (6 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 09/13] irqchip/aclint-sswi: Add Nuclei UX900 support Junhui Liu
` (5 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial
The Anlogic DR1V90 SoC integrates a UART controller compatible with
snps,dw-apb-uart, operating at a 50 MHz clock.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index cb9da6c97afcfd27a315414959b2b17beb4454cf..691bd0bac6be449516e213b550415acd37badad6 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -51,6 +51,7 @@ properties:
- const: renesas,rzn1-uart
- items:
- enum:
+ - anlogic,dr1v90-uart
- brcm,bcm11351-dw-apb-uart
- brcm,bcm21664-dw-apb-uart
- rockchip,px30-uart
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 09/13] irqchip/aclint-sswi: Add Nuclei UX900 support
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (7 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 08/13] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 10/13] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
` (4 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial
Reuse the generic ACLINT SSWI probe for Nuclei UX900 since it is
compliant with the ACLINT specification.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
drivers/irqchip/irq-aclint-sswi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint-sswi.c
index 93e28e9f281f64da4568be37dc57b414354c3f56..fee30f3bc5ac252b236078bf13df8c04e7327eaf 100644
--- a/drivers/irqchip/irq-aclint-sswi.c
+++ b/drivers/irqchip/irq-aclint-sswi.c
@@ -175,7 +175,8 @@ static int __init generic_aclint_sswi_early_probe(struct device_node *node,
{
return generic_aclint_sswi_probe(&node->fwnode);
}
-IRQCHIP_DECLARE(generic_aclint_sswi, "mips,p8700-aclint-sswi", generic_aclint_sswi_early_probe);
+IRQCHIP_DECLARE(mips_p8700_sswi, "mips,p8700-aclint-sswi", generic_aclint_sswi_early_probe);
+IRQCHIP_DECLARE(nuclei_ux900_sswi, "nuclei,ux900-aclint-sswi", generic_aclint_sswi_early_probe);
/* THEAD variant */
#define THEAD_C9XX_CSR_SXSTATUS 0x5c0
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 10/13] riscv: Add Anlogic SoC famly Kconfig support
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (8 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 09/13] irqchip/aclint-sswi: Add Nuclei UX900 support Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 11/13] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
` (3 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Conor Dooley
The first SoC in the Anlogic series is DR1V90, which contains a RISC-V
core from Nuclei.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 848e7149e4435ad3ca138b62bc3b3c8efb594a18..25f7e58cbf745a78b0e946749aa2a770dae3eb2b 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config ARCH_ANDES
help
This enables support for Andes SoC platform hardware.
+config ARCH_ANLOGIC
+ bool "Anlogic SoCs"
+ help
+ This enables support for Anlogic SoC platform hardware.
+
config ARCH_ESWIN
bool "ESWIN SoCs"
help
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 11/13] riscv: dts: Add initial Anlogic DR1V90 SoC device tree
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (9 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 10/13] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
` (2 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Conor Dooley
DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS
part and 94,464 LUTs for the PL part.
The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache
and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible
UART controllers.
Some basic information of the processor can be obtained by running a
simple application from nuclei-sdk [1]:
-----Nuclei RISC-V CPU Configuration Information-----
MARCHID: 0xc900
MIMPID: 0x20300
ISA: RV64 A B C D F I M P S U
MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-Safety-Mechanism DLEN=VLEN/2
ILM: 256 KB has-ecc
DLM: 256 KB has-ecc
ICACHE: 32 KB(set=256,way=2,lsize=64,ecc=1)
DCACHE: 32 KB(set=256,way=2,lsize=64,ecc=1)
TLB: MainTLB(set=32,way=2,entry=1,ecc=1) ITLB(entry=8) DTLB(entry=8)
IREGION: 0x68000000 128 MB
Unit Size Address
INFO 64KB 0x68000000
DEBUG 64KB 0x68010000
ECLIC 64KB 0x68020000
TIMER 64KB 0x68030000
PLIC 64MB 0x6c000000
INFO-Detail:
mpasize : 0
PPI: 0xf8000000 128 MB
-----End of Nuclei CPU INFO-----
Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application/baremetal/cpuinfo/main.c [1]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 100 ++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..a5d0765ade3231ece0afbe8835d95cd918a44ad9
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+/dts-v1/;
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Anlogic DR1V90";
+ compatible = "anlogic,dr1v90";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <800000000>;
+
+ cpu@0 {
+ compatible = "nuclei,ux900", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ reg = <0>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
+ "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
+ "zihintpause", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aclint_mswi: interrupt-controller@68031000 {
+ compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
+ reg = <0x0 0x68031000 0x0 0x4000>;
+ interrupts-extended = <&cpu0_intc 3>;
+ };
+
+ aclint_mtimer: timer@68035000 {
+ compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
+ reg = <0x0 0x68035000 0x0 0x8000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu0_intc 7>;
+ };
+
+ aclint_sswi: interrupt-controller@6803d000 {
+ compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
+ reg = <0x0 0x6803d000 0x0 0x3000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 1>;
+ };
+
+ plic: interrupt-controller@6c000000 {
+ compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0x6c000000 0x0 0x4000000>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ riscv,ndev = <150>;
+ };
+
+ uart0: serial@f8400000 {
+ compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xf8400000 0x0 0x1000>;
+ clock-frequency = <50000000>;
+ interrupts = <71>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@f8401000 {
+ compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xf8401000 0x0 0x1000>;
+ clock-frequency = <50000000>;
+ interrupts = <72>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (10 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 11/13] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-21 9:41 ` [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC Junhui Liu
2025-10-28 19:39 ` [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Conor Dooley
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Conor Dooley
Add support for the Milianke MLKPAI FS01 board based on the Anlogic
DR1V90 SoC. The board features 512MB of onboard memory, USB-C UART, 1GbE
RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash.
Currently, the board can boot to a console via UART1, which is connected
to the onboard serial chip and routed to the Type-C interface.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/anlogic/Makefile | 2 ++
arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++++++
3 files changed, 31 insertions(+)
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 3763d199c70ac659d00948241f4263dec62c548c..f99d38ee1aad255557ed6984f725f15df791690e 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
subdir-y += andes
+subdir-y += anlogic
subdir-y += canaan
subdir-y += eswin
subdir-y += microchip
diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anlogic/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..87f3b2f418cfa32012df5ae82d17262a9610f90c
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
new file mode 100644
index 0000000000000000000000000000000000000000..597407655efd2e74608dabb4559ab1239662cf41
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include "dr1v90.dtsi"
+
+/ {
+ model = "Milianke MLKPAI-FS01";
+ compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (11 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
@ 2025-10-21 9:41 ` Junhui Liu
2025-10-28 19:39 ` [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Conor Dooley
13 siblings, 0 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21 9:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
Conor Dooley
Enable Anlogic SoC config in defconfig to allow the default upstream
kernel booting on Milianke MLKPAI-FS01 board.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index fc2725cbca1879c181d179a3d59ac3a0ce206061..14b82f770efe1dc8abe1ef68b523023d89d1f4e5 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -23,6 +23,7 @@ CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
CONFIG_ARCH_ANDES=y
+CONFIG_ARCH_ANLOGIC=y
CONFIG_ARCH_MICROCHIP=y
CONFIG_ARCH_SIFIVE=y
CONFIG_ARCH_SOPHGO=y
--
2.51.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
2025-10-21 9:41 ` [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI Junhui Liu
@ 2025-10-26 21:40 ` Rob Herring (Arm)
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2025-10-26 21:40 UTC (permalink / raw)
To: Junhui Liu
Cc: Daniel Lezcano, Paul Walmsley, linux-serial, Thomas Gleixner,
Krzysztof Kozlowski, Greg Kroah-Hartman, linux-riscv, Albert Ou,
Jiri Slaby, Chen Wang, devicetree, Inochi Amaoto, linux-kernel,
Inochi Amaoto, Samuel Holland, sophgo, Paul Walmsley,
Conor Dooley, Alexandre Ghiti, Palmer Dabbelt, Palmer Dabbelt,
Conor Dooley
On Tue, 21 Oct 2025 17:41:40 +0800, Junhui Liu wrote:
> Add MSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
> TIMER unit compliant with the ACLINT specification.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> .../interrupt-controller/thead,c900-aclint-mswi.yaml | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
2025-10-21 9:41 ` [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI Junhui Liu
@ 2025-10-26 21:42 ` Rob Herring (Arm)
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2025-10-26 21:42 UTC (permalink / raw)
To: Junhui Liu
Cc: Chen Wang, sophgo, devicetree, linux-kernel, Inochi Amaoto,
Daniel Lezcano, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto,
Conor Dooley, linux-serial, Paul Walmsley, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Samuel Holland, Jiri Slaby,
Greg Kroah-Hartman, Paul Walmsley, linux-riscv, Albert Ou,
Alexandre Ghiti
On Tue, 21 Oct 2025 17:41:41 +0800, Junhui Liu wrote:
> Add SSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
> TIMER unit compliant with the ACLINT specification.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> .../bindings/interrupt-controller/thead,c900-aclint-sswi.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
2025-10-21 9:41 ` [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Junhui Liu
@ 2025-10-26 21:43 ` Rob Herring (Arm)
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2025-10-26 21:43 UTC (permalink / raw)
To: Junhui Liu
Cc: Inochi Amaoto, Samuel Holland, Jiri Slaby, linux-kernel,
Daniel Lezcano, Inochi Amaoto, Albert Ou, Paul Walmsley,
Alexandre Ghiti, sophgo, Thomas Gleixner, Greg Kroah-Hartman,
Palmer Dabbelt, Palmer Dabbelt, Conor Dooley, linux-riscv,
devicetree, linux-serial, Conor Dooley, Chen Wang, Paul Walmsley,
Krzysztof Kozlowski
On Tue, 21 Oct 2025 17:41:42 +0800, Junhui Liu wrote:
> Add MTIMER support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with
> a TIMER unit compliant with the ACLINT specification.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> .../bindings/timer/thead,c900-aclint-mtimer.yaml | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
` (12 preceding siblings ...)
2025-10-21 9:41 ` [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC Junhui Liu
@ 2025-10-28 19:39 ` Conor Dooley
2025-11-06 17:10 ` Conor Dooley
13 siblings, 1 reply; 19+ messages in thread
From: Conor Dooley @ 2025-10-28 19:39 UTC (permalink / raw)
To: Junhui Liu
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Thomas Gleixner,
Samuel Holland, Chen Wang, Inochi Amaoto, Daniel Lezcano,
Greg Kroah-Hartman, Jiri Slaby, devicetree, linux-kernel,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Inochi Amaoto, sophgo,
linux-serial, Krzysztof Kozlowski, Conor Dooley
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Thomas, Junhui,
On Tue, Oct 21, 2025 at 05:41:35PM +0800, Junhui Liu wrote:
> This introduces initial support for the Anlogic DR1V90 SoC [1] and the
> Milianke MLKPAI-FS01 [2] board.
>
> The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
> UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
> programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
> the first platforms based on this SoC, with UART1 routed to a Type-C
> interface for console access.
>
> Tested on the Milianke MLKPAI-FS01 board with both the vendor's OpenSBI
> and the not-yet-upstreamed mainline OpenSBI [4], as well as the vendor’s
> U-Boot. Because the vendor’s OpenSBI is loaded at 0x1f300000, we have
> to additionally reserve the DRAM region 0x1fe00000–0x1fffffff to prevent
> overlap if using vendor's OpenSBI.
>
> Link: https://www.anlogic.com/product/fpga/saldragon/dr1 [1]
> Link: https://www.milianke.com/product-item-104.html [2]
> Link: https://nucleisys.com/product/900.php [3]
> Link: https://github.com/pigmoral/opensbi/tree/dr1v90 [4]
> ---
> Changes in v3:
> - Update DT binding to use ACLINT instead of CLINT
> - Drop MAINTAINERS patch
> - Rebase on v6.18-rc1
> - Link to v2: https://lore.kernel.org/r/20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech
>
> Changes in v2:
> - Add MAINTAINERS entry for the DR1V90 platform
> - Remove the riscv,isa property of cpu and reorder propertyies
> - Fix clint base address in the dtsi
> - Change the memory node to cover the full 512MB RAM in board dts
> - Link to v1: https://lore.kernel.org/r/20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech
>
> ---
> Junhui Liu (13):
> dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
> dt-bindings: riscv: Add Nuclei UX900 compatibles
> dt-bindings: riscv: Add Anlogic DR1V90
> dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
> dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
> dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
> dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
> dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
> irqchip/aclint-sswi: Add Nuclei UX900 support
I'm happy enough with this series to grab it, but while I don't mind
taking some trivial binding changes with it, I don't want to take an
irqchip driver patch. Would you be able to apply the irqchip stuff
Thomas?
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90
2025-10-28 19:39 ` [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Conor Dooley
@ 2025-11-06 17:10 ` Conor Dooley
0 siblings, 0 replies; 19+ messages in thread
From: Conor Dooley @ 2025-11-06 17:10 UTC (permalink / raw)
To: Junhui Liu, tglx
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Thomas Gleixner,
Samuel Holland, Chen Wang, Inochi Amaoto, Daniel Lezcano,
Greg Kroah-Hartman, Jiri Slaby, devicetree, linux-kernel,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Inochi Amaoto, sophgo,
linux-serial, Krzysztof Kozlowski, Conor Dooley
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Thomas,
On Tue, Oct 28, 2025 at 07:39:07PM +0000, Conor Dooley wrote:
> Thomas, Junhui,
>
> On Tue, Oct 21, 2025 at 05:41:35PM +0800, Junhui Liu wrote:
> > This introduces initial support for the Anlogic DR1V90 SoC [1] and the
> > Milianke MLKPAI-FS01 [2] board.
> >
> > The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
> > UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
> > programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
> > the first platforms based on this SoC, with UART1 routed to a Type-C
> > interface for console access.
> >
> > Tested on the Milianke MLKPAI-FS01 board with both the vendor's OpenSBI
> > and the not-yet-upstreamed mainline OpenSBI [4], as well as the vendor’s
> > U-Boot. Because the vendor’s OpenSBI is loaded at 0x1f300000, we have
> > to additionally reserve the DRAM region 0x1fe00000–0x1fffffff to prevent
> > overlap if using vendor's OpenSBI.
> >
> > Link: https://www.anlogic.com/product/fpga/saldragon/dr1 [1]
> > Link: https://www.milianke.com/product-item-104.html [2]
> > Link: https://nucleisys.com/product/900.php [3]
> > Link: https://github.com/pigmoral/opensbi/tree/dr1v90 [4]
> > ---
> > Changes in v3:
> > - Update DT binding to use ACLINT instead of CLINT
> > - Drop MAINTAINERS patch
> > - Rebase on v6.18-rc1
> > - Link to v2: https://lore.kernel.org/r/20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech
> >
> > Changes in v2:
> > - Add MAINTAINERS entry for the DR1V90 platform
> > - Remove the riscv,isa property of cpu and reorder propertyies
> > - Fix clint base address in the dtsi
> > - Change the memory node to cover the full 512MB RAM in board dts
> > - Link to v1: https://lore.kernel.org/r/20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech
> >
> > ---
> > Junhui Liu (13):
> > dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
> > dt-bindings: riscv: Add Nuclei UX900 compatibles
> > dt-bindings: riscv: Add Anlogic DR1V90
> > dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
> > dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
> > dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
> > dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
> > dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
> > irqchip/aclint-sswi: Add Nuclei UX900 support
>
> I'm happy enough with this series to grab it, but while I don't mind
> taking some trivial binding changes with it, I don't want to take an
> irqchip driver patch. Would you be able to apply the irqchip stuff
> Thomas?
Could you pick up 4-6 and 9 here please?
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^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-11-06 17:10 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-10-21 9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-10-21 9:41 ` [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
2025-10-21 9:41 ` [PATCH v3 03/13] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
2025-10-21 9:41 ` [PATCH v3 04/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
2025-10-21 9:41 ` [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI Junhui Liu
2025-10-26 21:40 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI Junhui Liu
2025-10-26 21:42 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Junhui Liu
2025-10-26 21:43 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 08/13] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
2025-10-21 9:41 ` [PATCH v3 09/13] irqchip/aclint-sswi: Add Nuclei UX900 support Junhui Liu
2025-10-21 9:41 ` [PATCH v3 10/13] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
2025-10-21 9:41 ` [PATCH v3 11/13] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
2025-10-21 9:41 ` [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
2025-10-21 9:41 ` [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC Junhui Liu
2025-10-28 19:39 ` [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Conor Dooley
2025-11-06 17:10 ` Conor Dooley
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