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From: Junhui Liu <junhui.liu@pigmoral.tech>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>,
	Junhui Liu <junhui.liu@pigmoral.tech>,
	 Thomas Gleixner <tglx@linutronix.de>,
	 Samuel Holland <samuel.holland@sifive.com>,
	 Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	 Daniel Lezcano <daniel.lezcano@linaro.org>,
	 Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	 Jiri Slaby <jirislaby@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@sifive.com>,
	Conor Dooley <conor@kernel.org>,
	 linux-riscv@lists.infradead.org,
	Inochi Amaoto <inochiama@outlook.com>,
	 sophgo@lists.linux.dev, linux-serial@vger.kernel.org,
	 Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
Date: Tue, 21 Oct 2025 17:41:47 +0800	[thread overview]
Message-ID: <20251021-dr1v90-basic-dt-v3-12-5478db4f664a@pigmoral.tech> (raw)
In-Reply-To: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech>

Add support for the Milianke MLKPAI FS01 board based on the Anlogic
DR1V90 SoC. The board features 512MB of onboard memory, USB-C UART, 1GbE
RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash.

Currently, the board can boot to a console via UART1, which is connected
to the onboard serial chip and routed to the Type-C interface.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/anlogic/Makefile               |  2 ++
 arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++++++
 3 files changed, 31 insertions(+)

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 3763d199c70ac659d00948241f4263dec62c548c..f99d38ee1aad255557ed6984f725f15df791690e 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += allwinner
 subdir-y += andes
+subdir-y += anlogic
 subdir-y += canaan
 subdir-y += eswin
 subdir-y += microchip
diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anlogic/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..87f3b2f418cfa32012df5ae82d17262a9610f90c
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb
diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
new file mode 100644
index 0000000000000000000000000000000000000000..597407655efd2e74608dabb4559ab1239662cf41
--- /dev/null
+++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include "dr1v90.dtsi"
+
+/ {
+	model = "Milianke MLKPAI-FS01";
+	compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x20000000>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+};

-- 
2.51.1


  parent reply	other threads:[~2025-10-21  9:46 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-21  9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-10-21  9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-10-21  9:41 ` [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
2025-10-21  9:41 ` [PATCH v3 03/13] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
2025-10-21  9:41 ` [PATCH v3 04/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
2025-10-21  9:41 ` [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI Junhui Liu
2025-10-26 21:40   ` Rob Herring (Arm)
2025-10-21  9:41 ` [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI Junhui Liu
2025-10-26 21:42   ` Rob Herring (Arm)
2025-10-21  9:41 ` [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Junhui Liu
2025-10-26 21:43   ` Rob Herring (Arm)
2025-10-21  9:41 ` [PATCH v3 08/13] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
2025-10-21  9:41 ` [PATCH v3 09/13] irqchip/aclint-sswi: Add Nuclei UX900 support Junhui Liu
2025-10-21  9:41 ` [PATCH v3 10/13] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
2025-10-21  9:41 ` [PATCH v3 11/13] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
2025-10-21  9:41 ` Junhui Liu [this message]
2025-10-21  9:41 ` [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC Junhui Liu
2025-10-28 19:39 ` [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Conor Dooley
2025-11-06 17:10   ` Conor Dooley

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