From: Junhui Liu <junhui.liu@pigmoral.tech>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Junhui Liu <junhui.liu@pigmoral.tech>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
linux-riscv@lists.infradead.org,
Inochi Amaoto <inochiama@outlook.com>,
sophgo@lists.linux.dev, linux-serial@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v3 04/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
Date: Tue, 21 Oct 2025 17:41:39 +0800 [thread overview]
Message-ID: <20251021-dr1v90-basic-dt-v3-4-5478db4f664a@pigmoral.tech> (raw)
In-Reply-To: <20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech>
Add PLIC support for Anlogic DR1V90.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
.../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index f683d696909b9da302c53a64f6332f6251705c0d..9ebc483a05abcfcb162d9a8e4ad181ffe4c8732a 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -58,6 +58,7 @@ properties:
- const: andestech,nceplic100
- items:
- enum:
+ - anlogic,dr1v90-plic
- canaan,k210-plic
- eswin,eic7700-plic
- sifive,fu540-c000-plic
--
2.51.1
next prev parent reply other threads:[~2025-10-21 9:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-21 9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-10-21 9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-10-21 9:41 ` [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
2025-10-21 9:41 ` [PATCH v3 03/13] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
2025-10-21 9:41 ` Junhui Liu [this message]
2025-10-21 9:41 ` [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI Junhui Liu
2025-10-26 21:40 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI Junhui Liu
2025-10-26 21:42 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Junhui Liu
2025-10-26 21:43 ` Rob Herring (Arm)
2025-10-21 9:41 ` [PATCH v3 08/13] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
2025-10-21 9:41 ` [PATCH v3 09/13] irqchip/aclint-sswi: Add Nuclei UX900 support Junhui Liu
2025-10-21 9:41 ` [PATCH v3 10/13] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
2025-10-21 9:41 ` [PATCH v3 11/13] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
2025-10-21 9:41 ` [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
2025-10-21 9:41 ` [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC Junhui Liu
2025-10-28 19:39 ` [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Conor Dooley
2025-11-06 17:10 ` Conor Dooley
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