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* [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90
@ 2025-10-21  9:41 Junhui Liu
  2025-10-21  9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
                   ` (13 more replies)
  0 siblings, 14 replies; 19+ messages in thread
From: Junhui Liu @ 2025-10-21  9:41 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
	Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Junhui Liu,
	Thomas Gleixner, Samuel Holland, Chen Wang, Inochi Amaoto,
	Daniel Lezcano, Greg Kroah-Hartman, Jiri Slaby
  Cc: devicetree, linux-kernel, Paul Walmsley, Palmer Dabbelt,
	Conor Dooley, linux-riscv, Inochi Amaoto, sophgo, linux-serial,
	Krzysztof Kozlowski, Conor Dooley

This introduces initial support for the Anlogic DR1V90 SoC [1] and the
Milianke MLKPAI-FS01 [2] board.

The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
the first platforms based on this SoC, with UART1 routed to a Type-C
interface for console access.

Tested on the Milianke MLKPAI-FS01 board with both the vendor's OpenSBI
and the not-yet-upstreamed mainline OpenSBI [4], as well as the vendor’s
U-Boot. Because the vendor’s OpenSBI is loaded at 0x1f300000, we have
to additionally reserve the DRAM region 0x1fe00000–0x1fffffff to prevent
overlap if using vendor's OpenSBI.

Link: https://www.anlogic.com/product/fpga/saldragon/dr1 [1]
Link: https://www.milianke.com/product-item-104.html [2]
Link: https://nucleisys.com/product/900.php [3]
Link: https://github.com/pigmoral/opensbi/tree/dr1v90 [4]
---
Changes in v3:
- Update DT binding to use ACLINT instead of CLINT
- Drop MAINTAINERS patch
- Rebase on v6.18-rc1
- Link to v2: https://lore.kernel.org/r/20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech

Changes in v2:
- Add MAINTAINERS entry for the DR1V90 platform
- Remove the riscv,isa property of cpu and reorder propertyies
- Fix clint base address in the dtsi
- Change the memory node to cover the full 512MB RAM in board dts
- Link to v1: https://lore.kernel.org/r/20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech

---
Junhui Liu (13):
      dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
      dt-bindings: riscv: Add Nuclei UX900 compatibles
      dt-bindings: riscv: Add Anlogic DR1V90
      dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC
      dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
      dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI
      dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
      dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
      irqchip/aclint-sswi: Add Nuclei UX900 support
      riscv: Add Anlogic SoC famly Kconfig support
      riscv: dts: Add initial Anlogic DR1V90 SoC device tree
      riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
      riscv: defconfig: Enable Anlogic SoC

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 .../thead,c900-aclint-mswi.yaml                    |  17 ++--
 .../thead,c900-aclint-sswi.yaml                    |   4 +
 .../devicetree/bindings/riscv/anlogic.yaml         |  27 ++++++
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 .../bindings/serial/snps-dw-apb-uart.yaml          |   1 +
 .../bindings/timer/thead,c900-aclint-mtimer.yaml   |  17 ++--
 .../devicetree/bindings/vendor-prefixes.yaml       |   6 ++
 arch/riscv/Kconfig.socs                            |   5 ++
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/anlogic/Makefile               |   2 +
 arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts |  28 ++++++
 arch/riscv/boot/dts/anlogic/dr1v90.dtsi            | 100 +++++++++++++++++++++
 arch/riscv/configs/defconfig                       |   1 +
 drivers/irqchip/irq-aclint-sswi.c                  |   3 +-
 15 files changed, 201 insertions(+), 13 deletions(-)
---
base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
change-id: 20250710-dr1v90-basic-dt-352e9ae5acb8

Best regards,
-- 
Junhui Liu <junhui.liu@pigmoral.tech>


^ permalink raw reply	[flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-11-06 17:10 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-21  9:41 [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-10-21  9:41 ` [PATCH v3 01/13] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-10-21  9:41 ` [PATCH v3 02/13] dt-bindings: riscv: Add Nuclei UX900 compatibles Junhui Liu
2025-10-21  9:41 ` [PATCH v3 03/13] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
2025-10-21  9:41 ` [PATCH v3 04/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
2025-10-21  9:41 ` [PATCH v3 05/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI Junhui Liu
2025-10-26 21:40   ` Rob Herring (Arm)
2025-10-21  9:41 ` [PATCH v3 06/13] dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI Junhui Liu
2025-10-26 21:42   ` Rob Herring (Arm)
2025-10-21  9:41 ` [PATCH v3 07/13] dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER Junhui Liu
2025-10-26 21:43   ` Rob Herring (Arm)
2025-10-21  9:41 ` [PATCH v3 08/13] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
2025-10-21  9:41 ` [PATCH v3 09/13] irqchip/aclint-sswi: Add Nuclei UX900 support Junhui Liu
2025-10-21  9:41 ` [PATCH v3 10/13] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
2025-10-21  9:41 ` [PATCH v3 11/13] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
2025-10-21  9:41 ` [PATCH v3 12/13] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
2025-10-21  9:41 ` [PATCH v3 13/13] riscv: defconfig: Enable Anlogic SoC Junhui Liu
2025-10-28 19:39 ` [PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90 Conor Dooley
2025-11-06 17:10   ` Conor Dooley

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